T7024-TRQ

T7024 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Single 3-V Supply Voltage  High Power-added Efficient Power Amplifier (Pout Typically 23 dBm)  Ramp-controlled Output Power  Low-noise Preamplifier (NF Typically 2.1 dB)  Biasing for External PIN Diode T/R Switch  Current-saving Standby Mode  Few External Components  Packages: – PSSO20 – QFN20 with Extended Performance Electrostatic sensitive device. Observe precautions for handling.

Description

The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth ™ and WDCT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1. Block Diagram

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Figure 2. Pinning PSSO20 Figure 3. Pinning QFN20

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4533D–BLURF–01/04 Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT VS 6 V Junction temperature Tj 150 ° C Storage temperature Tstg -40 to +125 ° C RF input power LNA PinLNA 5 dBm RF input power PA PinP A 10 dBm Thermal Resistance Parameters Symbol Value Unit Junction ambient PSSOP20, slug soldered on PCB R thJA 19 K/W Junction ambient QFN20, slug soldered on PCB R thJA 27 K/W Operating Range All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_P A, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode. Parameters Symbol Min. Typ. Max. Unit Supply voltage Pins V1_PA, V2_PA and V3_PA_OUT VS 2.7 3.0 4.6 V Supply voltage Pin VS_LNA V S 2.7 3.0 5.5 V Supply current TX PSSO20 QFN20 Supply current RX IS IS IS 190 165 mA mA mA Standby current PU = 0 I S_standby 10 µA Ambient temperature T amb -25 +25 +85 ° C

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Electrical Characteristics

Test conditions (unless otherwise specified): VS = 3.0 V, Tamb = 25°C Parameters Test Conditions Symbol Min. Typ. Max. Unit Power Amplifier(1) Supply voltage Pins V1_PA, V2_PA, V3_PA_OUT VS 2.7 3.0 4.6 V Supply current TX PSSO20 TX QFN20 IS_TX IS_TX 190 165 mA mA RX (PA off), VRAMP ≤ 0.1 V IS_RX 10 µA Standby current Standby IS_standby 10 µA Frequency range TX f 2.4 2.5 GHz Gain-control range TX ∆Gp 60 42 dB Power gain maximum TX, Pin PA_IN to V3_PA_OUT Gp 28 30 33 dB Power gain minimum TX, Pin PA_IN to V3_PA_OUT Gp -40 -17 dB Ramping voltage maximum TX, power gain (maximum) Pin RAMP VRAMP max 1.7 1.75 1.83 V Ramping voltage minimum TX, power gain (minimum) Pin RAMP VRAMP min 0.1 V Ramping current maximum TX, VRAMP = 1.75 V , Pin RAMP IRAMP max 0.5 mA Power-added efficiency TX PSSO20 TX QFN20 PAE PAE Saturated output power TX, input power = 0 dBm referred to Pins V3_PA_OUT Psat 22 23 24 dBm Input matching(2) TX, Pin PA_IN Load VSWR <1.5:1 Output matching(2) TX, Pins V3_PA_OUT Load VSWR <1.5:1 Harmonics at Psat = 23 dBm TX, Pins V3_PA_OUT 2 fo -30 dBc TX, Pins V3_PA_OUT 3 fo -30 dBc T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND) Switch-out current output Standby, Pin SWITCH_OUT IS_O_standby 1 µA RX IS_O_RX 1 µA TX at 100 Ω IS_O_100 1.7 mA TX at 1.2 kΩ IS_O_1k2 7 mA TX at 33 kΩ IS_O_33k 17 mA TX at ∞ IS_O_R 19 mA Low-noise Amplifier(3) Supply voltage All, Pin VS_LNA VS 2.7 3.0 5.5 V Supply current RX IS 8 9 mA Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10 s, ZG = 50 Ω. 2. With external matching network, load impedance 50 Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 19 on page 11. Please note, that for RX_ON below 1.4 V the T/R switch driver switches to TX mode.

4533D–BLURF–01/04 Control Logic for LNA and T/R Switch Driver Supply current (LNA and control logic) TX (control logic active) Pin VS_LNA IS 0.5 mA Standby current Standby, Pin VS_LNA IS_standby 1 10 µA Frequency range RX f 2.4 2.5 GHz Power gain(5) RX, Pin LNA_IN to LNA_OUT Gp 15 16 19 dB Noise figure RX, PSSO20 RX QFN20 NF NF 2.5 2.1 2.8 2.3 dB dB Gain compression RX, referred to Pin LNA_OUT O1dB -9 -7 -6 dBm 3rd-order input interception point RX IIP3 -16 -14 -13 dBm Input matching(4) RX, Pin LNA_IN VSWRin 2:1 Output matching(4) RX Pin LNA_OUT VSWRout 2:1 Logic Input Levels (RX_ON, PU)(5) High input level = ‘1’ Pins RX_ON and PU ViH 2.4 VS, LNA V Low input level = ‘0’ ViL 0 0.5 V High input current = ‘1’ V iH = 2.4 V IiH 40 60 µA Low input current = ‘0’ IiL 0.2 µA Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3.0 V, Tamb = 25°C Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10 s, ZG = 50 Ω. 2. With external matching network, load impedance 50 Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 19 on page 11. Please note, that for RX_ON below 1.4 V the T/R switch driver switches to TX mode. Operation Mode PU RX_ON Standby 0 0 TX 1 0 RX 1 1

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Figure 4. LNA (PSSO20): Gain and Noise Figure versus Frequency Figure 5. LNA (N20): Gain and Noise Figure versus Frequency Figure 6. LNA: NF and Gain versus Temperature

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Figure 10. PA (PSSO20): Output Power and PAE versus Input Power Figure 11. PA (PSSO20): Output Power and PAE versus Frequency Figure 12. PA (QFN20): Output Power and PAE versus Supply Voltage

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Figure 16. LNA: Supply Current versus Temperature Figure 17. PA (PSSO20): Supply Current versus Iramp and Temperature Figure 18. PA (PSSO20, QFN20): Pout versus Vramp and Temperature

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Figure 22. Input Circuit V2_PA Figure 23. Input/Output Circuit V3_PA_OUT Figure 24. Input Circuit SWITCH_OUT/R_SWITCH

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Figure 28. Typical Application T7024 (PSSO20 Package)

Figure 29. Typical Application T7024 (QFN20 Package)

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Package Information

Ordering Information

Extended Type Number Package Remarks MOQ T7024-TRS PSSO20 T ube 830 pcs. T7024-TRQ PSSO20 T aped and reeled 4000 pcs. T7024-PGP QN20 T aped and reeled 1500 pcs. T7024-PGQ QFN20 T aped and reeled 6000 pcs.

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