T6829

T6819 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Supply Voltage up to 40 V
• RDSon Typically 0.5 Ω at 25°C, Maximum 1 Ω at 150°C
• Up to 1.5 A Output Current
• Three High-side and Three Low-side Drivers Usable as Single Outputs or Half Bridges
• Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors and Inductors
• PWM Capability for Each Output Controlled by External PWM Signal
• No Shoot-through Current
• Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range
• Outputs Short-circuit Protected
• Selective Overtemperature Protection for Each Switch and Overtemperature Prewarning
• Undervoltage Protection
• Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature and Power-supply Fail Detection
• Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
• SO16 Power Package

Description

The T6819/T6829 are fully protected driver interfaces designed in 0.8-µm BCDMOS technology. They are used to control up to six different loads by a microcontroller in automotive and industrial applications. Each of the three high-side and three low-side drivers is capable to drive currents up to 1.5 A. Each driver is freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. The capability to control each output with an external PWM signal opens additional applications. Protection is guaranteed regarding short-circuit conditions, overtemperature and und- ervoltage. Various diagnostic functions and a very low quiescent current in stand-by mode opens a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications. Dual Triple DMOS Output Driver with Serial Input Control T6819/T6829 Preliminary

Figure 1. Block Diagram

Figure 2. Pinning SO16 device is selected by CS = low, therefore, several ICs can operate on one data-output line only.

Figure 3. Data Transfer Table 1. Input Data Protocol

Table 2. Output Data Protocol to 6 can be used to detect the affected switch.

T6819/T6829 [Preliminary] 4531B–BCD–11/03 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immedi- ately when supply voltage recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the input register. Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detec- tion current IOUT1-3). If the current through the external load does not reach the open- load detection current, the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. Overtemperature Protection If the junction temperature of one ore more output stages exceeds the thermal prewarn- ing threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tj switch off, the affected output is disabled and the corresponding bit in the output register is set to low. Additional the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of ther- mal prewarning and shutdown threshold avoids oscillations. Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off after a delay time (tdSd). The over-load detection bit (OVL) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inac- tive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled. Inhibit The SI bit in the input register has to be set to zero to inhibit the T6819/T6829. All output stages are then turned off but the serial interface stays active. The current consumption is reduced to less than 5 µA at pin VS and less than 100 µA at pin VCC. The output stages can be activated again by bit SI = 1.

T6819/T6829 [Preliminary] 4531B–BCD–11/03 Thermal Resistance Note: 1. Threshold for undervoltage detection. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Pin Symbol Value Unit Supply voltage VVS -0.3 to +40 V Supply voltage t < 0.5 s; IS > -2 A VVS V Logic supply voltage VVCC -0.3 to +7 V Logic input voltage 5 to 8 VCS, VDI, VCLK, VPWM -0.3 to VVCC + 0.3 V Logic output voltage VDO -0.3 to VVCC + 0.3 V Input current 5 to 8 ICS, IDI, ICLK, IPWM -10 to +10 mA Output current IDO -10 to +10 mA Output current 2 to 4 13 to 15 IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L Internally limited, see output specification Output voltage 2 to 4 13 to 15 IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L -0.3 to +40 V Reverse conducting current (tpulse = 150 µs) 2 to 4 13 to 15 towards pin 12 IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L A Junction temperature range TJ -40 to +150 C Storage temperature range TSTG -55 to +150 C Parameters Test Conditions Symbol Value Unit T6819 Junction pin Measured to GND Pins 1, 9 and 16 RthJP K/W Junction ambient RthJA K/W T6829 Junction pin Measured to heat slug GND pins 1, 9 and 16 RthJP K/W Junction ambient RthJA K/W Operating Range Parameters Symbol Value Unit Supply voltage VVS VUV (1) to 40 V Logic supply voltage VVCC 4.75 to 5.25 V Logic input voltage VCS,VDI, VCLK, VPWM -0.3 to VVCC V Serial interface clock frequency fCLK MHz PWM input frequency fPWM kHz Junction temperature range Tj -40 to +150 C

T6819/T6829 [Preliminary] 4531B–BCD–11/03 Noise and Surge Immunity Note: 1. Test pulse 5: Vsmax = 40 V. Parameters Test Conditions Value Conducted interferences ISO 7637-1 Level 4(1) Interference suppression VDE 0879 Part 2 Level 5 ESD (Human Body Model) ESD S 5.1 2 kV ESD (Machine Model) JEDEC A115A 200 V

Electrical Characteristics

7.5 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Current Consumption 1.1 Quiescent current VS VVS < 20 V, SI = low IVS µA A 1.2 Quiescent current VCC 4.75 V < VVCC < 5.25 V, SI = low IVCC 100 µA A 1.3 Supply current VS VVS < 20 V normal operating, all outputs off, input register bit 13 (OLD) = high IVS mA A 1.4 Supply current VCC 4.75 V < VVCC < 5.25 V, normal operating IVCC 350 650 µA A 1.5 Discharge current VS VVS = 32.5 V, INH = low IVS 0.5 5.5 mA A 1.6 Discharge current VS VVS = 40 V, INH = low IVS 2.5 mA A Undervoltage Detection, Power-on Reset 2.1 Power-on reset threshold VVCC 3.2 3.9 4.4 V A 2.2 Power-on reset delay time After switching on VCC tdPor 190 µs A 2.3 Undervoltage-detection threshold VCC = 5 V VUv 5.6 7.0 V A 2.4 Undervoltage-detection hysteresis VCC = 5 V VUv 0.6 V A 2.5 Undervoltage-detection delay time tdUV µs A Thermal Prewarning and Shutdown 3.1 Thermal prewarning set TjPW set 120 145 170 C B 3.2 Thermal prewarning reset TjPW reset 105 130 155 C B 3.3 Thermal prewarning hysteresis TjPW K B 3.4 Thermal shutdown off Tj switch off 150 175 200 C B *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.

T6819/T6829 [Preliminary] 4531B–BCD–11/03 3.5 Thermal shutdown on Tj switch on 135 160 185 C B 3.6 Thermal shutdown hysteresis Tj switch off K B 3.7 Ratio thermal shutdown off/thermal prewarning set Tj switch off/ TjPW set 1.05 1.2 B 3.8 Ratio thermal shutdown on/thermal prewarning reset Tj switch on/ TjPW reset 1.05 1.2 B Output Specification (OUT1-OUT3) 4.1 On resistance IOut 1-3 H = -1.3 A 4, 13, RDS On 1-3 H 1.1 A 4.2 IOut 1-3 L = 1.3 A 2, 3, 15 RDS On 1-3 L 1.1 A 4.3 High-side output leakage current VOut 1-3 H = 0 V, output stages off 4, 13, IOut 1-3 H µA A 4.4 Low-side output leakage current VOut 1-3 L = VVS, output stages off 2, 3, 15 IOut 1-3 L µA A 4.5 High-side switch reverse diode forward voltage IOut = 1.5 A 4, 13, VOut 1-3 - VVS 1.5 V A 4.6 Low-side switch reverse diode forward voltage IOut 1-3 L = -1.5 A 2, 3, 15 VOut 1-3 L -1.5 V A 4.7 High-side overcurrent limitation and shutdown threshold 4, 13, IOut 1-3 H -2.5 -1.5 A A 4.8 Low-side overcurrent limitation and shutdown threshold 2, 3, 15 IOut 1-3 L 1.5 2.5 A A 4.9 Overcurrent shutdown delay time tdSd µs A 4.10 High-side open load detection current Input register bit 13 (OLD) = low, output off 4, 13, IOut 1-3 H -2.5 -0.2 mA A 4.11 Low-side open load detection current Input register bit 13 (OLD) = low, output off 2, 3, 15 IOut 1-3 L 0.2 2.5 mA A 4.12 High-side output switch on delay(1),(2) VVS = 13 V RLoad = 30 tdon µs A 4.13 Low-side output switch on delay(1),(2) VVS = 13 V RLoad = 30 tdon µs A 4.14 High-side output switch off delay(1),(2) VVS =13 V RLoad = 30 tdoff µs A Electrical Characteristics (Continued) 7.5 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.

T6819/T6829 [Preliminary] 4531B–BCD–11/03 4.15 Low-side output switch off delay(1),(2) VVS =13 V RLoad = 30 tdoff µs A 4.16 Dead time between corresponding high- and low-side switches VVS =13 V RLoad = 30 tdon - tdoff µs A 4.17 tdPWM low-side switch(3) VVS = 13 V RLoad = 30 tdPWM = tdon - tdoff µs A 4.18 tdPWM high-side switch(3) VVS = 13 V RLoad = 30 tdPWM = tdon - tdoff µs A Logic Inputs DI, CLK, CS, PWM 5.1 Input voltage low-level threshold 5-8 VIL 0.3 VVCC V A 5.2 Input voltage high-level threshold 5-8 VIH 0.7 VVCC V A 5.3 Hysteresis of input voltage 5-8 VI 700 mV A 5.4 Pull-down current Pins DI, CLK, PWM VDI, VCLK, VPWM = VCC 6, 7, 8 IPD µA A 5.5 Pull-up current Pin CS VCS = 0 V IPU -65 -10 µA A Serial Interface – Logic Output DO 6.1 Output-voltage low level IDOL = 2 mA VDOL 0.4 V A 6.2 Output-voltage high level IDOL = -2 mA VDOH VVCC- 0.7 V V A 6.3 Leakage current (tristate) VCS = VCC 0V < VDO < VVCC IDO -10 µA A Inhibit Input – Timing 7.1 Delay time from standby to normal operation tdINH 100 µs A Electrical Characteristics (Continued) 7.5 V < VS < 40 V; 4.75 V < VCC < 5.25 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.

T6819/T6829 [Preliminary] 4531B–BCD–11/03 Serial Interface – Timing No. Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type* 8.1 DO enable after CS falling edge CDO = 100 pF tENDO 200 ns D 8.2 DO disable after CS rising edge CDO = 100 pF tDISDO 200 ns D 8.3 DO fall time CDO = 100 pF tDOf 100 ns D 8.4 DO rise time CDO = 100 pF tDOr 100 ns D 8.5 DO valid time CDO = 100 pF tDOVal 200 ns D 8.6 CS setup time tCSSethl 225 ns D 8.7 CS setup time tCSSetlh 225 ns D 8.8 CS high time tCSh 500 ns D 8.9 CLK high time tCLKh 225 ns D 8.10 CLK low time tCLKl 225 ns D 8.11 CLK period time tCLKp 500 ns D 8.12 CLK setup time tCLKSethl 225 ns D 8.13 CLK setup time tCLKSetlh 225 ns D 8.14 DI setup time tDIset ns D 8.15 DI hold time tDIHold ns D *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. See Figure 4 on page 12

Figure 4. Serial Interface Timing with Chart Number

T6819/T6829 [Preliminary] 4531B–BCD–11/03 Application Ciruit Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOut1,2,3 (see “Absolute Maximum Ratings” on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to the GND pins. Negative spikes at the output pins (e.g. negative spikes caused by an inductive load switched off with a high side driver) may activate the overtemperature protection func- tion of the T6819/T6829. In this condition, the affected output will be switched off. If this behavior is not acceptable or compatible with the specific application functionally, it is necessary, that for switching on required outputs again, the SRR bit (Status Register Reset) is set, to ensure a reset of the overtemperature function. VCC 5 V 0 to 40 V VS VBatt VCC OUT1H OUT2H OUT3H DI CLK DO CS PWM UV - protection Serial interface Input register Output register H S L S H S L S H S L S S R R S I O L D P S F I N H O V L H S L S H S L S H S L S T P Fault detect GND GND VS OUT1L OUT2L OUT3L VCC Thermal protection Control logic Power-on reset GND pump Charge P H P L P H P L P H P L O C S Fault detect Fault detect Fault detect Fault detect Fault detect M M Microcontroller U5021M Watchdog VCC Reset Trigger

T6819/T6829 [Preliminary] 4531B–BCD–11/03

Package Information

Ordering Information

Power package, tubed T6819-TBQ SO16 Power package, taped and reeled T6829-TBS SO16 Power package with heat slug, tubed T6829-TBQ SO16 Power package with heat slug, taped and reeled technical drawings according to DIN specifications Dimensions in mm 10.0 9.85 8.89 0.4 1.27 1.4 0.25 0.10 5.2 4.8 3.7 3.8 6.15 5.85 0.2

T6819/T6829 [Preliminary] 4531B–BCD–11/03

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