T6817_05 ATMEL | Alldatasheet
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Features
- Three High-side and Three Low-side Drivers Outputs Freely Configurable as Switch, Half Bridge or H-bridge Capable of Switching All Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors 0.6A Continuous Current Per Switch Low-side: RDSon < 1.5Ω Versus Total Temperature Range High-side: RDSon < 2.0Ω Versus Total Temperature Range Very Low Quiescent Current IS < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage and Overvoltage Protection Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature and Power Supply Fail Serial Data Interface Daisy Chaining Possible SSO20 Package 1. Description The T6817 is a fully protected driver interface designed in 0.8-µm BCDMOS technol- ogy. It can be used to control up to 6 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design is especially supportive of H-bridges applications to drive DC motors. Protection is guaranteed in terms of short-circuit conditions, overtemperature, under- and overvoltage. Various diagnosis functi ons and a very low quiescent current in standby mode open a wide range of applications. Meeting automotive qualifications in the area of conducted interferences, EMC protection and 2 kV ESD protection provide added value and enhanced quality for the exacting requirements of automotive applications. Dual Triple DMOS Output Driver with Serial Input Control T6817 Rev. 4670C–BCD–09/05
4670C–BCD–09/05 T6817 Figure 1-1. Block Diagram HS1HS2HS3 DI CLK INH DO CS OV - protection UV -protection VS VS Vcc Serial interface Input register Output register H S L S H S L S H S L S S R R S I S T C O L D P S F I N H S C D H S L S H S L S H S L S T P Fault detect Fault detect Fault detect Fault detect GND GND GND GND VS Fault detect Fault detect LS1LS2LS3 VS VCC Thermal protection Osc Control logic Vcc Power-on reset 12 14 16 8 15 17 GND
4670C–BCD–09/05 T6817 2. Pin Configuration Figure 2-1. Pinning SSO20 GND DI CS CLK INH VS VS LS3 n.c. GND GND VCC DO LS1 HS1 LS2 HS2 GND HS3 GND Table 2-1. Pin Description Pin Symbol Function
1 GND Ground; reference potential; internal co nnection to pin 10, 11, 13 and 20; cooling tab
2D I Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control device, DI expects a 16-bit control word with LSB being transferred first 3C S Chip-select input; 5-V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled 4C L K Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz)
5 INH Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating
6, 7 VS Power supply output stages HS1, HS2 and HS3 8L S 3 Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load 9 n.c. Not connected
10 GND Ground (see pin 1) be consistant
11 GND Ground (see pin 1)
12 HS3 High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load
13 GND Ground (see pin 1)
14 HS2 High-side driver output 2 (see pin 12) be consistant
15 LS2 Low-side driver output 2 (see pin 8)
16 HS1 High-side driver output 1 (see pin 12)
17 LS1 Low-side driver output 1 (see pin 8)
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only one data output line only.
19 VCC Logic supply voltage (5V)
20 GND Ground (see pin 1)
4670C–BCD–09/05 T6817 3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of th e CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans- ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer Input Data Protocol CS DI CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 3-1. Input Data Protocol Bit Input Register Function 0S R R Status register reset (high = reset; the bits PSF , SCD and overtemperature shutdown in the output data register are set to low)
1 LS1 Controls output LS1 (h igh = switch output LS1 on)
2 HS1 Controls output HS1 (h igh = switch output HS1 on)
3 LS2 See LS1
4 HS2 See HS1
5 LS3 See LS1
6 HS3 See HS1
7 n.u. Not used 8 n.u. Not used 9 n.u. Not used 10 n.u. Not used 11 n.u. Not used 12 n.u. Not used
13 OLD Open load detection (low = on)
14 SCT
Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown delay high/low = 14 ms/3.5 ms 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered)
4670C–BCD–09/05 T6817 Note: Bit 0 to 15 = high: overtemperature shutdown Table 3-2. Output Data Protocol Bit Output (Status) Register Function 0T P Temperature prewarning: high = warning (overtemperature shut-down, see remark below)
1 Status LS1
Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off)
2 Status HS1
Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off)
3 Status LS2 Description, see LS1
4 Status HS2 Description, see HS1
5 Status LS3 Description, see LS1
6 Status HS3 Description, see HS1
7 n.u. Not used 8 n.u. Not used 9 n.u. Not used 10 n.u. Not used 11 n.u. Not used 12 n.u. Not used
13 SCD Short circuit detected: set high, when at least one output is switched off
by a short circuit condition
14 INH Inhibit: this bit is controlled by software (bit SI in input register) and
hardware inhibit (pin 17). High = standby, low = normal operation
15 PSF Power supply fail: over- or undervoltage at pin VS detected
Table 3-3. Status of the Input Register after Power on Reset Bit 15 (SI) Bit 14 (SCT) Bit 13 (OLD) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR)
4670C–BCD–09/05 T6817
3.2 Power-supply Fail
In case of over- or undervoltage at pin VS, an internal timer is started. When the undervoltage delay time (tdUV, tdOV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register.
3.3 Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current I HS1-3, ILS1-3). If VVS-VHS1-3 or VLS1-3 is lower than the open-load detection threshold (open-load condi- tion), the corresponding bit of the output in the output register is set to high. Switching on an output stage with the OLD bit set to low disables the open-load function for this output. If bit SI is set to low, the open-load function is also switched off.
3.4 Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, T jPW set, the temperature prewarning bit (TP) in the output register is se t. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted with- out affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, T j switch off , the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, T j switch on , and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis.
3.5 Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (I HS1-3, ILS1-3) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-cir- cuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled.
3.6 Inhibit
There are two ways to inhibit the T6817: 1. Set bit SI in the input register to zero 2. Switch pin 5 (INH) to 0V In both cases, all output stages are turned off but th e serial interface stays active. The output stages can be activated again by bit SI = 1 and by pin 5 (INH) switched back to 5V.
4670C–BCD–09/05 T6817 Notes: 1. Threshold for undervoltage detection 2. Outputs disabled for V VS > VOV (threshold for overvoltage detection) 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameter Pin Symbol Value Unit Supply voltage 6, 7 V VS –0.3 to +40 V Supply voltage t < 0.5s; IS > –2A 6, 7 V VS –1 V Supply voltage difference |VS_Pin6 – VS_Pin7| ∆VVS 150 mV Supply current 6, 7 I VS 1.4 A Supply current t < 200 ms 6, 7 I VS 2.6 A Logic supply voltage 19 V VCC –0.3 to 7 V Input voltage 5 V INH –0.3 to 17 V Logic input voltage 2 to 4 V DI, VCLK, VCS –0.3 to VVCC +0.3 V Logic output voltage 18 V DO –0.3 to VVCC +0.3 V Input current 5, 2 to 4 I INH, IDI, ICLK, ICS –10 to +10 mA Output current 18 I DO –10 to +10 mA Output current 8, 12, 14 to 17 ILS1 to ILS3 IHS1 to IHS3 Internal limited, see output specification Reverse conducting current (tPulse = 150 µs) 12, 14, 16 towards 6, 7 IHS1 to IHS3 17 A Junction temperature range T j –40 to +150 °C Storage temperature range T STG –55 to +150 °C 5. Thermal Resistance All values refer to GND pins Parameter Test Conditions Symbol Value Unit Junction pin Measured to GND Pins 1, 10, 11, 13 and 20 RthJP 25 K/W Junction ambient R thJA 65 K/W 6. Operating Range All values refer to GND pins Parameter Test Conditions Symbol Min. Typ. Max. Unit Supply voltage Pins 6, 7 V VS VUV (1) 40(2) V Logic supply voltage Pin 19 V VCC 4 . 555 . 5V Logic input voltage Pin 2 to 4 and 5 V INH, VDI, VCLK, VCS –0.3 V VCC V Serial interface clock frequency Pin 4 f CLK 2M H z Junction temperature range T j –40 150 °C
4670C–BCD–09/05 T6817 Note: 1. Test pulse 5: V Smax = 40V 7. Noise and Surge Immunity Parameter Test Conditions Value Conducted interferences ISO 7637–1 Level 4 (1) Interference Suppression VDE 0879 Part 2 Level 5 ESD (Human Body Model) MIL-STM 5.1 – 1998 2 kV ESD (Machine Model) JEDEC EIA / JESD 22 – A115-A 150V 8. Electrical Characteristics 7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1 Current Consumption
1.1 Quiescent current
(VS) VVS < 16V, INH or bit SI = low 6, 7 I VS 40 µA A
1.2 Quiescent current
(VCC) 4.5V < VVCC < 5.5V, INH or bit SI = low
19 I VCC 20 µA A
1.3 Supply current (VS)
VVS < 16V normal operating, all output stages off, 6, 7 I VS 0.8 1.2 mA A
1.4 Supply current (VS)
VVS < 16V normal operating, all output stages on, no load 6, 7 I VS 10 mA A 1.5 Supply current (VCC) 4.5V < VVCC < 5.5V, normal operating pin 19 I VCC 150 µA A
2 Internal Oscillator Frequency
2.1 Frequency (time
base for delay timers) fOSC 19 45 kHz A
3 Over- and Undervoltage De tection, Power-on Reset
3.1 Power-on reset
threshold 19 V VCC 3.4 3.9 4.4 V A
3.2 Power-on reset delay
19 t dPor 30 95 160 µs A
3.3 Undervoltage
detection threshold 6, 7 V UV 5.5 7.0 V A
3.4 Undervoltage
detection hysteresis 6, 7 ∆VUV 0.4 V A
3.6 Undervoltage
detection delay 6, 7 t dUV 72 1 m s A
3.7 Overvoltage
detection threshold 6, 7 V OV 18.0 22.5 V A
3.8 Overvoltage
detection hysteresis 6, 7 ∆VOV 1V A
3.9 Undervoltage
bit 14 (SCT) = high bit 14 (SCT) = low tdOV tdOV 1.75 5.25 ms ms A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of CS after data tran smission and switch on/off output stages to 90% of final level
4670C–BCD–09/05 T6817
4 Thermal Prewarning and Shutdown
4.1 Thermal prewarning T jPWset 125 145 165 °C A
4.2 Thermal prewarning T jPWreset 105 125 145 °C A
4.3 Thermal prewarning
hysteresis ∆TjPW 32 0 K A
4.4 Thermal shutdown T j switch off 150 170 190 °C A
4.5 Thermal shutdown T j switch on 130 150 170 °C A
4.6 Thermal shutdown
hysteresis ∆Tj switch off 32 0 K A 4.7 Ratio thermal shutdown/thermal prewarning Tj switch off/ TjPW set 1.05 1.17 A 4.8 Ratio thermal shutdown/thermal prewarning Tj switch on/ TjPW reset 1.05 1.2 A 5 Output Specification (LS1-LS6, HS1-HS6) 7.5V < V VS < VOV
5.1 On resistance I Out = 600 mA 8, 15,
17 RDS OnL 1.5 Ω A
5.2 On resistance I Out = –600 mA 12, 14,
16 RDS OnH 2.0 Ω A
5.3 Output clamping
voltage ILS1-3 = 50 mA 8, 15,
17 VLS1-3 40 60 V A
5.4 Output leakage
VLS1–3 = 40V all output stages off 8, 15,
17 ILS1–3 10 µA A
5.5 Output leakage
VHS1-3 = 0V all output stages off 2, 3, 12, 13, 15, 28 IHS1–3 –10 µA A
5.7 Inductive shutdown
8, 12, 14 to Woutx 15 mJ D
5.8 Output voltage edge
8, 12, 14 to dVLS1–3/dt dVHS1–3/dt 50 200 400 mV/µs A 5.9 Overcurrent limitation and shutdown threshold 8, 15,
17 ILS1–3 650 950 1250 mA A
5.10 Overcurrent limitation and shutdown threshold 12, 14,
16 IHS1–3 –1250 –950 –650 mA A
5.11 Overcurrent
bit 14 (SCT) = high bit 14 (SCT) = low tdSd tdSd 1.0 1.5 2.0 ms ms A A
5.12 Open load detection
(OLD) = low, output off 8, 15,
17 ILS1–3 60 200 µA A
- Electrical Characteristics (Continued) 7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of CS after data tran smission and switch on/off output stages to 90% of final level
4670C–BCD–09/05 T6817
5.13 Open load detection
(OLD) = low, output off 12, 14,
16 IHS1–3 –150 –30 µA A
5.14 Open load detection
ILS1–3/ IHS1–3 1.2 A
5.15 Open load detection
(OLD) = low, output off 8, 15, 17 VLS1–3 0.6 2 V A
5.16 Open load detection
(OLD) = low, output off 12, 14, VVS– VHS1–3 0.6 2 V A
5.17 Output switch on
delay(1) RLoad = 1 kΩ tdon 0.5 ms A
5.18 Output switch off
delay(1) RLoad = 1 kΩ tdoff 1m sA
6 Inhibit Input
6.1 Input voltage low
0.3 × VVCC VA
6.2 Input voltage high
0.7 × VVCC VA
6.3 Hysteresis of input
voltage 5 ∆VI 100 700 mV A
6.4 Pull-down current V INH = VVCC 5I PD 10 80 µA A
7 Serial Interface – Logic Inputs DI, CLK, CS
7.1 Input voltage low-
0.3 × VVCC VA
7.2 Input voltage high-
0.7 × VVCC VA
7.3 Hysteresis of input
voltage 2-4 ∆VI 50 500 mV A
7.4 Pull-down current pin
DI, CLK VDI, VCLK = VVCC 2, 4 I PDSI 25 0 µ A A
7.5 Pull-up current
pin CS VCS = 0V 3 I PUSI –50 –2 µA A
8 Serial Interface - Logic Output DO
8.1 Output voltage low
level IOL = 3 mA 18 V DOL 0.5 V A
8.2 Output voltage high
level IOL = –2 mA 18 V DOH VVCC – 1V VA
8.3 Leakage current
(tri-state) VCS = VVCC,
0 V < VDO < VVCC
18 I DO –10 10 µA A
- Electrical Characteristics (Continued) 7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of CS after data tran smission and switch on/off output stages to 90% of final level
4670C–BCD–09/05 T6817 9. Serial Interface - Timing Parameters Test Conditions Timing Chart No. Symbol Min. Typ. Max. Unit DO enable after CS falling edge C DO = 100 pF 1 t ENDO 200 ns DO disable after CS rising edge C DO = 100 pF 2 t DISDO 200 ns DO fall time C DO = 100 pF – t DOf 100 ns DO rise time C DO = 100 pF – t DOr 100 ns DO valid time C DO = 100 pF 10 t DOVal 200 ns CS setup time 4 t CSSethl 225 ns CS setup time 8 t CSSetlh 225 ns CS high time Input register bit 14 (SCT) = high 9t CSh 140 ms CS high time Input register bit 14 (SCT) = low 9t CSh 17.5 ms CLK high time 5 t CLKh 225 ns CLK low time 6 t CLKl 225 ns CLK period time – t CLKp 500 ns CLK setup time 7 t CLKSethl 225 ns CLK setup time 3 t CLKSetlh 225 ns DI setup time 11 t DIset 40 ns DI hold time 12 t DIHold 40 ns
4670C–BCD–09/05 T6817 Figure 9-1. Serial Interface Timing with Chart Numbers CS DO 1 2 CS CLK DI CLK DO 10 12 Inputs DI, CLK, CS: High level = 0.7× VCC, low level = 0.3 × VCC Output DO: High level = 0.8× VCC, low level = 0.2 × VCC
4670C–BCD–09/05 T6817 10. Application Figure 10-1. Application Circuit
10.1 Application Notes
It is strongly recommended that the blocking capacitors at VCC and VS be connected as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec- trolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolut Maximum Ratings). Recommended value for capacitors at VCC: Electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended that cooling areas be placed on the PCB as close as possible to GND pins. HS1HS2HS3 DI CLK INH DO CS OV- protection UV- protection VS VS Vcc Serial interface Input register Output register H S L S H S L S H S L S S R RSI S T C O L D n.u. P S F I N H S CD H S L S H S L S H S L S TP GND GND GND GND VS LS1LS2LS3 VS VCC Thermal protection Osc Control logic Vcc Power-on reset 12 14 16 81 5 1 7 GND Vcc 5 V+ 13 V BYT41D Vs VBatt Fault detect Fault detect Fault detect Fault detect Fault detect Fault detect M M µC U5021M Watchdog Vcc Reset Trigger Enable
4670C–BCD–09/05 T6817 12. Package Information 11. Ordering Information Extended Type Number Package Remarks T6817-TKSY SSO20 Power package, tube, Pb-free T6817-TKQY SSO20 Power package, taped and reeled, Pb-free technical drawings according to DIN specifications Dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.15 20 11 11 0
4670C–BCD–09/05 T6817 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4670C-BCD-09/05 • Pb-free logo on page 1 added
- Table “Ordering Information” on page 14 changed 4670B-BCD-05/05 • Put datasheet in a new template
- Table “Electrical Characteristics” rows 5.15 and 5.16 changed
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