T6816_05 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Six High-side and Six Low-side Drivers Outputs Freely Configurable as Switch, Half Bridge or H-bridge Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors and Inductors 0.6A Continuous Current per Switch Low-side: RDSon < 1.5Ω versus Total Temperature Range High-side: RDSon < 2.0Ω versus Total Temperature Range Very Low Quiescent Current Is < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage Protection Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature and Power Supply Fail Serial Data Interface Operation Voltage up to 40V Daisy Chaining Possible SO28 Power Package 1. Description The T6816 is a fully protected driver inte rface designed in 0.8 µm BCDMOS technol- ogy. It is especially suitable for truck or bus applications and the industrial 24-V supply. It controls up to 12 different loads via a 16-bit dataword. Each of the six high-side and six low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC is also designed to easily build H-bridges to drive DC motors in motion-control applications. Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting require- ments of automotive applications. 40-V Dual Hex Output Driver with Serial Input Control T6816 Rev. 4595E–BCD–09/05
4595E–BCD–09/05 T6816 Figure 1-1. Block Diagram CLK CS INH DO DI HS1 HS2 HS3 HS4 HS5 HS6 1315 12 32 28 Osc Fault Detect OH S VS VS GND GND GND GND GND GND GND GND VCC LS6LS1 LS2 LS3 LS4 LS5 Control logic VCC Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect S T CS I L D S H S L S L S H S L S H S L S H S L S H S L S R R P S F I N H S C D H S H S L S L S H S L S H S L S H S L S H S L S T P Input Register Output Register 16 14 11 41 27 Fault Detect Fault Detect Fault Detect Fault Detect UV - protection VS VCC Power-on reset Thermal protection 15 13 12 32 28
4595E–BCD–09/05 T6816 2. Pin Configuration Figure 2-1. Pinning SO28 123456 78 109 27 22 21 20 1819 17 1211 28 2526 2324 LS4 16 15 1413 HS6 LS6 DI CLK CS GND VCC DO INH LS1 HS1 LS5 HS5 HS4 VS VS LS3 HS3 HS2 LS2 GND GND GND GNDGND GND GND Lead frame T6816 Table 2-1. Pin Description Pin Symbol Function 1L S 5 Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load 2H S 5 High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load
3 HS4 High-side driver output 4; see pin 2
4 LS4 Low-side driver output 4; see pin 1
5 VS Power supply output stages HS4, HS5, HS6, inte rnal supply; external connection to pin 10 necessary 6, 7, 8, 9 GND Ground; reference potential; inte rnal connection to pin 20-23; cooling tab
10 VS Power supply output stages HS1, HS2 and HS3
11 LS3 Low-side driver output 3; see pin 1
12 HS3 High-side driver output 3; see pin 2
13 HS2 High-side driver output 2; see pin 2
14 LS2 Low-side driver output 2; see pin 1
15 HS1 High-side driver output 1; see pin 2
16 LS1 Low-side driver output 1; see pin 1
17 INH Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operating
Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only.
19 VCC Logic supply voltage (5V)
20-23 GND Ground; see pin 6-9
24 CS Chip select input; 5V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
25 CLK Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f max = 2 MHz) 26 DI Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first
27 LS6 Low-side driver output 6; see pin 1
28 HS6 High-side driver output 6; see pin 2
4595E–BCD–09/05 T6816 3. Functional Description
3.1 Serial Interface
Data transfer starts with the falling edge of th e CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans- ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer Input Data Protocol SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT SI CS DI CLK DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Table 3-1. Input Data Protocol Bit Input Register Function 0S R R Status register reset (high = reset; the bits PSF , SCD and overtemperature shutdown in the output data register are set to low)
1 LS1 Controls output LS1 (high = switch output LS1 on)
2 HS1 Controls output HS1 (high = switch output HS1 on)
3 LS2 See LS1
4 HS2 See HS1
5 LS3 See LS1
6 HS3 See HS1
7 LS4 See LS1
8 HS4 See HS1
9 LS5 See LS1
10 HS5 See HS1
11 LS6 See LS1
12 HS6 See HS1
13 OLD Open load detection (low = on)
14 SCT Programmable time delay for short circuit
(shutdown delay high/low = 12 ms/1.5 ms) 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered)
4595E–BCD–09/05 T6816 Note: Bit 0 to 15 = high: overtemperature shutdown Table 3-2. Output Data Protocol Bit Output (Status) Register Function 0T P Temperature prewarning: high = warning (overtemperature shutdown see remark below)
1 Status LS1
Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off)
2 Status HS1
Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off)
3 Status LS2 Description see LS1
4 Status HS2 Description see HS1
5 Status LS3 Description see LS1
6 Status HS3 Description see HS1
7 Status LS4 Description see LS1
8 Status HS4 Description see HS1
9 Status LS5 Description see LS1
10 Status HS5 Description see HS1
11 Status LS6 Description see LS1
12 Status HS6 Description see HS1
13 SCD Short circuit detected: set high, when at least one output is switched off by a
14 INH Inhibit: this bit is controlled by software (bit SI in input register) and hardware
inhibit (pin 17). High = standby, low = normal operation
15 PSF Power supply fail: undervoltage at pin VS detected
Table 3-3. Status of the Input Register after Power on Reset Bit 15 (SI) Bit 14 (SCT) Bit 13 (OLD) Bit 12 (HS6) Bit 11 (LS6) Bit 10 (HS5) Bit 9 (LS5) Bit 8 (HS4) Bit 7 (LS4) Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR) HH H L L L LL LL L L L L L L
4595E–BCD–09/05 T6816
3.2 Power Supply Fail
In case of undervoltage at pin VS, an internal timer is started. When the undervoltage delay time (tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output regis- ter is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register.
3.3 Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current I HS1-6, ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condi- tion), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output.
3.4 Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, T jPW set, the temperature prewarning bit (TP) in the output register is se t. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted with- out affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, T j switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, T j switch on , and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis.
3.5 Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (I HS1-6, ILS1-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-cir- cuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled.
3.6 Inhibit
There are two ways to inhibit the T6816: 1. Set bit SI in the input register to zero 2. Switch pin 17 (INH) to 0V In both cases, all output stages are turned off but th e serial interface stays active. The output stages can be activated again by bit SI = 1 or by pin 17 (INH) switched back to 5V.
4595E–BCD–09/05 T6816 Note: 1. Threshold for undervoltage detection. 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins Parameter Pin Symbol Value Unit Supply voltage 5, 10 V VS –0.3 to +40 V Supply voltage t < 0.5 s; IS ≥ –2 A 5, 10 V VS –1 V Supply voltage difference ⏐ VS_pin5 – VS_pin10⏐∆ VVS 150 mV Supply current 5, 10 I VS 1.4 A Supply current t < 200 ms 5, 10 I VS 2.6 A Logic supply voltage 19 V VCC –0.3 to +7 V Input voltage 17 V INH –0.3 to +17 V Logic input voltage 24 to 26 V DI, VCLK, VCS –0.3 to VVCC +0.3 V Logic output voltage 18 V DO –0.3 to VVCC +0.3 V Input current 17, 24 to 26 I INH, IDI, ICLK, ICS –10 to +10 mA Output current 18 I DO –10 to +10 mA Output current 1 to 4, 11 to 16, 27 and 28 ILS1 to ILS6 IHS1 to IHS6 Internal limited, see output specification Reverse conducting current (tPulse = 150 µs) 2, 3, 12, 13, 15, 28 towards 5, 10 IHS1 to IHS6 17 A Junction temperature range T j –40 to +150 °C Storage temperature range T STG –55 to +150 °C 5. Thermal Resistance All values refer to GND pins Parameter Test Conditions Pin Symbol Min. Typ. Max. Unit Junction pin Measured to GND 6 to 9, 20 to 23 R thJP 25 K/W Junction ambient R thJA 65 K/W 6. Operating Range All values refer to GND pins Parameter Test Conditions Pin Symbol Min. Typ. Max. Unit Supply voltage 5, 10 V VS VUV (1) 40 V Logic supply voltage 19 V VCC 4 . 555 . 5 V Logic input voltage 17, 24 to 26 VINH, VDI, VCLK, VCS –0.3 V VCC V Serial interface clock frequency 25 f CLK 2M H z Junction temperature range Tj –40 150 °C
4595E–BCD–09/05 T6816 Note: 1. Test pulse 5: V Smax = 40V 7. Noise and Surge Immunity Parameter Test Conditions Value Conducted interferences ISO 7637-1 Level 4 (1) Interference Suppression VDE 0879 Part 2 Level 5 ESD (Human Body Model) MIL-STD-883D Method 3015.7 2 kV ESD (Machine Model) EOS/ESD - S 5.2 150V 8. Electrical Characteristics 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type*
1 Current Consumption
1.1 Quiescent current (VS) VVS < 28V,
INH or bit SI = low 5, 10 I VS 40 µA A
1.2 Quiescent current
(VCC) 4.5V < VVCC < 5.5V, INH or bit SI = low
19 I VCC 20 µA A
1.3 Supply current (VS)
VVS < 28V normal operating, all output stages off 5, 10 I VS 0.8 1.2 mA A
1.4 Supply current (VS)
VVS < 28V normal operating, all output stages on, no load 5, 10 I VS 10 mA A 1.5 Supply current (VCC) 4.5V < VVCC < 5.5V, normal operating pin 19 I VCC 150 µA A
2 Internal Oscillator Frequency
2.1 Frequency (timebase
for delay timers) fOSC 19 45 kHz A
3 Undervoltage Detection, Power-on Reset
3.1 Power-on reset
threshold 19 V VCC 3.4 3.9 4.4 V A
3.2 Power-on reset delay
time After switching on VVCC 19 t dPor 30 95 160 µs A
3.3 Undervoltage detection
threshold 5, 10 V UV 5.5 7.0 V A
3.4 Undervoltage detection
hysteresis 5, 10 ∆VUV 0.4 V A
3.5 Undervoltage detection
delay 5, 10 t dUV 72 1 m s A
4 Thermal Prewarning and Shutdown
4.1 Thermal prewarning 17 T jPWset 125 145 165 °C A
4.2 Thermal prewarning 17 T jPWreset 105 125 145 °C A
4.3 Thermal prewarning
hysteresis ∆TjPW 20 K A
4.4 Thermal shutdown 17 T j switch off 150 170 190 °C A
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data tr ansmission and switch on output stages to 90% of final level
4595E–BCD–09/05 T6816
4.5 Thermal shutdown 17 T j switch on 130 150 170 °C A
4.6 Thermal shutdown
hysteresis ∆Tj switch off 20 K A 4.7 Ratio thermal shutdown/thermal prewarning Tj switch off/ TjPW set 1.05 1.17 A 4.8 Ratio thermal shutdown/thermal prewarning T j switch on/ TjPW reset 1.05 1.2 A 5 Output Specification (LS1 -LS6, HS1-HS6) 7.5V < VVS < 40V
5.1 On resistance I Out = 600 mA
1, 4, 11, 14, 16, RDS OnL 1.5 Ω A
5.2 On resistance I Out = –600 mA
2, 3, 12, 13, 15, RDS OnH 2.0 Ω A
5.3 Output clamping
voltage ILS1-6 = 50 mA 1, 4, 11, 14, 16, VLS1-6 40 60 V A
5.4 Output leakage current VLS1–6 = 40V
1, 4, 11, 14, 16, ILS1-6 10 µA A
5.5 Output leakage current VHS1-6 = 0V
2, 3, 12, 13, 15, IHS1-6 –10 µA A
5.7 Inductive shutdown
1-4, 11-16, 27, 28 Woutx 15 mJ D
5.8 Output voltage edge
1-4, 11-16, 27, 28 dVLS1-6/dt dVHS1-6/dt 50 200 400 mV/µs A
5.9 Overcurrent limitation
1-4, 11-16, ILS1-6 650 950 1250 mA A
5.10 Overcurrent limitation
2, 3, 12,13, 15, 28 IHS1-6 –1250 –950 –650 mA A
5.11 Overcurrent shutdown
bit 14 (SCT) = low tdSd 1.0 1.5 2.0 ms A
5.12 Open load detection
(OLD) = low, output off 1, 4, 11,14, 16, 27 ILS1-6 60 200 µA A
5.13 Open load detection
(OLD) = low, output off 2, 3, 12, 13 15, IHS1-6 –150 –30 µA A 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data tr ansmission and switch on output stages to 90% of final level
4595E–BCD–09/05 T6816
5.14 Open load detection
current ratio ILS1-6/IHS1-6 1.2 A
5.15 Open load detection
(OLD) = low, output off 1, 4, 11,14, 16, 27 VLS1-6 0.6 2 V A
5.16 Open load detection
(OLD) = low, output off 2, 3, 12, 13 15, 28 V VS – VHS1-6 0.6 2 V A
5.17 Output switch on
delay(1) RLoad = 1 kΩ tdon 0.5 ms A
5.18 Output switch off
delay(1) RLoad = 1 kΩ tdoff 1m sA
6 Inhibit Input
6.1 Input voltage low level
0.3 × VVCC VA
6.2 Input voltage high level
0.7 × VVCC VA
6.3 Hysteresis of input
voltage 17 ∆VI 100 700 mV A
6.4 Pull-down current V INH = VVCC 17 I PD 10 80 µA A
7 Serial Interface - Logi c Inputs DI, CLK, CS
7.1 Input voltage low-level
0.3 × VVCC VA
7.2 Input voltage high-level
0.7 × VVCC VA
7.3 Hysteresis of input
voltage 24-26 ∆VI 50 500 mV A
7.4 Pull-down current pin
DI, CLK VDI, VCLK = VVCC 25, 26 I PDSI 25 0 µ A A
7.5 Pull-up current pin CS V CS= 0V 24 I PUSI –50 –2 µA A
8 Serial Interface - Logic Output DO
8.1 Output voltage low level I OL = 3 mA 18 V DOL 0.5 V A
8.2 Output voltage high
level IOL = –2 mA 18 V DOH VVCC – 0.7V VA
8.3 Leakage current
(tri-state) VCS = VVCC, 0V < VDO < VVCC
18 I DO –10 10 µA A
- Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pi n Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data tr ansmission and switch on output stages to 90% of final level
4595E–BCD–09/05 T6816 9. Serial Interface - Timing Parameters Test Conditions Timing Chart No. Symbol Min. Typ. Max. Unit DO enable after CS falling edge C DO = 100 pF 1 t ENDO 200 ns DO disable after CS rising edge C DO = 100 pF 2 t DISDO 200 ns DO fall time C DO = 100 pF – t DOf 100 ns DO rise time C DO = 100 pF – t DOr 100 ns DO valid time C DO = 100 pF 10 t DOVal 200 ns CS setup time 4 t CSSethl 225 ns CS setup time 8 t CSSetlh 225 ns CS high time Input register bit 14 (SCT) = high 9t CSh 16 ms CS high time Input register bit 14 (SCT) = low 9t CSh 2m s CLK high time 5 t CLKh 225 ns CLK low time 6 t CLKl 225 ns CLK period time – t CLKp 500 ns CLK setup time 7 t CLKSethl 225 ns CLK setup time 3 t CLKSetlh 225 ns DI setup time 11 t DIset 40 ns DI hold time 12 t DIHold 40 ns
4595E–BCD–09/05 T6816 Figure 9-1. Serial Interface Timing with Chart Numbers CS DO 1 2 CS CLK DI CLK DO 10 12 Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.2 × VCC Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC
4595E–BCD–09/05 T6816 10. Application Figure 10-1. Application Circuit
10.1 Application Notes
It is strongly recommended to connect the blocking capacitors at V CC and VS as close as possi- ble to the power supply and GND pins. Recommended value for capacitors at VS: electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for elec- trolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolute Maximum Ratings). Recommended value for capacitors at VCC: electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins. BYT41D VS VBatt 24V VS VCC U5021M WATCHDOG VCC VCC Reset Trigger Enable CLK CS DO HS1 HS2 HS3 HS4 HS5 HS6 Osc OH S VS GND GND GND GND GND GND GND GND VCC LS6LS1 LS2 LS3 LS4 LS5 Control logic S T CS I L D S H S L S L S H S L S H S L S H S L S H S L S R R P S F IN H S C D H S H S L S L S H S L S H S L S H S L S H S L S T P Input Register Output Register 16 14 11 41 27 UV - protection Power-on Reset Thermal protection 15 13 12 32 28 5 V DI INH Microcontroller FaultDetectFault Detect Fault Detect Fault Detect VCC VS VS VCC VCC VS FaultDetect FaultDetect FaultDetect FaultDetect FaultDetect FaultDetect FaultDetect FaultDetect
4595E–BCD–09/05 T6816 12. Package Information 11. Ordering Information Extended Type Number Package Remarks T6816-TIQY SO28 Power package, taped and reeled, Pb-free technical drawings according to DIN specifications 0.25 0.10 Dimensions in mm 0.4 1.27 16.51 18.05 17.80 2.35 7.5 7.3 9.15 8.65 10.50 10.20 0.25 28 15 11 4
4595E–BCD–09/05 T6816 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4595E-BCD-09/05
- Pb-free logo on page 1 added
- Section 1 “Description” on page 1 changed
- Ordering Information on page 14 changed 4595D-BCD-05/05 • Put datasheet in a new template
- Table “Electrical Characteristics” rows 5.15 and 5.16 changed 4595C-BCD-04/04
- Put datasheet in a new template
- Table “Absolute Maximum Ratings” on page 7 changed
- Table “Electrical Characteristics” on page 10 changed
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