T6816

T6816 ATMEL | Alldatasheet

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Technical content

Features

• Six High-side and Six Low-side Drivers  Outputs Freely Configurable as Switch, Half Bridge or H–bridge  Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors and Inductors  0.6 A Continuous Current per Switch  Low-side: RDSon < 1.5 /g87 versus Total Temperature Range  High-side: RDSon < 2.0 /g87 versus Total Temperature Range  Very Low Quiescent Current Is < 20 µA in Standby Mode  Outputs Short-circuit Protected  Overtemperature Prewarning and Protection  Undervoltage Protection  Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature and Power Supply Fail  Serial Data Interface  Operation Voltage up to 40 V  Daisy Chaining Possible  SO28 Power Package

Description

The T6816 is a fully protected driver interface designed in 0.8 µm BCDMOS technol- ogy. It is especially suitable for truck or bus applications and the industrial 24-V supply. It controls up to 12 different loads via a 16-bit dataword. Each of the six high-side and six low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurabl e and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC is also designed to easily build H- bridges to drive DC motors in motion-control applications. Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Overvoltage protection is matched to the requirements of the 24-V industrial voltage and the 24-V automotive supply. Automotive qualification referring to conducted inter- ferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications. 40-V Dual Hex Output Driver with Serial Input Control T6816 Rev. 4595B–BCD–05/03

2 T6816

Figure 1. Block Diagram

4595B–BCD–05/03 Pin Configuration Figure 2. Pinning SO28 12345678 109 27 22 21 20 18 19 17 1211 28 2526 23 24 LS4 16 15 1413 HS6 LS6 DI CLK CS GND VCC DO INH LS1 HS1 LS5 HS5 HS4 VS VS LS3 HS3 HS2 LS2 GND GND GND GNDGND GND GND Lead frame T6816 Pin Description Pin Symbol Function 1L S 5 Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load 2H S 5 High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load

3 HS4 High-side driver output 4; see Pin 2

4 LS4 Low-side driver output 4; see Pin 1

5 VS Power supply output stages HS4, HS5, HS6, inte rnal supply; external connection to Pin 10 necessary 6, 7, 8, 9 GND Ground; reference potential; in ternal connection to Pin 20 - 23; cooling tab

10 VS Power supply output stages HS1, HS2 and HS3

11 LS3 Low-side driver output 3; see Pin 1

12 HS3 High-side driver output 3; see Pin 2

13 HS2 High-side driver output 2; see Pin 2

14 LS2 Low-side driver output 2; see Pin 1

15 HS1 High-side driver output 1; see Pin 2

16 LS1 Low-side driver output 1; see Pin 1

17 INH Inhibit input; 5 V logic input with internal pull down; low = standby,

high = normal operating 18 DO Serial data output; 5 V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the /g181C (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only.

19 VCC Logic supply voltage (5 V)

20, 21, 22,

23 GND Ground; see Pin 6 – 9

24 CS Chip select input; 5 V CMOS logic level input with internal pull up;

low = serial communication is enabled, high = disabled

25 CLK Serial clock input; 5 V CMOS logic level input with internal pull down;

controls serial data input interface and internal shift register (f max = 2 MHz) 26 DI Serial data input; 5 V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first

27 LS6 Low-side driver output 6; see Pin 1

28 HS6 High-side driver output 6; see Pin 2

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Figure 3. Data Transfer Input Data Protocol Table 1. Input Data Protocol

1 LS1 Controls output LS1 (high = switch output LS1 on)

2 HS1 Controls output HS1 (high = switch output HS1 on)

3 LS2 See LS1

4 HS2 See HS1

5 LS3 See LS1

6 HS3 See HS1

7 LS4 See LS1

8 HS4 See HS1

9 LS5 See LS1

10 HS5 See HS1

11 LS6 See LS1

12 HS6 See HS1

Table 2. Output Data Protocol

13 OLD Open load detection (low = on)

14 SCT Programmable time delay for short circuit (shutdown delay high/

1 Status LS1

2 Status HS1

3 Status LS2 Description see LS1

4 Status HS2 Description see HS1

5 Status LS3 Description see LS1

6 Status HS3 Description see HS1

7 Status LS4 Description see LS1

8 Status HS4 Description see HS1

9 Status LS5 Description see LS1

10 Status HS5 Description see HS1

11 Status LS6 Description see LS1

12 Status HS6 Description see HS1

13 SCD Short circuit detected: set high, when at least one output is

14 INH

15 PSF Power supply fail: undervoltage at Pin VS detected

Table 1. Input Data Protocol (Continued) Table 3. Status of the Input Register after Power on Reset

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4595B–BCD–05/03 Power Supply Fail In case of undervoltage at Pin VS, an internal timer is started. When the undervoltage delay time (tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detec- tion current I HS1-6, ILS1-6). If V VS–VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open- load function for this output. Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, T jPW set, the tem- perature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, T jPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at Pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, T j switch off, the out- puts are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, T js w i t c ho n, and when a high has been written to the SRR bit in the input register. Ther- mal prewarning and shutdown threshold have hysteresis. Short-circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (I HS1-6 , ILS1-6 ) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (t dSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is dis- abled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. Inhibit There are two ways to inhibit the T6816: 1. Set bit SI in the input register to zero 2. Switch Pin 17 (INH) to 0 V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by Pin 17 (INH) switched back to 5V .

4595B–BCD–05/03 Note: 1. Threshold for undervoltage detection. Absolute Maximum Ratings All values refer to GND pins Parameter Symbol Value Unit Supply voltage Pins 5, 10 V VS -0.3 to +40 V Supply voltage tt0.5 s; ISu-2 A Pins 5, 10 V VS -1 V Supply voltage difference |VS_Pin5 - VS_Pin10|D V VS 150 mV Supply current Pins 5, 10 I VS 1.4 A Supply current t < 200 ms Pins 5, 10 I VS 2.6 A Logic supply voltage Pin 19 V VCC -0.3 to +7 V Input voltage Pin 17 V INH -0.3 to +17 V Logic input voltage Pins 24 to 26 V DI, VCLK, VCS -0.3 to VVCC +0.3 V Logic output voltage Pin 18 V DO -0.3 to VVCC +0.3 V Input current Pins 17, 24 to 26 I INH, IDI, ICLK, ICS -10 to +10 mA Output current Pin 18 I DO -10 to +10 mA Output current Pins 1 to 4, 11 to 16, Pins 27 and 28 ILS1 to ILS6 IHS1 to IHS6 Internal limited, see output specification Reverse conducting current Pins 2, 3, 12, 13, 15, (tPulse = 150 ms) 28 towards Pins 5, 10 IHS1 to IHS6 17 A Junction temperature range T j -40 to +150 /g176C Storage temperature range T STG -55 to +150 /g176C Thermal Resistance All values refer to GND pins Parameter Test Conditions Symbol Min. Typ. Max. Unit Junction - pin Measured to GND Pins 6 to 9 and 20 to 23 RthJP 25 K/W Junction ambient R thJA 65 K/W Operating Range All values refer to GND pins Parameter Test Conditions Symbol Min. Typ. Max. Unit Supply voltage Pins 5, 10 V VS VUV (1) 40 V Logic supply voltage Pin 19 V VCC 4 . 555 . 5V Logic input voltage Pin 17, 24 to 26 V INH, VDI, VCLK, VCS -0.3 V VCC V Serial interface clock frequency Pin 25 f CLK 2M H z Junction temperature range T j -40 150 /g176C

8 T6816

4595B–BCD–05/03 Note: 1. Test pulse 5: V Smax = 40 V Noise and Surge Immunity Parameter Test Conditions Value Conducted interferences ISO 7637-1 Level 4 (1) Interference Suppression VDE 0879 Part 2 Level 5 ESD (Human Body Model) MIL-STD-883D Method 3015.7 2 kV ESD (Machine Model) EOS/ESD - S 5.2 150 V

Electrical Characteristics

7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 Current Consumption

1.1 Quiescent current

(VS) VVS < 28 V, INH or bit SI = lo 5, 10 I VS 40 µA A

1.2 Quiescent current

(VCC) 4.5 V < VVCC < 5.5 V , INH or bit SI = low

19 I VCC 20 µA A

1.3 Supply current (VS) VVS < 28 V normal operating, all output stages off, 5, 10 I VS 0.8 1.2 mA A 1.4 Supply current (VS) VVS < 28 V normal operating, all output stages on, no load 5, 10 I VS 10 mA A 1.5 Supply current (VCC) 4.5 V < VVCC < 5.5 V , normal operating Pin 19 I VCC 150 µA A

2 Internal Oscillator Frequency

2.1 Frequency (timebase

for delay timers) fOSC 19 45 kHz A

3 Undervoltage Detection, Power-on Reset

3.1 Power–on reset

threshold 19 V VCC 3.4 3.9 4.4 V A

3.2 Power–on reset delay

19 t dPor 30 95 160 µs A

3.3 Undervoltage

detection threshold 5, 10 V UV 5.5 7.0 V A

3.4 Undervoltage

detection hysteresis 5, 10 /g68VUV 0.4 V A

3.5 Undervoltage

detection delay 5, 10 t dUV 72 1 m s A

4 Thermal Prewarning and Shutdown

4.1 Thermal prewarning 17 T jPWset 125 145 165 /g176CA

4.2 Thermal prewarning 17 T jPWreset 105 125 145 /g176CA

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

4595B–BCD–05/03

4.3 Thermal prewarning

4.4 Thermal shutdown 17 T j switch off 150 170 190 /g176CA

4.5 Thermal shutdown 17 T j switch on 130 150 170 /g176CA

4.6 Thermal shutdown

hysteresis DTj switch off 20 K A

4.7 Ratio thermal

1.05 1.17 A

4.8 Ratio thermal

1.05 1.2 A 5 Output Specification (LS1 - LS6, HS1 - HS6) 7.5 V < VVS < 40 V 5.1 On resistance I Out = 600 mA 1, 4, 11, 14, 16, 27 R DS OnL 1.5 /g87 A 5.2 On resistance I Out = -600 mA 2, 3, 12, 13, 15, 28 R DS OnH 2.0 /g87 A 5.3 Output clamping voltage ILS1-6 = 50 mA 1, 4, 11, 14, 16, 27 VLS1-6 40 60 V A 5.4 Output leakage current VLS1–6 = 40 V all output stages off 1, 4, 11, 14, 16, 27 ILS1–6 10 µA A 5.5 Output leakage current VHS1-6 = 0 V all output stages off 2, 3, 12, 13, 15, 28 IHS1–6 -10 µA A

5.7 Inductive shutdown

1-4, 11-16 27, 28 Woutx 15 mJ D

5.8 Output voltage edge

1-4, 11-16 27, 28 dVLS1–6/dt dVHS1–6/dt 50 200 400 mV/µs A

5.9 Overcurrent limitation

1, 4, 11,14 16, 27 I LS1–6 650 950 1250 mA A Electrical Characteristics (Continued) 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

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4595B–BCD–05/03

5.10 Overcurrent limitation

2, 3, 12,13 15, 28 I HS1–6 -1250 -950 -650 mA A

5.11 Overcurrent

bit 14 (SCT) = low tdSd 1.0 1.5 2.0 ms A

5.12 Open load detection

(OLD) =low, output off 1, 4, 11,14 16, 27 ILS1–6 60 200 µA A

5.13 Open load detection

(OLD) =low, output off 2, 3, 12, 13 15, 28 IHS1–6 -150 -30 µA A

5.14 Open load detection

ILS1–6/IHS1– 1.2 A

5.15 Open load detection

(OLD) =low, output off 1, 4, 11,14 16, 27 VLS1–6 0.6 4 V A

5.16 Open load detection

(OLD) =low, output off 2, 3, 12, 13 15, 28 VVS– VHS1–6 0.6 4 V A

5.17 Output switch on

delay 1) RLoad = 1 k/g87 tdon 0.5 ms A

5.18 Output switch off

delay 1) RLoad = 1 k/g87 tdoff 1m sA

6 Inhibit Input

6.1 Input voltage low level

0.3- VVCC VA

6.2 Input voltage high

0.7- VVCC VA

6.3 Hysteresis of input

voltage 17 /g68VI 100 700 mV A

6.4 Pull-down current V INH = VVCC 17 I PD 10 80 µA A

7 Serial Interface - Logic Inputs DI, CLK, CS

7.1 Input voltage low-

level threshold 24-26 V IL 0.3- VVCC VA

7.2 Input voltage high-

level threshold 24-26 V IH 0.7- VVCC VA

7.3 Hysteresis of input

voltage 24-26 DV I 50 500 mV A

7.4 Pull-down current Pin

DI, CLK VDI, VCLK = VVCC 25, 26 I PDSI 25 0 µ A A

7.5 Pull-up current

Pin CS VCS= 0 V 24 I PUSI -50 -2 µA A Electrical Characteristics (Continued) 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level

4595B–BCD–05/03 Serial Interface — Timing

8 Serial Interface - Logic Output DO

8.1 Output voltage low

level IOL = 3 mA 18 V DOL 0.5 V A

8.2 Output voltage high

level IOL = -2 mA 18 V DOH VVCC-

0.7 V VA

8.3 Leakage current

(tri-state) VCS = VVCC,

0 V < VDO < VVCC

18 I DO -10 10 µA A

Electrical Characteristics (Continued) 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level Parameters Test Conditions Timing Chart No. Symbol Min. Typ. Max. Unit DO enable after CS falling edge C DO = 100 pF 1 t ENDO 200 ns DO disable after CS rising edge C DO = 100 pF 2 t DISDO 200 ns DO fall time C DO = 100 pF – t DOf 100 ns DO rise time C DO = 100 pF – t DOr 100 ns DO valid time C DO = 100 pF 10 t DOVal 200 ns CS setup time 4 t CSSethl 225 ns CS setup time 8 t CSSetlh 225 ns CS high time Input register Bit 14 (SCT) = high 9t CSh 16 ms CS high time Input register Bit 14 (SCT) = low 9t CSh 2m s CLK high time 5 t CLKh 225 ns CLK low time 6 t CLKl 225 ns CLK period time – t CLKp 500 ns CLK setup time 7 t CLKSethl 225 ns CLK setup time 3 t CLKSetlh 225 ns DI setup time 11 t DIset 40 ns DI hold time 12 t DIHold 40 ns

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Figure 4. Serial Interface Timing with Chart Numbers

Figure 5. Application Circuit possible to the power supply and GND pins. HSX (see: Absolut Maximum Ratings). electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. close as possible to GND pins.

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4595B–BCD–05/03

Package Information

Ordering Information

Extended Type Number Package Remarks T6816-TIQ SO28 Power package, taped and reeled technical drawings according to DIN specifications 0.25 0.10 Dimensions in mm 0.4 1.27 16.51 18.05 17.80 2.35 7.5 7.3 9.15 8.65 10.50 10.20 0.25 28 15 11 4

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