T5754-6AQ

T5754 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Integrated PLL Loop Filter  ESD Protection (4 kV HBM/200 V MM; Except Pin 2: 4 kV HBM/100 V MM) also at ANT1/ANT2  High Output Power (7.5 dBm) with Low Supply Current (9.0 mA)  Modulation Scheme ASK/ FSK – FSK Modulation is Achieved by Connecting an Additional Capacitor Between the XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller  Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply  Single Li-cell for Power Supply  Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40° C to 85° C/125° C  Package TSSOP8L  Single-ended Antenna Output with High Efficient Power Amplifier  CLK Output for Clocking the Microcontroller  One-chip Solution with Minimum External Circuitry  125° C Operation for Tire Pressure Systems

Description

The T5754 is a PLL transmitter IC which has been developed for the demands of RF low-cost transmission systems at data rates up to 32 kBaud. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems. Figure 1. System Block Diagram

1 Li cell

2 T5754

Figure 2. Pinning TSSOP8L

2 PA_ENABLE Switches on power amplifier, used for

5 XTAL Connection for crystal

6 VS Supply voltage See ESD protection circuitry (see Figure 8 on page 8)

7 GND Ground See ESD protection circuitry (see Figure 8 on page 8)

8 ENABLE Enable input

Figure 3. Block Diagram crystal connected in series to GND are needed as external elements. microcontroller and the PA is switched on. via the connected load impedance. an optimized load impedance of ZLoad = (166 + j223) Ω is used at 3 V supply voltage.

4 T5754

4511F–RKE–07/04 Functional If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so that a lithium cell used as power supply can work for several years. With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform the ASK modulation. ASK Transmission The T5754 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1m s , t h e n the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of Pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5754 is switched back to standby mode with ENABLE = L. FSK Transmission The T5754 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1m s , t h e n the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capaci- tor and GND with an open-drain output port , thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5754 is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered. Figure 4. Tolerances of Frequency Modulation CMOS compatible if the load capacitance is lower than 10 pF. sion IC, so that the message can be sent with crystal accuracy.

low resistive path to VS to deliver the DC current. power amplifier is compensated by the load impedance. parallel imaginary part should be kept constant. cable used to measure the output power must be calibrated out. Figure 5. Output Power Measurement loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. 15 pF load-capacitance crystal.

6 T5754

Figure 6. ASK Application Circuit

Figure 7. FSK Application Circuit

8 T5754

Figure 8. ESD Protection Circuit specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

4511F–RKE–07/04

Electrical Characteristics

VS = 2.0 V to 4.0 V, Tamb = -40° C to 125° C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25° C. All parameters are referred to GND (pin 7). Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply current Power down VENABLE < 0.25 V , -40° C to 85° C VPA-ENABLE < 0.25 V , -40° C to +125° C VPA-ENABLE < 0.25 V , 25° C (100% correlation tested) IS_Off <10 350 nA µA nA Supply current Power up, PA off, VS = 3 V, VENABLE >1 . 7V , VPA-ENABLE <0 . 2 5V IS 3.7 4.8 mA Supply current Power up, VS = 3.0 V, VENABLE >1 . 7V , VPA-ENABLE >1 . 7V IS_Transmit 91 1 . 6 m A Output power VS = 3.0 V, Tamb =2 5° C, f = 433.92 MHz, ZLoad = (166 + j233) Ω PRef 5.5 7.5 10 dBm Output power variation for the full temperature range Tamb = -40° C to +85° C, VS = 3.0 V VS = 2.0 V ∆PRef ∆PRef -1.5 -4.0 dB dB Output power variation for the full temperature range Tamb = -40° C to +125° C, VS = 3.0 V VS = 2.0 V POut = PRef + ∆PRef ∆PRef ∆PRef -2.0 -4.5 dB dB Achievable output-power range Selectable by load impedance P Out_typ 07 . 5 d B m Spurious emission fCLK = f0/128 Load capacitance at pin CLK = 10 pF f O ± 1× fCLK fO ± 4 × fCLK other spurious are lower -55 -52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM ≤ 10 fF , load capacitance selected accordingly Tamb = -40° C to +85° C Tamb = -40° C to +125° C fXTO -30 -40 fXT AL +30 +40 ppm ppm PLL loop bandwidth 250 kHz Phase noise of phase comparator Referred to fPC = fXT0, 25 kHz distance to carrier -116 -110 dBc/Hz In loop phase noise PLL 25 kHz distance to carrier -86 -80 dBc/Hz Phase noise VCO at 1 MHz at 36 MHz -94 -125 -90 -121 dBc/Hz dBc/Hz Frequency range of VCO f VCO 429 439 MHz Clock output frequency (CMOS microcontroller compatible) f0/128 MHz Voltage swing at Pin CLK C Load ≤ 10 pF V0h V0l VS × 0.8 VS × 0.2 V V Series resonance R of the crystal Rs 110 Ω Capacitive load at Pin XT0 7p F Note: 1. If V S is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.

10 T5754

4511F–RKE–07/04 FSK modulation frequency rate Duty cycle of the modulation signal = 50% 03 2 k H z ASK modulation frequency rate Duty cycle of the modulation signal = 50% 03 2 k H z ENABLE input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 V V µA PA_ENABLE input Low level input voltage High level input voltage Input current high VIl VIh IIn 1.7 0.25 VS (1) V V µA Electrical Characteristics (Continued) VS = 2.0 V to 4.0 V, Tamb = -40° C to 125° C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25° C. All parameters are referred to GND (pin 7). Parameters Test Conditions Symbol Min. Typ. Max. Unit Note: 1. If V S is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.

4511F–RKE–07/04

Package Information

Ordering Information

Extended Type Number Package Remarks T5754-6AQ TSSOP8L Taped and reeled, Marking: T574

12 T5754

4511F–RKE–07/04 Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Changes from Rev. 4511E-RKE-10/03 to Rev. 4511F-RKE-07/04 1. Abs. Max. Ratings table (page 8): row “Input voltage” added 2. Abs. Max. Ratings table (page 8): table note 1 added 3. El. Char. table (page 10): row “PA_ENABLE input“ changed 4. El. Char. table (page 10): table note 1 added 5. Ordering Information table (page 10): Remarks changed

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