T5743

T5743 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Two Different IF Receiving Bandwidth Versions Are Available (BIF = 300 kHz or 600 kHz)
• 5 V to 20 V Automotive Compatible Data Interface
• IC Condition Indicator, Sleep or Active Mode
• Low Power Consumption Due to Configurable Self Polling with a Programmable Timeframe Check
• High Sensitivity, Especially at Low Data Rates
• Data Clock Available for Manchester- and Bi-phase-coded Signals
• Minimal External Circuitry Requirements, no RF Components on the PC Board Except Matching to the Receiver Antenna
• Sensitivity Reduction Possible Even While Receiving
• Fully Integrated VCO
• SO20 Package
• Supply Voltage 4.5 V to 5.5 V, Operating Temperature Range -40°C to +105°C
• Single-ended RF Input for Easy Adaptation to λ/4 Antenna or Printed Antenna on PCB
• Low-cost Solution Due to High Integration Level
• ESD Protection According to MIL-STD. 883 (4KV HBM)
• High Image Frequency Suppression Due to 1 MHz IF in Conjunction with a SAW Front- end Filter. Up to 40 dB is Thereby Achievable With State-of-the-art SAWs.
• Communication to Microcontroller Possible Via a Single, Bi-directional Data Line
• Power Management (Polling) Is Also Possible by Means of a Separate Pin Via the Microcontroller
• Programmable Digital Noise Suppression

Description

The T5743 is a multi-chip PLL receiver device supplied in an SO20 package. It has been especially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud in Manchester or Bi-phase code. The receiver is well suited to operate with Atmel's PLL RF transmitter U2741B. Its main applications are in the areas of telemetering, security technology and keyless-entry systems. It can be used in the frequency receiving range of f 0 = 300 MHz to 450 MHz for ASK or FSK data transmission. All the statements made below refer to 433.92 MHz and 315 MHz applications. System Block Diagram Figure 1. System Block Diagram

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Figure 2. Pinning SO20

1 SENS Sensitivity-control resistor

2 IC_ACTIVE IC condition indicator

3 CDEM Lower cut-off frequency data filter

4 AVCC Analog power supply

5 TEST Test pin, during operation at GND

6 AGND Analog ground

7 MIXVCC Power supply mixer

8 LNAGND High-frequency ground LNA and mixer

9 LNA_IN RF input

11 LFVCC Power supply VCO

12 LF Loop filter

13 LFGND Ground VCO

14 XTO Crystal oscillator

Figure 3. Block Diagram

15 DVCC Digital power supply

17 DATA_CLK Bit clock of data stream

18 DGND Digital ground

19 POLLING/_ON Selects polling or receiving mode

20 DATA Data output/configuration input

3 MHz

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(low-noise amplifier), LO (local oscillator), a mixer and an RF amplifier. fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64. tal. According to Figure 4, the crystal should be connected to GND via a capacitor CL. of the crystal and the XTO must be considered. Figure 4. PLL Peripherals

not equal to 1 MHz. f IF is then dependent on the logical level at Pin MODE and on f RF. Table 1 summarizes the different conditions. works for the parameters given in the electrical characteristics. Table 1. Calculation of LO and IF Frequency

300 MHz < fRF < 365 MHz,

365 MHz < fRF < 450 MHz,

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Figure 5. Input Matching Network with SAW Filter Figure 6. Input Matching Network without SAW Filter value is not critical but must be large enough not to detune the series resonance circuit. improves the sensitivity of the receiver by about 1 dB to 2 dB.

IF = 600 kHz together with such transmitters. signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode the S/N ratio is not affected by the dynamic range of the RSSI amplifier. Sens is connected to GND, the receiver operates at full sensitivity. receiver is still active (see also figure 34). Figure 7. Steady L State Limited DATA Output Pattern

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4569A–RKE–12/02 FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via the bit ASK/_FSK in the OPMODE register. Logic ‘L’ sets the demodulator to FSK, applying ‘H’ to ASK mode. In ASK mode, an automatic threshold control ci rcuit (ATC) is used to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit effectively suppresses any kind of inband noise signals or competing transmitters. If the S/N (ratio to suppress inband noise signals) exceeds 10 dB, the data signal can be detected properly. The FSK demodulator is intended to be used for an FSK deviation of 10 kHz /g163 /g68f /g163 100 kHz. In FSK mode the data signal can be detected if the S/N (ratio to suppress inband noise signals) exceeds 2 dB. This value is guaranteed for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filt er improves the S/N ratio as its passband can be adopted to the characteristics of the dat a signal. The data filter consists of a st-order highpass and a 2nd-order lowpass filter. The highpass filter cut-off frequency is defined by an external capacitor connected to Pin CDEM. The cut-off frequency of the highpass filter is defined by the following formula: In self-polling mode, the data filter must settle very rapidly to achieve a low current con- sumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter require- ments according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the lowpass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to section ‘Con- figuration of the Receiver’). The BR_Range must be set in accordance to the used baud rate. The T5743 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V DC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 2 dB in that condition. Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig ). These limits are defined in the electric al characteristics. They should not be exceeded to maintain full sensitivity of the receiver. Receiving Characteristics The RF receiver T5743 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 8. This example relates to ASK mode and the 300-kHz bandwidth version of the T5743. FSK mode and the 600-kHz bandwidth version of the receiver exhibits similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. fcu_DF 1

Figure 8. Receiving Frequency Response culated to be the sum of the deviation of the crystal and the XTO deviation of the T5743. ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in that case. is disabled during that time. consumption, system response time, data rate etc. nected microcontroller or it can be operated by up to five uni-directional ports. of the local oscillator (fLO).

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Figure 9. Generation of the Basic Clock Cycle

• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (f IF0) Most applications are dominated by two transmission frequencies: f Send = 315 MHz is mainly used in USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk- dependent parameters on this electrical characteristics display three conditions for each parameter.
• Application USA (f XTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs)
• Application Europe (f XTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs)
• Other applications (T Clk is dependent on fXTO and on the logical state of Pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T XClk is defined by the following formulas for further reference: BR_Range = BR_Range0: T XClk = 8 /g180 TClk BR_Range1: T XClk = 4 /g180 TClk BR_Range2: T XClk = 2 /g180 TClk BR_Range3: T XClk = 1 /g180 TClk Polling Mode According to Figure 10, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period T Sleep while consuming low current of IS =I Soff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period T Bit-check. This period varies check by check as it is a statistical process. An average value for TBit-check is given in the electrical characteristics. During T Startup and TBit-check the current consumption is I S =I Son. The condition of the receiver is indicated on Pin IC_ACTIVE. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: DVCC XTO MODE T f Clk XTO XTO Divider :14/:10 L : USA(:10) H: Europe(:14)

4569A–RKE–12/02 During TSleep and TStartup the receiver is not sensitive to a transmitter signal. To guaran- tee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters T Sleep, TStartup, TBit-check and the start-up time of a connected microcontroller (TStart,µC). Thus, TBit-check depends on the actual bit rate and the number of bits (NBit-check) to be tested. The following formula indicates how to calculate the preburst length. T Preburst /g179 TSleep + TStartup + TBit-check + TStart_µC Sleep Mode The length of period T Sleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor XSleep (according to Table 9), and the basic clock cycle T Clk. It is calculated to be: TSleep = Sleep /g180 XSleep /g180 1024 /g180 TClk In US- and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to 1. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleep Std to 1. According to Table 8, the highest register value of sleep sets the receiver into a perma- nent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line and may also be used for microcontroller polling — via Pin POLLING/_ON, the receiver can be switched on and off. I Spoll ISoff TSleep ISon TStartup TBit-check+/g40/g41/g180+/g180

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Figure 10. Polling Mode Flow Chart condition and ready to receive. Bit-check: Depends on the result of the bit check. condition and ready to receive. TBit-check: Depends on the result of the bit check. condition and ready to receive. TBit-check: Depends on the result of the bit check.

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Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. maximum value of the upper limit is Lim_max = 63. (NBit-check) to prevent switching to receiving mode due to noise. check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 15. Figure 13. Timing Diagram During Bit Check Figure 14. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)

Figure 15. Timing Diagram for Failed Bit Check (Condition: CV_Lim /g179 Lim_max) switched back to polling mode explicitly. period tee of the Data signal as a result is always an integral multiple of TXClk. handling of a connected microcontroller. after the receiver has switched to receiving mode.

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Figure 16. Synchronization of the Demodulator Output Figure 17. Debouncing of the Demodulator Output Figure 18. Steady L State Limited DATA Output Pattern After Transmission

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Figure 21. Activating the Receiving Mode via Pin POLLING/_ON Figure 20 illustrates how to set the receiver back to polling mode via Pin POLLING/_ON. check will be ignored, but not deleted (see also section “Digital Noise Suppression”). POLLING/_ON is held to High. stream. This clock can only be used for Manchester and Bi-phase coded signals. distance between two edges is continuously compared to a programmable time window. phase coded signals are valid (T and 2T). LIMIT-register (Lim_min and Lim_max, see Table 11 and Table 12).

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Figure 24. Data Clock Disappears Because of a Logical Error Figure 25. Output of the Data Clock After a Successful Bit Check load at Pin DATA is exceeded, the data clock disappears (see section “Data Interface”).

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Figure 28. Output of Digital Noise at the End of the Data Stream Figure 29. Automatic Noise Suppression Figure 30. Occurence of a Pulse at the End of the Data Stream the Pin POLLING/_ON must be set to High.

Figure 31. Controlled Noise Suppression programming operation, must be set to 0. Table 2. Effect of Bit 1 and Bit 2 on Programming the Registers Table 3. Effect of Bit 15 on Programming the Register

0 The values will be written into the register (OPMODE or LIMIT)

1 The values will not be written into the register

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Table 4. Effect of the Configuration Words Within the Registers configuration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. Table 5. Effect of the Configuration Word BR_Range Table 6. Effect of the Configuration Word NBit-check

Table 7. Effect of the Configuration Bit Modulation Table 8. Effect of the Configuration Word Sleep Table 9. Effect of the Configuration Bit XSleep Table 10. Effect of the Configuration Bit Noise Suppression

0 FSK (default)

1 ASK

0 Noise suppression is inactive

1 Noise suppression is active (default)

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Table 11. Effect of the Configuration Word Lim_min Note: 1. Lim_min is also be used to determine the margins of the data clock control logic (see section “Data Clock”). Table 12. Effect of the Configuration Word Lim_max Note: 1. Lim_max is also be used to determine the margins of the data clock control logic (see section “Data Clock”). provide a mechanism to preserve the RAM register information. voltage of the receiver is turned on. cancelled via a Low pulse t1 at Pin DATA.

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Figure 34. Data Interface according to Figure 33 and Figure 34. subsequently programmed this way. The time frame to program a bit is defined by t6. Programming of a register is possible both in sleep- and in active-mode of the receiver. Manchester demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers.

• t1(min) < t1 < 5632 /g180/g32T Clk: t1(min) is the minimum specified value for the relevant BR_Range Programming respectively OFF-command is initiated if the receiver is not in reset mode.If the receiver is in reset mode, programming respectively Off-command is not ini- tiated and the reset marker RM is still present at Pin DATA. This period is generally used to switch the receiver to polling mode or to start the pro- gramming of a register. In reset condition, RM is not cancelled by accident.
• t1 > 7936 /g180T Clk Data_In Data_out Input - Interface DATA0 ... 20 V0 V / 5 V VX = 5 V to 20 V Rpup CL VS = 4.5 V to 5.5 V I/O Serial bi-directional data line T5743 Microcontroller Out1 mîcrocontroller ID Data_In Data_out Input - Interface DATA0 ... 20 V0 V / 5 V VX = 5 V to 20 V Rpup CL VS = 4.5 V to 5.5 V I/O Serial bi-directional data line T5743 Microcontroller Out1 mîcrocontroller ID

OPMODE and LIMIT are set to the default values. RM is cancelled if present. ates in default mode, this time period for t1 can generally be used. Note that the capacitive load at Pin DATA is limited. connected via the pull-up resistor Rpup up to 20 V and is short-circuit-protected. of the maximum load capacity at Pin DATA is given in the “Application Hints U3743BM”. Table 13. Applicable R Figure 35. Application Circuit: fRF = 433.92 MHz without SAW Filter

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Figure 36. Application Circuit: fRF = 315 MHz without SAW Filter Figure 37. Application Circuit: fRF = 433.92 MHz with SAW Filter

Figure 38. Application Circuit: fRF = 315 MHz with SAW Filter

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4569A–RKE–12/02

Electrical Characteristics

All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V , Tamb = 25/g176C) Parameter Test Conditions Symbol 6.76438 MHz Osc. (MODE: 1) 4.90625 MHz Osc. (MODE: 0) Variable Oscillator Basic Clock Cycle of the Digital Circuitry Basic clock cycle MODE = 0 (USA) MODE = 1 (Europe) TClk 2.0697 2.0697 2.0383 2.0383 1/fXTO/10 1/fXTO/14 1/fXTO/10 1/fXTO/14 µs µs Extended basic clock cycle BR_Range0 BR_Range1 BR_Range2 BR_Range3 T XClk 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 /g180/g32T Clk 4/g32/g180/g32TClk 2 /g180/g32TClk 1 /g180/g32TClk 8 /g180/g32TClk 4/g32/g180/g32TClk 2 /g180/g32TClk 1 /g180/g32TClk µs µs µs µs Polling Mode Sleep time (see Figure 10, Figure 19, and Figure 33) Sleep and XSleep are defined in the OPMODE register T Sleep Sleep /g180/g32 XSleep /g180/g32 1024 /g180/g32 2.0697 Sleep /g180/g32 XSleep /g180/g32 1024 /g180/g32 2.0697 Sleep /g180/g32 XSleep /g180/g32 1024 /g180/g32 2.0383 Sleep /g180/g32 XSleep /g180/g32 1024 /g180/g32 2.0383 Sleep /g180/g32 XSleep /g180/g32 1024 /g180/g32TClk Sleep /g180/g32 XSleep /g180/g32 1024 /g180/g32TClk ms Start-up time (see Figure 10, and Figure 11) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Startup 1855 1061 1061 663 1855 1061 1061 663 1827 1045 1045 653 1827 1045 1045 653 896.5 512.5 512.5 320.5/g32/g180/g32TClk 896.5 512.5 512.5 320.5 /g180/g32 TClk µs µs µs µs Time for bit check (see Figure 10) Average bit-check time while polling, no RF applied (see Figure 14, and Figure 15) BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms Bit-check time for a valid input signal f Sig , (see Figure 11) NBit-check = 0 NBit-check = 3 NBit-check = 6 NBit-check = 9 TBit-check 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig 3/fSig 6/fSig 9/fSig 3.5/fSig 6.5/fSig 9.5/fSig

1 X TXClk

3.5/fSig 6.5/fSig 9.5/fSig ms ms ms ms Receiving Mode Intermediate frequency MODE = 0 (USA) MODE = 1 (Europe) fIF 1.0 1.0 fXTO /g180/g3264/314 fXTO /g180/g3264/432.92 MHz MHz Baud-rate range BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 BR_Range0 /g180/g322 /g109s/T Clk BR_Range1 /g180/g322 /g109s/TClk BR_Range2 /g180/g322 /g109s/TClk BR_Range3 /g180/g322 /g109s/TClk kBaud kBaud kBaud kBaud Minimum time period between edges at Pin DATA (see Figure 7, Figure 17 and Figure 18, with the exception of parameter T Pulse) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t DA TA-min 165 41.4 20.7 165 41.4 20.7 163 40.7 20.4 163 40.7 20.4 10 /g180/g32T XClk 10 /g180/g32TXClk 10 /g180/g32TXClk 10 /g180/g32TXClk 10 /g180/g32TXClk 10 /g180/g32TXClk 10 /g180/g32TXClk 10 /g180/g32TXClk µs µs µs µs

4569A–RKE–12/02 Maximum Low period at Pin DATA (see Figure 7 and Figure 18) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t DATA_L_max 2152 1076 538 270 2152 1076 538 270 2120 1060 530 265 2120 1060 530 265 130 /g180/g32TXClk 130 /g180/g32TXClk 130 /g180/g32TXClk 130 /g180/g32TXClk 130 /g180/g32TXClk 130 /g180/g32TXClk 130 /g180/g32TXClk 130 /g180/g32TXClk µs µs µs µs Delay to activate the start-up mode (see Figure 21) Clk 10.5 /g180/g32TClk µs OFF- command at Pin POLLING/_ON (see Figure 20) Ton2 16.6 16.4 8 /g180/g32T Clk µs Delay to activate the sleep mode (see Figure 20) Pulse on Pin DATA at the end of a data stream (see Figure 30) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 T Pulse 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 /g180/g32TClk 4 /g180/g32TClk 2 /g180/g32TClk 1 /g180/g32TClk 8 /g180/g32TClk 4 /g180/g32TClk 2 /g180/g32TClk 1 /g180/g32TClk µs µs µs µs Configuration of the Receiver Frequency of the reset marker (see Figure 31) f RM 117.9 117.9 119.8 119.8 Hz Programming start pulse (see Figure 19 and Figure 33) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR 3367 2277 1735 1464 16.43 11650 11650 11650 11650 3311 2243 1709 1442 16.18 11470 11470 11470 11470 1624/g32/g180/g32T Clk 1100/g180/g32TClk 838 /g180/g32TClk 707 /g180/g32TClk 7936 /g180/g32TClk 5632 /g180/g32TClk 5632 /g180/g32TClk 5632 /g180/g32TClk 5632 /g180/g32TClk µs µs µs µs µs Programming delay period (see Figure 19 and Figure 33) t2 795 798 783 786 384.5 /g180/g32T Clk 385.5 /g180/g32 TClk µs Synchroni- zation pulse t3 265 265 261 261 128 /g180/g32TClk 128 /g180/g32TClk µs Delay until of the program window starts t4 131 131 129 129 63.5 /g180/g32TClk 63.5 /g180/g32TClk µs Programming window t5 530 530 522 522 256 /g180/g32TClk 256 /g180/g32TClk µs Time frame of a bit (see Figure 33) t6 1060 1060 1044 1044 512 /g180/g32TClk 512 /g180/g32TClk µs Programming pulse (see Figure 19 and Figure 33) t7 132 529 130 521 64 /g180/g32TClk 256 /g180/g32TClk µs Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V , Tamb = 25/g176C) Parameter Test Conditions Symbol 6.76438 MHz Osc. (MODE: 1) 4.90625 MHz Osc. (MODE: 0) Variable Oscillator

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4569A–RKE–12/02 Equivalent acknowledge pulse: E_Ack (see Figure 33) t8 265 265 261 261 128 /g180/g32T Clk 128 /g180/g32TClk µs Equivalent time window (see Figure 33) t9 534 534 526 526 258 /g180/g32T Clk 258 /g180/g32TClk µs OFF-bit programming window (see Figure 19) t10 930 930 916 916 449.5 /g180/g32T Clk 449.5 /g180/g32TClk µs Data Clock Minimum delay time between edge at DATA and DATA_CLK (see Figure 26 and Figure 27) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t Delay2 16.6 8.3 4.15 2.07 16.3 8.2 4.08 2.04 1 /g180/g32T XClk 1 /g180/g32TXClk 1 /g180/g32TXClk 1 /g180/g32TXClk µs µs µs µs Pulswidth of negative pulse at Pin DATA_CLK (see Figure 26 and Figure 27) BR_Range = BR_Range0 BR_Range1 BR_Range2 BR_Range3 t P_DATA_CLK 66.2 33.1 16.56 8.3 66.2 33.1 16.56 8.3 65.2 32.6 16.3 8.2 65.2 32.6 16.3 8.2 4 /g180/g32TXClk 4 /g180/g32TXClk 4 /g180/g32TXClk 4 /g180/g32TXClk 4 /g180/g32TXClk 4 /g180/g32TXClk 4 /g180/g32TXClk 4 /g180/g32TXClk µs µs µs µs Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V , Tamb = 25/g176C) Parameter Test Conditions Symbol 6.76438 MHz Osc. (MODE: 1) 4.90625 MHz Osc. (MODE: 0) Variable Oscillator Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25/g176C) Parameters Test Conditions Symbol Min. Typ. Max. Unit Current consumption Sleep mode (XTO and polling logic active) IS off 170 276 µA IC active (start-up-, bit check-, receiving mode) Pin DATA = H FSK ASK IS on 7.5 7.1 9.1 8.7 mA mA LNA Mixer (Input Matched According to Figure 6) Third-order intercept point LNA/mixer/IF amplifier IIP3 -28 dBm LO spurious emission at RF In Required according to I-ETS 300220 IS LORF -73 -57 dBm Noise figure LNA and mixer (DSB) NF 7 dB LNA_IN input impedance at 433.92 MHz at 315 MHz Zi LNA_IN 1.0 || 1.56 1.3 || 1.0 k/g87 || pF k/g87 || pF 1 dB compression point (LNA, mixer, IF amplifier) Referred to RFin IP1db -40 dBm

4569A–RKE–12/02 Maximum input level BER /g163 10-3, FSK mode ASK mode Pin_max -22 -20 dBm dBm Local Oscillator Operating frequency range VCO f VCO 299 449 MHz Phase noise VCO/LO f osc = 432.92 MHz at 1 MHz at 10 MHz L (fm) -93 -113 -90 -110 dBC/Hz dBC/Hz Spurious of the VCO at ± f XTO -55 -47 dBC VCO gain K VCO 190 MHz/V Loop bandwidth of the PLL For best LO noise (design parameter) R1 = 820 /g87 C9 = 4.7 nF C10 = 1 nF B Loop 100 kHz Capacitive load at Pin LF The capacitive load at Pin LF is limited if bit check is used. The limitation therefore also applies to self polling. CLF_tot 10 nF XTO operating frequency XTO crystal frequency, appropriate load capacitance must be connected to XTAL fXT AL = 6.764375 MHz (EU) fXT AL = 4.90625 MHz (US) fXTO -30 ppm f XT AL +30 ppm MHz Series resonance resistor of the crystal fXTO = 6.764 MHz, fXTO = 4.906 MHz RS 150 220 /g87 /g87 Static capacitance at Pin XTO to GND C0 6.5 pF Analog Signal Processing Input sensitivity ASK 300 kHz IF-filter Input matched according to Figure 6 ASK (level of carrier) BER /g163 10-3, BW = 300 kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25/g176C, fIF = 1 MHz BR_Range0 BR_Range1 BR_Range2 BR_Range3 P Ref_ASK -109 -107 -106 -104 -111 -109 -108 -106 -113 -111 -110 -108 dBm dBm dBm dBm Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25/g176C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

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4569A–RKE–12/02 Input sensitivity ASK 600 kHz IF-filter Input matched according to Figure 6 ASK (level of carrier) BER /g163 10-3, BW = 600kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25/g176C, fIF = 1 MHz BR_Range0 BR_Range1 BR_Range2 BR_Range3 P Ref_ASK -108 -106.5 -106 -104 -110 -108.5 -108 -106 -112 -110.5 -110 -108 dBm dBm dBm dBm Sensitivity variation ASK for the full operating range compared to T amb =2 5/g176C, VS =5V 300 kHz and 600 kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz, PASK = PRef_ASK + /g68PRef /g68PRef +2.5 -1.5 dB Sensitivity variation ASK for full operating range including IF-filter compared to Tamb =2 5/g176C, VS = 5 V, 300 kHz version fin = 433.92 MHz/315 MHz fIF = 0.89 MHz to 1.11 MHz fIF = 0.86 MHz to 1.14 MHz PASK = PRef_ASK + /g68PRef /g68PRef +5.5 +7.5 -1.5 -1.5 dB dB 600 kHz version f in = 433.92 MHz/315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + /g68PRef /g68PRef +5.5 +7.5 -1.5 -1.5 dB dB Input sensitivity FSK 300 kHz IF-filter Input matched according to Figure 6 BER /g163 10-3, BW = 300 kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25/g176C fIF = 1 MHz BR_Range0 df = ±16 kHz df = ±10 kHz to ±30 kHz PRef_FSK -101 -99 -104 -105.5 -105.5 dBm dBm BR_Range1 df = ±16 kHz df = ±10 kHz to ±30 kHz PRef_FSK -99 -97 -102 -103.5 -103.5 dBm dBm BR_Range2 df = ± 16 kHz df = ±10 kHz to ±30 kHz P Ref_FSK -97.5 -95.5 -100.5 -102 -102 dBm dBm BR_Range3 df = ±16 kHz df = ±10 kHz to ±30 kHz PRef_FSK -95.5 -93.5 -98.5 -100 -100 dBm dBm Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25/g176C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4569A–RKE–12/02 Input sensitivity FSK 600 kHz IF-filter Input matched according to Figure 6 BER /g163 10-3, BW = 600 kHz fin = 433.92 MHz/315 MHz VS = 5 V, Tamb = 25/g176C fIF = 1 MHz BR_Range0 df = ±16 kHz df = ±10 kHz to ±100 kHz PRef_FSK -101 -99 -104 -105.5 -105.5 dBm dBm BR_Range1 df = ±16 kHz df = ±10 kHz to ±100 kHz P Ref_FSK -99 -97 -102 -103.5 -103.5 dBm dBm BR_Range2 df = ±16 kHz df = ±10 kHz to ±100 kHz PRef_FSK -97.5 -95.5 -100.5 -102 -102 dBm dBm BR_Range3 df = ±16 kHz df = ±10 kHz to ±100 kHz PRef_FSK -95.5 -93.5 -98.5 -100 -100 dBm dBm Sensitivity variation FSK for the full operating range compared to T amb =2 5/g176C, VS = 5 V 300 kHz and 600 kHz version fin = 433.92 MHz/315 MHz fIF = 1 MHz PFSK = PRef_FSK + /g68PRef /g68PRef +3 -1.5 dB Sensitivity variation FSK for the full operating range including IF-filter compared to T amb = 25/g176C, VS = 5 V 300 kHz version fin = 433.92 MHz/ 315 MHz fIF = 0.89 MHz to 1.11 MHz fIF = 0.86 MHz to 1.14 MHz fIF = 0.82 MHz to 1.18 MHz PFSK = PRef_FSK + /g68PRef /g68PRef +11 dB dB dB 600 kHz version fin = 433.92 MHz/ 315 MHz fIF = 0.85 MHz to 1.15 MHz fIF = 0.80 MHz to 1.20 MHz fIF = 0.74 MHz to 1.26 MHz PFSK = PRef_FSK + /g68PRef /g68PRef +11 dB dB dB S/N ratio to suppress inband noise signals. Noise signals may have any modulation scheme ASK mode FSK mode SNR ASK SNRFSK dB dB Dynamic range RSSI ampl. DR RSSI 60 dB Lower cut-off frequency of the data filter CDEM = 33 nF fcu_DF 0.11 0.16 0.20 kHz Recommended CDEM for best performance BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 CDEM 8.2 nF nF nF nF Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25/g176C) Parameters Test Conditions Symbol Min. Typ. Max. Unit fcu_DF

38 T5743

4569A–RKE–12/02 Edge-to-edge time period of the input data signal for full sensitivity BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 t ee_sig 270 156 1000 560 320 180 µs µs µs µs Upper cut-off frequency data filter Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (default) BR_Range1 BR_Range2 BR_Range3 f u 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 kHz kHz kHz kHz Reduced sensitivity R Sense connected from Pin Sens to VS, input matched according to Figure 6 dBm (peak level) RSense = 56 k/g87, fin = 433.92 MHz, at BW = 300 kHz at BW = 600 kHz PRef_Red -71 -67 -76 -72 -81 -77 dBm dBm RSense = 100 k/g87, fin =4 3 3 . 9 2M H z , at BW = 300 kHz at BW = 600 kHz -80 -76 -85 -81 -90 -86 dBm dBm R Sense = 56 k/g87, fin = 315 MHz, at BW = 300 kHz at BW = 600 kHz -72 -68 -77 -73 -82 -78 dBm dBm RSense = 100 k/g87, fin =3 1 5M H z , at BW = 300 kHz at BW = 600 kHz -81 -77 -86 -82 -91 -87 dBm dBm Reduced sensitivity variation over full operating range RSense = 56 k/g87 RSense = 100 k/g87 PRed = PRef_Red + /g68PRed /g68PRed dB dB Reduced sensitivity variation for different values of RSense Values relative to RSense = 56 k/g87 RSense = 56 k/g87 RSense = 68 k/g87 RSense = 82 k/g87 RSense = 100 k/g87 RSense = 120 k/g87 RSense = 150 k/g87 PRed = PRef_Red + /g68PRed /g68PRed /g68PRed /g68PRed /g68PRed /g68PRed /g68PRed -3.5 -6.0 -9.0 -11.0 -13.5 dB dB dB dB dB dB Threshold voltage for reset V ThRESET 1.95 2.8 3.75 V Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25/g176C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

4569A–RKE–12/02 Digital Ports Data output - Saturation voltage Low - max voltage at Pin DATA - quiescent current - short-circuit current - ambient temperature in case of permanent short-circuit Data input - Input voltage Low - Input voltage High I ol /g163 12 mA Iol = 2 mA Voh = 20 V Vol = 0.8 V to 20 V Voh = 0 V to 20 V Vol Vol Voh Iqu Iol_lim tamb_sc VIl Vich 0.65 /g180/g32VS 0.35 0.08 0.8 0.3 0.35 /g180/g32VS V V V µA mA /g176C V V DATA_CLK output - Saturation voltage Low - Saturation voltage High IDATA_CLK = 1 mA IDATA_CLK = -1 mA V ol Voh VS-0.4 V 0.1 VS-0.15 V 0.4 V V IC_ACTIVE output - Saturation voltage Low - Saturation voltage High IIC_ACTIVE = 1 mA IIC_ACTIVE = -1 mA Vol Voh VS-0.4 V 0.1 VS-0.15 V 0.4 V V POLLING/_ON input - Low level input voltage - High level input voltage Receiving mode Polling mode VIl VIh 0.8 /g180/g32VS 0.2 /g180/g32VS V V MODE input - Low level input voltage - High level input voltage Division factor = 10 Division factor = 14 V Il VIh 0.8 /g180/g32VS 0.2 /g180/g32VS V V TEST input - Low level input voltage Test input must always be set to Low VIl 0.2 /g180/g32VS V Electrical Characteristics (Continued) All parameters refer to GND, Tamb = -40/g176C to +105/g176C, VS = 4.5 V to 5.5 V , f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (For typical values: VS = 5 V, Tamb = 25/g176C) Parameters Test Conditions Symbol Min. Typ. Max. Unit

40 T5743

4569A–RKE–12/02

Package Information

Ordering Information

Extended Type Number Package Remarks T5743P3-TG SO20 Tube, IF bandwidth of 300 kHz T5743P3-TGQ SO20 Taped and reeled, IF bandwidth of 300 kHz T5743P6-TG SO20 Tube, IF bandwidth of 600 kHz T5743P6-TGQ SO20 Taped and reeled, IF bandwidth of 600 kHz technical drawings according to DIN specifications Dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 11 0

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