T4260

T4260 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 AM/FM Tuner Front End with Integrated PLL  AM Up-conversion System (AM-IF: 10.7 MHz)  FM Down-conversion System (FM-IF: 10.7 MHz)  IF Frequencies up to 25 MHz  Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz  Fast Fractional PLL (Lock Time < 1 ms) Inclusive Spurious Compensation  Fast RF-AGC, Programmable in 1-dB Steps  Fast IF-AGC, Programmable in 2-dB Steps  Fast Frequency Change by 2 Programmable N-divider  Two DACs for Automatic Tuner Alignment  High S/N Ratio  3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers-compatible)

Description

The T4260 is an advanced AM/FM receiver with integrated fast PLL as a single-chip solution based on Atmel’s high-performance BICMOS II technology. The low-imped- ance driver at the IF output is designed for the A/D of a digital IF . The fast tuning concept realized in this part is based on patents held by Atmel and allows lock times less than 1 ms for a jump over the FM band with a step width of 12.5 kHz. The AM up-conversion and the FM down-conversion allows an economic filter concept. An automatic tuner alignment is provided by built-in DACs for gain and offset compensa- tion. The frequency range of the IC covers the FM broadcasting band as well as the AM band. The low current consumption helps the designers to achieve economic power consumption concepts and helps to keep the power dissipation in the tuner low. Pin Description Figure 1. Pinning SSO44

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4528G–AUDR–12/03 Pin Description Pin Symbol Function

1 DAC1 DAC1 output

2 DAC2 DAC2 output

3 FMAGCO FM AGC current

4 MXFMIA FM mixer input A

5 MXFMIB FM mixer input B

6 GNDRF RF ground

7 MXAMIB AM mixer input B

8 MXAMIA AM mixer input A

9 AMAGCO AM AGC current

10 IFAGCA2 AM IF-AGC filter 2

11 SW2/AGC Switch 2 / AM AGC voltage

12 RFAGCA2 RF AM-AGC filter 2

13 SW1 Switching output 1

14 VRVCO VCO reference voltage

15 VSPLL PLL supply voltage

16 FMLF FM loop filter

17 AMLF AM loop filter

18 VTUNE T uning voltage

19 OSCGND Oscillator ground

20 OSCE Oscillator emitter

21 OSCB Oscillator base

22 OSCBUF Oscillator buffer output/input

23 EN 3-wire bus Enable

24 CLK 3-wire bus Clock

25 DATA 3-wire bus Data

26 VRPLL PLL reference voltage

27 REFFREQ PLL reference frequency

28 GNDPLL PLL ground

29 IFOUTB IF output B

30 IFOUTA IF output A

31 IFAGCFM FM IF-AGC filter

32 IFAGCA1 AM IF-AGC filter 1

33 RFAGCFM RF FM-AGC filter

34 IFREF IF amplifier reference input

35 IFINAM IF amplifier AM input

36 IFINFM IF amplifier FM input

37 VRT T uner reference voltage

38 GNDT T uner ground

39 MXAMOB AM mixer output B

40 MXAMOA AM mixer output A

41 VST T uner supply voltage

42 RFAGCA1 RF AM-AGC filter 1

43 MXFMOA FM mixer output A

44 MXFMOB FM mixer output B

4528G–AUDR–12/03 Figure 2. Block Diagram The T4260 implements an AM up-conversion reception path from the RF input signal to the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the LO frequency to the AM mixer. The FM reception path generates the same LO frequency from the RF input signal by a down- conversion to the IF output. The IF A/D output is designed for digital signal processing. The IF can be chosen in the range of 10 MHz to 25 MHz. Automatic gain control (AGC) circuits are implemented to control the preamplifier stages in the AM and FM reception paths. For improved performance, the PLL has an integrated special 2-bit shift fractional logic with spurious suppression that enables fast frequency changes in AM and FM mode by a low step frequency (f PDF). In addition, two programmable DACs (Digital to Analog Converter) support the alignment via a microcontroller. For a double-tuner concept, external voltage can be applied at the input of the DACs, the internal PLL can switched off and the OSC buffer (output) can also be used as input. Several register bits (Bit 0 to Bit 145) are used to control the circuit’s operation and to adapt certain circuit parameters to the specific application. The control bits are orga- nized in four 8-bit, four 16-bit and three 24-bit registers that can be programmed by the 3-wire bus protocol. The bus protocol and the bit-to-register mapping is described in the section “3-wire Bus Description” on page 9. The meaning of the control bits is mentioned in the following sections. AGC PLL SUPPLY AGC DIV N DIV R DIV PD RF/IF SUPPLY BUS VCO FMAGCO GNDRF MXAMIB MXAMIA MXFMIB MXFMIA AMAGCO AM FM MXFMOB MXAMOB MXAMOA IFREF IFINAM ININFM IFOUTB IFOUTA IFAGCFM IFAGCA1 VST VRT GNDT VSPLL VRPLL GNDPLL EN CLK DATA SW1 SW2/AGC VTUNEAMLFFMLFREFFREQ OSCGND OSCE OSCB OSCBUF RFAGCA2 RFAGCFM RFAGCA1 VRVCO DAC1 DAC2 IFAGCA2 SW-AMLF MXFMOA 44 39 40 34 35 36 29 30 31 10 32 16 17 1822 21 20 19 27

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4528G–AUDR–12/03 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referred to GND Parameters Symbol Value Unit Analog supply voltage Pins 15 and 41 V ST, VSPLL 10 V Maximum power consumption P tot 1.0 W Ambient temperature range T amb -40 to +85 ° C Storage temperature range T stg -40 to +150 ° C Junction temperature T j 150 ° C Thermal Resistance Parameters Symbol Value Unit Junction ambient, soldered to PCB R thJA 52 K/W Operating Range Parameters Symbol Min. Typ. Max. Unit Supply voltage range (1) Pins 15 and 41 V ST, VSPLL 88 . 5 1 0V Ambient temperature T amb -40 85 ° C Oscillator frequency Pin 21 R fi 60 175 MHz Note: 1. V ST and VSPLL must have the same voltage.

Electrical Characteristics

Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

1 Power Supply

1.1 Supply voltage 15,

41 VS 88 . 51 0 VC

1.2 Supply current AM and FM mode,

VS = 10 V 15,

41 IS 70 85 110 mA A

2.1 Programmable

R-divider 14-bit register 3 16383 A 2.2 Programmable (VCO) N-divider (1 kHz step frequency) 2- × 18-bit register switchable via Bit 5 3 262143 A

2.3 Reference oscillator

input voltage f = 0.1 MHz to 3 MHz 27 100 mV rms B

2.4 Reference frequency FM

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40 ° C to +85° C) but are tested at +25° C

4528G–AUDR–12/03 2.5 Settling time in FM mode (switching from

87.5 MHz to 108 MHz

or vice versa) fPD = 50 kHz IPD = 2 mA 1m s B

3 AMLF/FMLF

3.1 Output current 1 FMLF , AMLF = 1.8 V 16, 17 40 50 60 µA A (1) 3.2 Output current 2 FMLF , AMLF = 1.8 V 16, 17 80 100 120 µA A (1) 3.3 Output current 3 FMLF , AMLF = 1.8 V 16, 17 850 1000 1250 µA A (1) 3.4 Output current 4 FMLF , AMLF = 1.8 V 16, 17 1650 2000 2450 µA A (1) 3.5 Leakage current FMLF , AMLF = 1.8 V 16, 17 10 nA A (1)

4 VTUNE

4.1 Saturation voltage

LOW VSATH = (VA-VPDOFM)1 8 V SA TL 100 200 400 mV C

4.2 Saturation voltage

HIGH VSATH = (VA-VPDOFM)1 8 V SATH 500 mV C

5 DAC1, DAC2

5.1 Output current 1, 2 I DAC1,2 1m A D

5.2 Output voltage 1, 2 V DAC1,2 0.3 V S-0.6 V A 5.3 Maximum offset range Offset = 0, gain = 58 1, 2 0.9 0.98 1.1 V A (1) 5.4 Minimum offset range Offset = 127, gain = 58 1, 2 -0.9 -0.98 -1.1 V A (1) 5.5 Maximum gain range Gain = 255, offset = 64 1, 2 2.06 2.09 2.13 – A (1) 5.6 Minimum gain range Gain = 0, offset = 64 1, 2 0.63 0.67 0.73 – A (1)

6 Oscillator

6.1 Frequency range 21 60 170 MHz B

6.2 Fractional frequency

range Fractional mode 21 60 140 MHz A

6.3 Buffer output 22 150 mV rms C

7 Oscillator Input

7.1 Input voltage 21 V OSC 150 mV rms A

8 FM Mixer

8.1 Frequency range 75 163 MHz B

8.2 Input IP3 133 dBµV C

8.3 Input impedance 3.5 k Ω D

8.4 Input capacitance 4p F D

8.5 Noise figure F 14 dB C

8.6 Conversion

transconductance 2.6 3.1 3.6 ms D (1) Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40 ° C to +85° C) but are tested at +25° C

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4528G–AUDR–12/03

9 AM Mixer (Symmetrical Input)

9.1 Frequency range 0.075 26 MHz B

9.2 Input IP3 133 dBµV C

9.3 Input impedance 2.5 k Ω D

9.4 Noise figure F 10 dB C

9.5 Conversion

transconductance 2.6 3.1 3.6 mS D (1)

10 Isolation

10.1 Isolation AM-FM 40 dB C

10.2 IF suppression 40 dB C

11 RF-AGC

11.1 Frequency range FM

0.075 163 MHz MHz A

11.2 Output current FM

11.3 Output current time

C 11.4 RF-AGC AM threshold (programmable with Bit 12 - Bit 15) 88 dBµV 42 87 88 90 dBµV A (1) 89 dBµV 42 88 89 91 dBµV A (1) 90 dBµV 42 89 90 92 dBµV A (1) 91 dBµV 42 90 91 93 dBµV A (1) 92 dBµV 42 91 92 94 dBµV A (1) 93 dBµV 42 92 93 95 dBµV A (1) 94 dBµV 42 93 94 96 dBµV A (1) 95 dBµV 42 94 95 97 dBµV A (1) 96 dBµV 42 95 96 98 dBµV A (1) 97 dBµV 42 96 97 99 dBµV A (1) 98 dBµV 42 97 98 100 dBµV A (1) 99 dBµV 42 98 99 101 dBµV A (1) 100 dBµV 42 99 100 102 dBµV A (1) 101 dBµV 42 100 101 103 dBµV A (1) 102 dBµV 42 101 102 104 dBµV A (1) 103 dBµV 42 102 103 107 dBµV A (1) Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40 ° C to +85° C) but are tested at +25° C

4528G–AUDR–12/03 11.5 RF-AGC FM threshold (programmable with Bit 12 - Bit 15) 91 dBµV 33 90 91 93 dBµV A (1) 92 dBµV 33 91 92 95 dBµV A (1) 93 dBµV 33 92 93 96 dBµV A (1) 94 dBµV 33 93 94 96 dBµV A (1) 95 dBµV 33 94 95 98 dBµV A (1) 96 dBµV 33 95 96 99 dBµV A (1) 97 dBµV 33 96 97 102 dBµV A (1) 98 dBµV 33 97 98 101 dBµV A (1) 99 dBµV 33 98 99 102 dBµV A (1) 100 dBµV 33 99 100 104 dBµV A (1) 101 dBµV 33 100 101 104 dBµV A (1) 102 dBµV 33 101 102 105 dBµV A (1) 103 dBµV 33 102 103 106 dBµV A (1) 104 dBµV 33 103 104 107 dBµV A (1) 105 dBµV 33 104 105 108 dBµV A (1) 106 dBµV 33 105 106 109 dBµV A (1)

12 IF Amplifier

12.1 Frequency range 10 25 MHz A

12.2 Output voltage 117 dBµV B

12.3 Distortion

(2-tone IM3) f1 = 10.7 MHz f2 = 10.75 MHz RL = 2 × 300 Ω 55 dB A

12.4 Gain (programmable in

2-dB steps) Minimum gain Maximum gain dB dB A

12.5 Input impedance FM

36, 330 2500 Ω Ω D

13 IF-AGC

13.1 IF-AGC AM/FM threshold (programmable with Bit 0 - Bit 2) 109 dBµV 29/30 108 109 112 dBµV A (1) 111 dBµV 29/30 110 111 114 dBµV A (1) 113 dBµV 29/30 111 113 115 dBµV A (1) 115 dBµV 29/30 113 115 117 dBµV A (1) 117 dBµV 29/30 116 117 121 dBµV A (1) 118 dBµV 29/30 117 118 122 dBµV A (1) 119 dBµV 29/30 118 119 123 dBµV A (1) 121 dBµV 29/30 120 121 126 dBµV A (1)

13.2 AGC dynamic range 40 dB B

13.3 AGC time constant (external capacity ≤100 nF) FM rising FM falling AM symmetrical 200 µs ms ms D Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40 ° C to +85° C) but are tested at +25° C

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4528G–AUDR–12/03

14 IF Gain

14.1 IF gain (programmable with Bit 6 - Bit 9) 12 dB 9 12 14 dB A (1) 14 dB 12 14 16 dB A (1) 16 dB 14 16 18 dB A (1) 18 dB 17 18 20 dB C (1) 20 dB 17 20 22 dB A (1) 22 dB 19 22 24 dB C (1) 24 dB 21 24 26 dB C (1) 26 dB 23 26 28 dB C (1) 28 dB 25 28 30 dB A (1) 30 dB 27 30 32 dB C (1) 32 dB 29 32 34 dB C (1) 34 dB 31 34 36 dB C (1) 36 dB 33 36 38 dB C (1) 38 dB 35 38 40 dB C (1) 40 dB 37 40 42 dB C (1) 42 dB 39 42 44 dB A (1)

15 SWO1 (Open Drain)

15.1 Output voltageLOW

I = 1 mA, VSWO1 = 8.5 V

13 V SWOL 100 160 200 mV A

15.2 Output leakage current

HIGH 13 I OHL 10 µA A 15.3 Maximum output voltage 13 8.5 V C

16 SW2/AGC (Open Drain in Switch Mode)

16.1 Output voltage LOW

I = 1 mA, V11 = 6 V

11 V SWOL 100 160 200 mV A

16.2 Output leakage current

HIGH 11 I OHL 10 µA A

16.3 Maximum output voltage 11 6 V C

17 3-wire Bus, ENABLE, DATA, CLOCK

17.1 Input voltage High

2.7 -0.3 5.3 +0.8 V V A A 17.2 Clock frequency 24 1.0 MHz B

17.3 Period of CLK 24 tH

C C

17.4 Rise time EN, DA, CLK 23-25 t R 400 ns C

17.5 Fall time EN, DA, CLK 23-25 t F 100 ns C

17.6 Set-up time 23-25 t S 100 ns C

17.7 Hold time EN 23 t HEN 250 ns C

17.8 Hold time DA 25 tHDA 0 ns C

Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40 ° C to +85° C) but are tested at +25° C

4528G–AUDR–12/03 3-wire Bus The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus protocol consists of separate commands. A defined number of bits is transmitted sequentially during each command. One command is used to program all bits of one register. The different registers avail- able (see chapter “3-wire Bus Data Transfer” on page 11) are addressed by the length of the command (number of transmitted bits) and by two address bits that are unique to each register of a given length. 8-bit registers are programmed by 8-bit commands, 16- bit registers are programmed by 16-bit commands and 24-bit registers are programmed by 24-bit commands. Each bus command starts with a falling edge on the enable line (EN) and ends with a rising edge on EN. EN has to be kept LOW during the bus command. The sequence of transmitted bits during one co mmand starts with the MSB of the first byte and ends with the LSB of the last byte of the register addressed. To transmit one bit (0/1), DATA has to be set to the appropriate value (LOW/HIGH) and a LOW-to-HIGH transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is evaluated at the rising edges of CLK. The number of LOW-to-HIGH transitions on CLK during the LOW period of EN is used to determine the length of the command. Figure 3. 3-wire Pulse Diagram

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Figure 4. 3-wire Bus Timing Diagram

Table 1. Control Registers

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4528G–AUDR–12/03 Note: 1. Value has to be 0. Note: 1. Value has to be 0. Note: 1. Value has to be 0. A16_00 MSB BYTE 1 LSB MSB BYTE 2 LSB DAC1-Offset ADDR. x x x x x SHIFT x2 6 25 24 23 22 21 20 00 0 0 0 0 0 1) 1/0 31 30 29 28 27 26 25 24 x x 37 36 35 34 33 32 A8_11 MSB BYTE 1 LSB ADDR. Delay time high cur. CP2 Delay time high cur. CP1 x HCDEL

11 ON/

LO 01) 1/0 x x 23 22 21 20 19 18 A8_10 MSB BYTE 1 LSB ADDR. AM/ FM IF- AGC RF-AGC 10 1 / 0 1 / 0 2 3 22 21 20 x x 17 16 15 14 13 12 A8_01 MSB BYTE 1 LSB ADDR. IF-IN VCO IF-Gain

01 AM/

A8_00 MSB BYTE 1 LSB ADDR. N2/N1 PLL ON/ OFF PD TE/ PD IF-AGC 00 1 / 0 1 / 0 0 1) 22 21 20 xx 5 4 3 2 1 0

The IF-AGC threshold can be controlled by setting Bits 0 to 2 as given in Table 2. Table 2. IF-AGC Threshold The IF-AGC ON/OFF can be controlled by Bit 16 as given in Table 3. Table 3. IF-AGC application. For normal operation Bit 3 has to be set to 0. Table 4. PD-Test Mode N1/N2 The N2/N1 Bit controls the active N-divider. Only one of the two N-Divider can be active. The N1-Divider is activated by setting Bit 5 = 0, the N2-Divider by setting Bit 5 = 1. Table 5. N-Divider

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external ceramic bandfilters. The IF gain can be controlled in 2-dB steps by setting Bit 6 to Bit 9 as given in Table 6. Table 6. IF Gain The selection of the IF amplifier input can be controlled by Bit 11 as given in Table 7. Table 7. IF-IN Operating Mode The AM input (Pin 35) has an input impedance of 2.5 kΩ for matching with a crystal filter. VCO The VCO HI/LO function is controlled by means of Bit 10. Table 8. VCO Operating Mode FM and AM are controlled by Bit 17.

Table 9. RF-AGC IF FM amplifier (input at Pin 36) are activated. 145 = 0 and to Pin 17 (with the external AM loopfilter) by Bit 145 = 1. The AM/FM function for the tuner part is controlled by Bit 17 as given in Table 10. Table 10. Tuner Operating Modes Table 11. PLL Mode (HCDEL) determines whether register HCDEL 1 or 2 is used. Table 12. High-current Charge Pump Delay Time Register

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Table 13. Delay Time of HCDEL Register the R-divider has to be a multiple of 4. Table 14. Manual and Lock Detect Shift Mode SW1 (Pin 13) The switching output SW1 (Pin 13) is controlled by Bit 46 as given in Table 15. Table 15. Switching Output REMARK: SW1 is an open-drain output. Figure 5. Internal Components at SW1

control pin to control the cascade stage of an external AM-preamplifier. The SW2/AGC is controlled by Bits 47 and 48 as given in Table 16. Table 16. Switching Output 2 / AGC Mode REMARK: In AGC mode, the output voltage is 6 V down to 1 V. Figure 6. Internal Components at SW2/AGC normal operation Bit 123 has to be set to 0. Table 17. Test Mode frequency from the VCO frequency. The VCO divider can be controlled by the Bits 140 to 143 as given in Table 18.

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Table 18. Divider Factor of the AM Prescaler frequency. The VCO frequency is used as LO frequency for the mixer. Table 19. Loop Filter Operating Mode step frequency. After the frequency change, the normal step frequency is active again. active N-Divider are not used in this mode. The shift bits are interpreted as logic 0. quency changes with a step frequency of 12.5 kHz. Table 20. Fractional Mode Table 21. Spurious Suppression by SW Wire

Table 22. Spurious Suppression by Correction Current Charge Pump to the chosen pump current and the internal reference frequency. register to 0 (Bit 20 and Bit 21 [HCDEL 1] or Bit 22 and Bit 23 [HCDEL 2]). The current of the high-current charge pump is controlled by Bit 62 as given in Table 23. Table 23. High-current Charge Pump The current of the low-current charge pump is controlled by Bit 63 as given in Table 24. Table 24. Low-current Charge Pump be applied (Bit 65 = 0). If this is not done, the IC operates in standard mode (Bit 65 = 1). Table 25. Oscillator Operating Modes

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and the IF filter. For alignment, offset and gain are set for having the best tuner tracking. Figure 7. Block Diagram of DAC1, 2 Table 26. Gain of DAC1, 2 DAC2 can be controlled by the Bits 52 to Bit 58 (20 to 26) as given in Table 27.

Table 27. Offset of DAC1, 2

0.9815 V 0 0 0 0 0 0 0 0

0.9659 V 0 0 0 0 0 0 1 1

0.9512 V 0 0 0 0 0 1 0 2

0.9353 V 0 0 0 0 0 1 1 3

22 T4260

18) with the desired voltage gain and offset value. may not remain for a longer period of time. input voltage of the internal OP input voltage does not exceed 0.5 V. Figure 8. Internal Components of DAC1, 2

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4528G–AUDR–12/03 Figure 11. Block Diagram of the PLL Core The two N-dividers are stored in two 18-bit memory register (LATCH N-DIV) and the R-divider in a 14-bit memory register (LATCH R-DIV). One of the the two N-dividers (N1 or N2) can be activated by Bit 5 as active N-divider (with the 18-bit multiplexer MUX). The (divider) 2-bit shift mode can be activated with Bit 32 = 0. The N- and R-divider are shifted two bits to the right in this shi ft mode. Because the two lowest R-divider bits (Bit 124 and Bit 125) are 0 they do not have to be evaluated. In opposite to the R-divider the lowest two N-divider bits (Bit 102 an d Bit 103 or Bit 80 and Bit 81, depends on the active N-divider) are special evaluated in the ACCU block if fractional mode is active (Bit 144 = 0). The two lowest N- and R-divider bits are also called shift bits. The SWITCH N+1, N block is steering the di vision through N or N+1 in the N-divider if fractional and 2-bit shift mode are active. Ther e is only a division by N if the fractional mode is deactivated in 2-bit shift mode. The output signals of the 18-bit N-divider and 14-bit R-divider will be compared in the PHASEDETECTOR which one activates the sink and source currents of the charge pumps (CP). LATCH R - DIV. SHIFT 2 BIT R - DIVIDER DELAYTIME high cur. CP SWITCH PHASE DETECTOR CHARGE PUMP AM/FM FILTER N / N+1 DIVIDER PREAMP SWITCH N+1, N ACCU 2 - BIT SHIFT 2 BIT MUX N1 N2 LATCH N - DIV 1 LATCH N - DIV 2 VCO FM - LOOP FILTER AM - LOOP FILTER B60, B144 2-BIT (LSB) 18 - BIT18 - BIT BIT 18 Fref 14 - BIT B145 AM / FM BIT 32 HCDEL 1 HCDEL 2 B62,63 B61

4528G–AUDR–12/03 There are also two HCDEL registers (for the high current CP delay time) but only one of them is active. One of the HCDEL registers can be activated by Bit 18. The delay time of the HCDEL register can be selected with Bit 20 and Bit 21 or Bit 22 and Bit 23). The current for the high CP (HCCP) can be set by Bit 62 and the current for the low current CP (LCCP) by Bit 63. With Bit 145 the AM- or FM-Loopfilter (pin) can be activated. It is also possible to use the AM-Loopfilter in FM mode (instead of the FM-Loopfilter) or the FM-Loopfilter in AM mode. High-speed Tuning The fractional mode (Bit 144 = 0) in connection with the direct shift mode (Bit 32 = 0) allows very fast frequency changes with four times the step frequency (50 kHz = 4 × f PDF) at low frequency steps (e.g., f PDF = 12.5 kHz). In direct shift mode, the R- and the N-divider are shifted by 2 bits to the right (this corresponds to a R- and N-divider division by 4 or a step frequency multiplication by 4). Due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of 3- 4 ms for a tune over the whole FM band from 87.5 MHz to 108 MHz is possible with f PDF =1 2 . 5k H z . If the FM receiving frequency is 103.2125 MHz (with e.g. f PDF = 12.5 kHz and fIF = 10.7 MHz), an N-divider of 9113 and an R-divider of 12 are necessary when using a reference-frequency (fref) of 150 kHz. fVCO = fIF + frec = 10.7 MHz + 103.2125 MHz = 113.9125 MHz fPDF = fVCO / N = fref / R = 113.9125 MHz / 9113 = 150 kHz /12 = 12.5 kHz An important condition for the use of the fractional mode is an R-divider with an integer value after the division by 4 (R-dividers have to be a multiple of 4). After a 2-bit shift (divider division by 4), the R-divider is now 3 (instead of 12) and the N-divider is 2278.25 (instead of 9113). The new N-divider of 2278.25 is also called ¼ fractional step because the modulo value of the N-divider is 0.25 = ¼. In total, there are 4 different fractional 2-bit shift steps: full, ¼, ½ and ¾ step. If the fractional mode is switched off (Bit 144 = 1) during direct shift mode (Bit 32 = 0), the modulo value of the N-divider will be ignored (the new N-divider is then 2278 instead of 2278.25). This means that the PLL locks on the next lower multiple frequency of 4 × f PDF (in our case fPDF = 12.5 kHz). The new VCO frequency (fVCO) is then 113.9 MHz (instead of 113.9125 MHz in fractional mode). Also the PLL has additionally a special fractional logic which allows a good spurious suppression in the fractional and direct shift mode. Activating the wire switch (Bit 60 = 1) and the correction charge pump (Bit 60 = 1) the spurious suppression is active.

26 T4260

(0 = 50 µA; 1 = 100 µA). A lower charge pump current guarantees a higher S/N ratio. Table 28 lists the AM prescaler (divider) settings and the reception frequencies. Table 28. AM Prescaler (Divider) Settings and the Reception Frequencies ple. The tuning range depends on the tuning diode and the inductor in the VCO circuit. to VSPLL - 1 V for a good S/N performance.

11540 and a R-Divider of 400 is necessary. age factor ratio of 100/16 (R1/R2) is required. allowed range of R1 is 10 kΩ to 1 MΩ and 1.6 kΩ to 160 kΩ for R2. Figure 12. External Voltage at AMLF (Pin 17) settings have to be observed (see chapter “Permitted DAC Conditons” on page 22). SWAMLF voltage should be limited to a voltage lower than 0.83 V.

28 T4260

Figure 13. Test Circuit

2 RFAGCFM

Figure 14. Application Circuit

30 T4260

4528G–AUDR–12/03

Package Information

Ordering Information

Extended Type Number Package Remarks T4260IL SSO44 Tube T4260ILQ SSO44 Taped and reeled technical drawings according to DIN specifications Dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22

Printed on recycled paper. Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standar d warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel produc ts, expressly or by implication. Atmel’s products are not aut horized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations

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Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Memory San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602

44306 Nantes Cedex 3, France

13106 Rousset Cedex, France

1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535

74025 Heilbronn, Germany

1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123

38521 Saint-Egreve Cedex, France

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