T2803_05 ATMEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 28
Technical content
Features
- Supply-voltage Range 3V to 4.6V (Regulated) Auxiliary Voltage Regulator On-chip (3.2V to 4.6V) Low Current Consumption Few Low-cost External Components No Mechanical Tuning Required Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz) Fast Settling Synthesizer (864 kHz Channel Spacing) TX Preamplifier with 3 dBm Output Power at 2.45 GHz (4 Programmable Power Levels) Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power Amplifier (T7024 and T7026) Electrostatic sensitive device. Observe precautions for handling. 1. Description The T2803 is an RF IC for low-power applications in the 2.45 GHz ISM band. The QFN48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO and Gaus- sian data filter for TX. No mechanical tuning is necessary in production. Figure 1-1. Block Diagram TANK PC RC GF CP VCO f : n f : n CTRL LOGIC PD TX/RX SWITCH IR MIXER IF AMP 1 IF AMP 2 DEMOD BB FILTER 3-WIRE BUS DEMOD DAC RSSI TX DRIVER CLOCK DATA ENABLE RX_ON TX_ON PU_RX/TX PU_PLL TX_DATA RSSI BB_OUT CF DEMOD IF_TANKIF_IN MIXER OUT RF_IN TX_OUT VS_VCO CP LD REF_CLK VTUNE VREG VS_REG REG_CTRL VREG_VCO VCO REG RAMP GEN RAMP_OUT RAMP_SET AUX REG OLE PU_REGGND_VCO D/A I_CPSW RAMP D/A
2.4 GHz
Rev. 4572I–DECT–07/05
4572I–DECT–07/05 T2803 2. Pin Configuration Figure 2-1. Pinning QFN48 Table 1-1. Functional Block Description Name Description AUX REG Auxiliary voltage regulator BBF Baseband filter CP Charge pump DAC D/A converter for demodulator tuning DEMOD Demodulator GF Gaussian filter for transmit data IF AMP1 1st intermediate frequency amplifier IF AMP2 2nd intermediate frequency amplifier IR MIXER Image rejection mixer PC Programmable counter PD Phase detector RAMP GEN Ramp-signal generator RC Reference counter RSSI Received signal-strength indicator TX DRIVER Buffer amplifier for TX_OUT TX/RX SWITCH Switches VCO signal to IR MIXER respectively TX DRIVER VCO Voltage-controlled oscillator VCO REG Voltage regulator for VCO CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 T2803 RX_ON TX_ON OLE TX_DATA VS_M IXER GND_PLL PU_RX/TX PU_PLL I_CPSW RAM P_SET CP GND_VCO VS_VCO GND1 VTUNE VREG_VCO BB_OUT DAC_DEC BB_CF REG_DEC DEM OD_TANK2 DEM OD_TANK1
4572I–DECT–07/05 T2803 Table 2-1. Pin Description Pin Symbol Function Configuration CLOCK DATA ENABLE 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input
4 REF_CLK Reference-frequency input
5 LD Lock-detect output
6 PU_REG Power-up input for auxiliary voltage regulator
1,2,3 5k 5k VS_PLL GND_PLL VS_PLL REF_CLK 10k GND_PLL 10k GND_PLL 100 LD PU_REG 6 25k 25k GND_PLL
4572I–DECT–07/05 T2803
7 VS_PLL PLL supply voltage
REG_CTRL VS_REG Auxiliary voltage-regulator output Auxiliary voltage-regulator control output Auxiliary voltage-regulator supply voltage GND_CP VS_CP CP Charge-pump ground Charge-pump supply voltage Charge-pump output Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL VREG REG_CTRL VS_REG GND_PLL VS_PLL VS_CP CP GND_CP VS_PLL GND_PLL
4572I–DECT–07/05 T2803 VS_VCO VREG_VCO GND_VCO VCO voltage-regulator supply voltage VCO voltage-regulator control output VCO ground
17 VTUNE VCO tuning voltage input
18 GND1 Ground
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration VS_VCO GND_VCO VREG_VCO VS_PLL GND_PLL VTUNE GND_VCO VREG_VCO VS_PLL GND_PLL GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
4572I–DECT–07/05 T2803 DEMOD_TANK1 DEMOD_TANK2 Demodulator tank circuit Demodulator tank circuit
21 DAC_DEC Decoupling pin
22 REG_DEC Decoupling pin for VCO_REG
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration DEMOD TANK1 10k 10k DEMOD TANK2 VS_MIXER GND1 VS_IF GND2 DAC_DEC 10k GND_VCO 400 VREG_VCO VS_PLL GND_PLL REG_DEC 42k VREG_VCO GND_VCO VS_IF GND2
4572I–DECT–07/05 T2803
23 BB_CF Baseband filter corner-frequency control
24 BB_OUT Baseband filter output
25 RSSI Received signal strength indicator output
IF_TANK1 IF_TANK2 IF tank circuit IF tank circuit Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration BB_CF VS_IF GND1 GND2 VS_IF GND1 BB_OUT GND2 VS_IF RSSI 13k GND2 IF_TANK1 VS_IF GND2
4572I–DECT–07/05 T2803
28 GND2 Ground
RF_IN1 RF_IN2 RF input of image reject mixer RF input of image reject mixer
31 GND3 Ground
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL RF_IN1 GND2 VS_MIXER RF_IN2 GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
4572I–DECT–07/05 T2803
32 TX_OUT TX driver amplifier output for PA
33 VS_IF IF amplifier supply voltage
IF_IN1 IF_IN2 IF input of IF amplifier IF input of IF amplifier
36 RAMP_OUT Ramp-generator output for PA power
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration TX_OUT GND3 GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL IF_IN1 IF_IN2 90k VS_IF GND2 VS_MIXER GND2 RAMP_OUT VS_IF
4572I–DECT–07/05 T2803
37 RAMP_SET Slew-rate setting of ramping signal
RX_ON TX_ON RX control input TX control input MIXER_OUT1 MIXER_OUT2 Mixer output to SAW filter Mixer output to SAW filter Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration 100 RAMP SET VS_MIXER GND2 VS_IF RX_ON TX_ON 38, 39 5k 5k VS_IF GND1 GND2 270 270 MIXER_OUT2 MIXER_OUT1 GND2 VS_MIXER VS_IF
4572I–DECT–07/05 T2803 VS_MIXER GND_PLL Mixer supply voltage PLL ground
44 OLE Open loop enable input
45 PU_RX/TX RX/TX power-up input
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL OLE 5k 5k VS_PLL GND_PLL PU_RX/TX GND18 25k 25k
4572I–DECT–07/05 T2803
46 PU_PLL PLL power-up input
47 TX_DATA TX data input of Gaussian filter
48 I_CPSW Charge-pump current control input
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration PU PLL 25k 25k 10k 10k 140k GND PLL 10k 20k 5k 5k VS_PLL TX_DATA 47 2.5k VS_PLL GND_PLL I_CPSW 48 5k VS_PLL GND_PLL
4572I–DECT–07/05 T2803 3. Functional Description
3.1 Receiver
The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF_AMP1 and IF_AMP2 IF amplifiers with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 (≈ 55 MHz) and finally to an inte- grated baseband filter BB. For demodulator tunning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the on-chip varicap diode.
3.2 Transmitter
The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output f requency. After modulation the signal is fre- quency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typically +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is inte- grated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin.
3.3 Synthesizer
The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully inte- grated VCO (including on-chip induc tors and varactors). The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 1.728 MHz). Open loop modulation is supported.
3.4 Power Supply
An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided.
4572I–DECT–07/05 T2803 Figure 3-1. PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO Phase frequency Divider by 2 PA driver detector PD VCO Mixer VCO DAC fPD = 1.728 MHz GF_DATA Gaussian filter GF Reference counter RC 6.912 MHz REF_CLK SRC
13.824 MHz
1.152 Mbit/s
PLL reference TX_DATA Frequency REF_CLK Baseband controller
10.368 MHz
ext. loop filter Charge pump
4572I–DECT–07/05 T2803 Table 3-1 shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Formula TX: f ANT = fVCO = 864 kHz × (32 × SMC + SSC) RX: f ANT = 864 kHz × (32 × SMC + SSC) + fIF 4. Control Signals Table 3-1. LO Frequencies Mode f IF/MHz Channel f ANT/MHz f VCO/MHz S MC SSC N TX – C0 2401.056 2401.056 86 27 2779 C1 2401.920 2401.920 86 28 2780 C93 2481.408 2481.408 89 24 2872 C94 2482.272 2482.272 89 25 2873 RX 110.592 (for 10.368 MHz REF_CLK recommended) C0 2401.056 2290.464 82 27 2651 C1 2401.920 2291.328 82 28 2652 C93 2481.408 2370.816 85 24 2744 C94 2482.272 2371.680 85 25 2745 RX 112.320 (for 13.824 MHz REF_CLK recommended) C0 2401.056 2288.736 82 25 2649 C1 2401.920 2289.600 82 26 2650 C93 2481.408 2369.088 85 22 2742 C94 2482.272 2369.952 85 23 2743 Table 4-1. Control Signals – Functions Signal Functions I_CPSW Charge pump current control PU_REG Activates AUX voltage regulator supplying the complete transceiver PU_RX/TX Activates RX/TX blocks PU_PLL Activates PLL circuits: PC, PD, CP , RC, VCO RX_ON Activates RX circuits: BBF , DEMOD, IF AMP , IR MIXER TX_ON Activates TX circuits: TX-DRIVER, RAMP GEN, Starts RAMP SIGNAL at RAMP OUT OLE Activates open loop mode of the PLL Data Word 1, bit D0 Activates GF
4572I–DECT–07/05 T2803 5. Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed informat ion is loaded into the addressed latches according to the address bit condition (last bit) . Additional leading bits are ignored and there is no check made how many pulses arrived during enable low condition. During enable low condi- tion, the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Data word 2 holds setup information, which is adjusted during production. Table 4-2. Control Signals – Modes Modes TX Mode RX Mode RSSI Only PU_REG 1 1 1 P U _ V C O 111 PU_RX/TX 1 1 1 P U _ P L L 111 R X _ O N 011 T X _ O N 101 BB filter OFF ON OFF Demodulator OFF ON OFF IF amplifiers and RSSI OFF ON ON IR mixer OFF ON ON RX switch OFF ON ON TX switch ON OFF OFF TX driver ON OFF OFF Ramp generator ON OFF OFF Programmable counter ON ON ON Voltage-controlled oscillator ON ON ON Gaussian filter ON OFF OFF Phase detector/charge pump ON ON ON Reference counter ON ON ON Typical current consumption at V S = 3.2V 56 mA 85 mA 82 mA
4572I–DECT–07/05 T2803
5.1 Data Word 1
D11 = x: do not care
5.2 Data Word 2
E3, E4, E5 = x: do not care 6. Data Word 1 Programs
6.1 PLL Settings
D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 R C S C M C V S x 0 G F C S 0000C P C SG F 1 E 1 2 E 1 1E 1 0 E 9E 8E 7E 6E 5E 4E 3E 2E 1E 0A 0 PA DEMODDAC/RAMPDAC x x x TEST 0 Table 6-1. With the Reference Counter bits D22-D22 RC (Reference Counter) D22 S RC REF_CLK 0 6 10.368 MHz 1 8 13.824 MHz Table 6-2. With the Main Counter bits D13-D16 MC (Main Counter) D16 D15 D14 D13 S MC 0000 8 0 0001 8 1 1110 9 4 1111 9 5
4572I–DECT–07/05 T2803
6.2 VCO Selection
6.3 Gaussian Filter On/off
6.4 GFCS Adjustment
Table 6-3. With the Swallow Counter bits D17-D21 SC (Swallow Counter) D21 D20 D19 D18 D17 S SC 000000 000011 000102 11101 2 9 11110 3 0 11111 3 1 Table 6-4. With bit D12 VCO Selection D12 VCO Mode 0V C O 1 1V C O 2 Table 6-5. With bit D0, GF is used only in TX mode D0 GF (Gaussi an Filter) 0O F F 1O N Table 6-6. With bits D7-D9, only in TX mode effective for setting the frequency deviation of the modulation GFCS (Gaussian Filter Settings) D9 D8 D7 GFCS 000 6 0 % 001 7 0 % 010 8 0 % 011 9 0 % 100 1 0 0 % 101 1 1 0 % 110 1 2 0 % 111 1 3 0 %
4572I–DECT–07/05 T2803
6.5 CPCS Adjustment
Note: Used to adjust the charge pump current. This can be used to compensate the change of the tun- ing sensitivity over frequency and device tolerances. 7. Data Word 2 Programs
7.1 DEMODDAC Adjustment
Note: Only in RX mode effective. Used to tune the demodulator center frequency and allows to compen- sate tolerances of external components and the T2803. Table 6-7. With bits D1-D2 CPCS (Charge-Pump Current Settings) D2 D1 CPCS 00 – 1 010 101 112 Table 7-1. With bits E6-E10 Demod DAC Voltage E 1 0 E 9E 8E 7E 6 f IFcenter % 00000 – 5 00001 . . . 00010 . . . 11101 . . . 11110 . . . 11111 5
4572I–DECT–07/05 T2803
7.2 RAMPDAC Adjustment for TX Mode
Note: Only in TX mode effective. Used to control the power of the external PA by adjusting the ramping voltage
7.3 TEST Mode Settings
Note: In normal operation Lock detect output is used. All other settings are for test only.
7.4 Output Power Settings
Note: Use of maximum power (+3 dBm) for external PA is recommended. Table 7-2. With bits E6-E10 RAMPDAC Voltage (at Pin 36 RAMP_OUT) E 1 0 E 9E 8E 7E 6 V RAMP_OUT 00000 1 . 1 V 00001 . . . 00010 . . . 10111 1 . 6 8 V 11000 1 . 7 V 11110 . . . 11111 1 . 7 V Table 7-3. With bits E0-E2 E2 E1 E0 Signal at Lock Detect Output CP Mode 0 0 0 Lock detect Active 0 0 1 PC out/2 Active
010 R C o u t / 2 A c t i v e
110 R C o u t / 2 A c t i v e
1 1 1 GFTEST: RC out Active Table 7-4. With bits E11-E12 PA (Output Power Settings) E12 E11 PA 0 0 –21 dBm 0 1 –11 dBm 1 0 –4 dBm 11 + 3 d B m
4572I–DECT–07/05 T2803 10. Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test require- ment (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. 8. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Pin Symbol Min. Max. Unit Supply voltage regulator 10 V S_REG 3.2 4.7 V Supply voltage 7, 12, 14, 33, 42 V S 3.0 4.7 V Logic input voltage 1, 2, 3, 38, 39, 44-48 VIN –0.3 V S V Junction temperature T jmax 125 °C Storage temperature T stg –40 150 °C 9. Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 25 K/W 11. Operating Range Parameters Pin Symbol Min. Typ. Max. Unit Supply voltage regulator 10 V S_REG 3.2 3.6 4.6 V Supply voltage 7, 14, 33, 42 V S 2.9 3.0 4.6 V Supply voltage charge pump 12 V SCP VS 4.6 V Ambient temperature T amb –10 +60 °C
4572I–DECT–07/05 T2803 12. Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit IR Mixer (Pins 29, 30, 40 and 41) Input impedance Pins 29 or 30 (single ended) Z in 110 + j12 Ω Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Pins 29 or 30 (single ended) NFDSB = NFSSB 10 dB Conversion gain R load = 200Ω Gconv 11 dB Input intercept point Pins 29 or 30 (single ended) IIP3 –7 dBm Output impedance Pin 40 and 41 (differential) Z OUT 175 + j145 Ω IF Amplifier (Pins 26, 27, 34 and 35) Input impedance Pins 34 and 35 (differential) Z in 1200 – j480 Ω Lower cut-off frequency fl 3dB 90 MHz Upper cut-off frequency fu 3dB 130 MHz Power gain Gp 85 dB Bandwidth of external tank circuit Pins 26 and 27 BW3dB 10 MHz Noise figure NF 9 dB RSSI (Pins 25, 34 and 35) RSSI sensitivity At IF_IN1,2; pins 34 and 35 P min 20 dBµV RSSI compression At IF_IN1,2; pins 34 and 35 P max 100 dBµV RSSI dynamic range DR 80 dB RSSI resolution Slope of the RSSI has to be steady Acc ±2d B RSSI rise time P in = 30 to 100 dBµV, pin 25 t r 1µ s RSSI fall time P in = 100 to 30 dBµV, pin 25 t f 1µ s Quiescent output voltage At Pin < 20 dBµV at IF_IN1, IF_IN2, pin 25 Vout 0.4 V Maximum output voltage At Pin = 100 dBµV at IF_IN1, IF_IN2, pin 25 Vout 1.9 V FM Demodulator, BB-filter (Pins 19, 20, 23 and 24) Co-channel rejection ratio at P in = –75 dBm at IR-mixer input CCRR 10 dB Sensitivity Quality factor of external tank circuit approximately 20, fres = FIF/2, pin 24 S0 . 5 V / M H z Amplitude of recovered signal Nominal deviation of signal ±400 kHz, pin 24 A 450 mVpp Corner frequency Pin 23: C = 68 pF f c 680 kHz Output voltage DC range Pin 24 V outDC 1V S – 1 V DEMOD_DAC range (see bus protocol E6 to E10) ∆fIFcenter ±5% VCOs Frequency range VCO 1, D12 VS = 1 VCO 2, D12 VS = 0 fvco fvco 2289 2289 2483 2483 MHz MHz Tuning gain G tune 200 MHz/V Frequency control voltage range Pin 17 V tune 0.4 2.8 V
4572I–DECT–07/05 T2803 PLL Scaling factor prescaler S PSC 32/33 Scaling factor main counter S MC 82-89 Scaling factor swallow counter S SC 03 1 External reference input frequency AC coupled sinewave, pin 4 f REF_CLK 10.368 13.824 MHz MHz External reference input voltage AC coupled sinewave, pin 4 V REF_CLK 50 250 mV RMS Scaling factor reference counter S RC 6/8 Charge Pump (Pin 13) Output current V CP = VVS_CP/2, I_CPSW = 1, pin 48 I CP_nom ±7.5 mA Output current V CP = VVS_CP/2, I_CPSW = 0, pin 48 I CP_nom ±1.2 mA Current scaling ICP = ICP_nom + CPCS × ICP_step (see bus protocol D1 ... D2) ICP_step 0.2 mA Leakage current OLE = 1 I L ±100 pA Gaussian Transmit Filter (Gaussian Shape B × T = 0.5) Tx data rate 1152 kBit/s Tx data filter clock 6 taps in filter f TXFCLK 6.912 MHz Frequency deviation GF FM_nom ±400 kHz Frequency deviation scaling GFFM = GFFM_nom × GFCS (see bus protocol D7 ... D9) GFCS 60 130 % TX Driver (Pin 32) Maximum output power At L = 5.6 nH, pin 32 (see bus protocol E11-E12) P TX 3d B m Minimum output power At L = 5.6 nH, pin 32 (see bus protocol E11-E12) PTX –21 dBm RF leakage In RX mode P leak –47 dBm Output impedance At L = 5.6 nH, 2.5 GHz, pin 32 Z OUT 13+j40 Ω Ramp Generator (Pins 36 and 37) Minimum output voltage V min 0.7 V Maximum output voltage (see bus protocol E6-E10) V max 1.1 1.8 V Rise time C ramp = 270 pF at pin 37 t r 5µ s Fall time C ramp = 270 pF at pin 37 t f 5µ s Lock Detect and Test Mode Output (Pin 5) Lock detect output, test mode output Locked = 1, unlocked = 0 Test modes (see bus protocol E0 ... E2) LD Leakage current V OH = 4.6V I L 5µ A Saturation voltage I OL = 0.5 mA V SL 0.4 V Auxiliary Regulator (Pins 8, 9 and 10) Output voltage V SREG = 3V, pin 8 V REG 2.9 3.0 3.1 V VCO Regulator (Pins 14, 15 and 12) Output voltage V SVCO = 3V, pin 15 V REG_VCO 2.6 2.7 2.8 V 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit
4572I–DECT–07/05 T2803 3-wire Bus Clock fClock 6.912 MHz Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, OLE, TX_DATA, DATA_HOLD) (Pins 1, 2, 3, 38, 39, 44, 47 and 48) High input level = 1 V iH 1.5 V Low input level = 0 V iL 0.5 V High input current = 1 I iH –5 5 µA Low input current = 0 I iL –5 5 µA Standby Control (Pins 6, 45 and 46) Power Up PU_REG = 1 PU_RX/TX = 1 PU_PLL = 1 High input level Pin 6 Pin 45 Pin 46 VPU_REG VPU_RX/TX VPU_PLL 2.0 V Standby PU_REG = 0 PU_RX/TX = 0 PU_PLL = 0 Low input level Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF 0.7 V Power Up PU_REG = 1 PU_RX/TX = 1 PU_PLL = 1 High input current VPU = 3V, pin 6 VPU = 4.6V, pin 45 VPU = 3V, pin 46 VPU = 4.6V IPU_REG IPU_RX/TX IPU_PLL 100 200 125 300 100 150 400 µA µA µA µA Standby PU_xxxx = 0 Low input current VPU = 0V, pin 6 VPU = 0.5V, pins 45, 46 IPU,OFF 0.1 µA µA Settling Time VS = 0 → active operation Switched from VS = 0 to VS = 3V t soa < 10 µs Settling Time standby → active operation Switched from PU = 0 to PU = 1 t ssa < 10 µs Settling Time active operation → standby Switched from PU = 1 to standby t sas < 2 µs Power Supply (Pins 7, 10, 12, 14, 33 and 42) Total supply current RX I S 85 mA RSSI only I S 82 mA TX I S 54 mA TX (GF active) I S 56 mA Standby current PU_RX/TX = GND I S 10 µA Supply current CP VVS_CP = 3V, PLL in lock condition, Pin 13 ICP 1µ A 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit
4572I–DECT–07/05 T2803 Figure 12-1. Typical Application Circuit VCC BB_OUT RSSI
48 I_CPSW
47 TX_DATA
46 PU_PLL
45 PU_RX/TX
44 OLE
43 GND_PLL
42 VS_MIXER
41 MIXER_OUT2
40 MIXER_OUT1
39 TX_ON
38 RX_ON
37 RAMP_SET
VS_VCO 14 VREG_VCO 15 GND_VCO 16 VTUNE 17 GND1 18 DEMOD_TANK1 19 DEMOD_TANK2 20 DAC_DEC 21 REG_DEC 22 BB_CF 23 BB_OUT 24
12 VS_CP
11 GND_CP
10 VS_REG
9 REG_CTRL
8 VREG
7 VS_PLL
6 PU_REG
4 REF_CLOCK
3 ENABLE
2 DATA
1 CLOCK
IF_TANK1 26 IF_TANK2 27 GND2 28 RF_IN1 29 RF_IN2 30 GND3 31 TX_OUT 32 VS_IF 33 IF_IN1 34 IF_IN2 35 RAM P_OUT 36 OLE PU_RX/TX PU_PLL TX_DATA I_CPSW TX_ON RX_ON LD PU_REG CLOCK DATA ENABLE REF_CLK BC808 or similar 56 pF 220 pF 27 pF 27 pF 150 nH 47 pF 47 pF 180 nH 56 pF 470 nF 180 Ω 150 nF 22 nF 68 pF 2.2 nF 100 pF TBD TBD 18 pF 100 nH TX_OUT RF_IN SAW Filter TFS 112B tantal tantal 4.7 nF RAMP_OUT 68 pF T2803
4572I–DECT–07/05 T2803 14. Package Information 13. Ordering Information Extended Type Number Package Remarks MOQ T2803-PLQ QFN48 Taped and reeled 4000 pcs. T2803-PLQW QFN48, Pb-free, halogen-free Taped and reeled 4000 pcs.
Printed on recycled paper. 4572I–DECT–07/05 © Atmel Corporation 2005 . All rights reserved. Atmel ®, logo and combinations thereof, Everywhere Y ou Are ® and others, are registered trade- marks or trademarks of Atmel Corporation or its subsidiari es. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTOR Y WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU LAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR I NCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF AT MEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained her ein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza
77 Mody Road Tsimshatsui
Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Memory San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Microcontrollers San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602
44306 Nantes Cedex 3, France
13106 Rousset Cedex, France
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535
74025 Heilbronn, Germany
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123
38521 Saint-Egreve Cedex, France
www.atmel.com/literature