T2802 ATMEL | Alldatasheet
Document overview
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Technical content
Features
Fully Integrated TX/RX with VCO Fast Settling Synthesizer Unlimited Multi-slot Operation with Advanced Closed-loop Modulation No Mechanical Tuning Required Low Current Consumption Auxiliary Voltage Regulator On-chip (3.2 V to 4.6 V) Supply-voltage Range 3 V to 4.6 V (Regulated) Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power Amplifier (T7024 and T7026) Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz/20.736 MHz/27.648 MHz) TX Preamplifier with 3 dBm Output Power at 2.45 GHz Few Low-cost External Components Electrostatic sensitive device. Observe precautions for handling.
Description
The T2802 is an RF IC for low-power applications in the 2.45 GHz ISM band. The QFN48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closed-loop modulation concept. No mechanical tuning is necessary in production. Figure 1. Block Diagram
2.4 GHz
2 T2802
Table 1. Functional Block Description Figure 2. Pinning QFN48
4509F–DECT–10/03 Pin Description Pin Symbol Function Configuration CLOCK DATA ENABLE 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input
4 REF_CLK Reference-frequency input
5 LD Lock-detect output
6 PU_REG Power-up input for auxiliary voltage regulator
1,2,3 5k 5k VS_PLL GND_PLL VS_PLL REF_CLK 10k GND_PLL 10k GND_PLL 100 LD PU_REG 6 25k 25k GND_PLL
4 T2802
4509F–DECT–10/03
7 VS_PLL PLL supply voltage
REG_CTRL VS_REG Auxiliary voltage-regulator output Auxiliary voltage-regulator control output Auxiliary voltage-regulator supply voltage GND_CP VS_CP CP Charge-pump ground Charge-pump supply voltage Charge-pump output Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL VREG REG_CTRL VS_REG GND_PLL VS_PLL VS_CP CP GND_CP VS_PLL GND_PLL
4509F–DECT–10/03 VS_VCO VREG_VCO GND_VCO VCO voltage-regulator supply voltage VCO voltage-regulator control output VCO ground
17 VTUNE VCO tuning voltage input
18 GND1 Ground
Pin Description (Continued) Pin Symbol Function Configuration VS_VCO GND_VCO VREG_VCO VS_PLL GND_PLL VTUNE GND_VCO VREG_VCO VS_PLL GND_PLL GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
6 T2802
4509F–DECT–10/03 DEMOD_TANK1 DEMOD_TANK2 Demodulator tank circuit Demodulator tank circuit
21 DAC_DEC Decoupling PIN for VCO_DAC
22 REG_DEC Decoupling PIN for VCO_REG
Pin Description (Continued) Pin Symbol Function Configuration DEMOD TANK1 10k 10k DEMOD TANK2 VS_MIXER GND1 VS_IF GND2 DAC_DEC 10k GND_VCO 400 VREG_VCO VS_PLL GND_PLL REG_DEC 42k VREG_VCO GND_VCO VS_IF GND2
4509F–DECT–10/03
23 BB_CF Baseband filter corner-frequency control input
24 BB_OUT Baseband filter output
25 RSSI Received signal strength indicator output
IF_TANK1 IF_TANK2 IF tank circuit IF tank circuit Pin Description (Continued) Pin Symbol Function Configuration BB_CF VS_IF GND1 GND2 VS_IF GND1 BB_OUT GND2 VS_IF RSSI 13k GND2 IF_TANK1 VS_IF GND2
8 T2802
4509F–DECT–10/03
28 GND2 Ground
RF_IN1 RF_IN2 RF input of image reject mixer RF input of image reject mixer
31 GND3 Ground
Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL RF_IN1 GND2 VS_MIXER RF_IN2 GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
4509F–DECT–10/03
32 TX_OUT TX driver amplifier output for PA
33 VS_IF IF amplifier supply voltage
IF_IN1 IF_IN2 IF input of IF amplifier IF input of IF amplifier
36 RAMP_OUT Ramp-generator output for PA power ramping
Pin Description (Continued) Pin Symbol Function Configuration TX_OUT GND3 GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL IF_IN1 IF_IN2 90k VS_IF GND2 VS_MIXER GND2 RAMP_OUT VS_IF
10 T2802
4509F–DECT–10/03
37 RAMP_SET Slew-rate setting of ramping signal
RX_ON TX_ON RX control input TX control input MIXER_OUT1 MIXER_OUT2 Mixer output to SAW filter Mixer output to SAW filter Pin Description (Continued) Pin Symbol Function Configuration 100 RAMP SET VS_MIXER GND2 VS_IF RX_ON TX_ON 38, 39 5k 5k VS_IF GND1 GND2 270 270 MIXER_OUT2 MIXER_OUT1 GND2 VS_MIXER VS_IF
4509F–DECT–10/03 VS_MIXER GND_PLL Mixer supply voltage PLL ground
44 PU_VCO VCO power-up input
45 PU_RX/TX RX/TX power-up input
Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL PU_VCO 5k 5k VS_VCO GND_VCO GND_PLL PU_RX/TX GND1 25k 25k GND_PLL
12 T2802
4509F–DECT–10/03
46 PU_PLL PLL power-up input
47 TX_DATA TX data input of Gaussian filter and modulation-
48 I_CPSW Charge-pump current control input
Pin Description (Continued) Pin Symbol Function Configuration PU PLL 25k 25k 10k 10k 140k GND PLL 10k 20k TX_DATA 47 2.5k VS_PLL GND_PLL I_CPSW 48 5k VS_PLL GND_PLL
4509F–DECT–10/03 Functional Description Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f=f IF/2 (/g18755 MHz) and finally to an integrated baseband filter BB. For demodulator tunning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the on-chip varicap diode. Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typically +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. Synthesizer The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). A 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (f PD =3 . 4 5 6M H z ) . Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC. Power Supply An integrated bandgap-stabilized voltage regulat or for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided.
14 T2802
Figure 3. PLL Principle
13.824 MHz 4
20.736 MHz 6
27.648 MHz 8
1.152 Mbit/s
310.368 MHz
DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 1. LO Frequencies Table 2. Control Signals — Functions
16 T2802
Table 3. Control Signals — Modes The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). condition. In this case the power-down current is below 100 µA. the channel. Dataword 2 holds setup information, which is adjusted during production.
4509F–DECT–10/03 Data Word 1 D11 = x: do not care Data Word 2 Data Word 1 Programs PLL Settings MSB LSB Data bits Address bit D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 RC SC MC VS X MCC GFCS VCODAC CPCS GF E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 A0 PA DEMODDAC/RAMPDAC MCCS TEST 0 With the Reference Counter bits D21 - D22 RC (Reference Counter) D22 D21 S RC REF_CLK 0 0 3 10.368 MHz 0 1 4 13.824 MHz 1 0 6 20.736 MHz 1 1 8 27.648 MHz With the Main Counter bits D13 - D15 MC (Main Counter) D15 D14 D13 S MC 00 0 4 0 00 1 4 1 11 0 4 6 11 1 4 7 With the Swallow Counter bits D16 - D20 SC (Swallow Counter) D20 D19 D18 D17 D16 S SC 000000 000011 000102 11101 2 9 11110 3 0 11111 3 1
18 T2802
4509F–DECT–10/03 VCO Selection Gaussian Filter On/Off Modulation Compensation Circuit On/Off GFCS Adjustment With bit D12 VCO Selection D12 VCO Mode
0 RX-VCO
1 TX-VCO
GF is used only in TX mode. D0 GF (Gaussian Filter) 0O F F 1O N With bit D10 MCC is used only in TX mode. D10 MCC (Modulation Compensation Circuit) 0O F F 1O N With bits D7 - D9 Only in TX mode effective for setting the frequency deviation of the modulation. GFCS (Gaussian Filter Settings) D9 D8 D7 GFCS 00 0 6 0 % 00 1 7 0 % 01 0 8 0 % 01 1 9 0 % 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130%
4509F–DECT–10/03 VCO_DAC Adjustment CPCS Adjustment Data Word 2 Programs DEMODDAC Adjustment With bits D3 - D6 Used to pretune the VCO frequency in case of production tolerances of the device. Pretune DAC Voltage D6 D5 D4 D3 f VCO/% 00 0 0 - 5 00 0 1 . . . 00 1 0 . . . 11 0 1 . . . 11 1 0 . . . 11 1 1 5 With bits D1 - D2 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. CPCS (Charge-pump Current Settings) D2 D1 CPCS 00 - 1 010 101 112 With bits E6 - E10 Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of external components and the T2802. Demod DAC Voltage E 1 0 E 9E 8E 7E 6 f IFcenter % 00000 - 5 00001 . . . 00010 . . . 11101 . . . 11110 . . . 11111 5
20 T2802
4509F–DECT–10/03 RAMPDAC Adjustment for TX Mode MCCS Adjustment TEST Mode Settings With bits E6 - E10 Only in TX mode effective. Used to control the power of the external PA by adjusting the ramping voltage. RAMPDAC Voltage (at Pin 36 RAMP_OUT) E 1 0 E 9E 8E 7E 6 V RAMP_OUT 00000 1 . 1 V 00001 . . . 00010 . . . 10111 1 . 6 8 V 11000 1 . 7 V 11110 . . . 11111 1 . 7 V With bits E3 - E5 Only in TX mode effective. Adjusts the modulation compensation circuit for closed-loop modulation. This adjustment is done with a test sequence of a long stream of ,1‘ - ,0‘. The correct setting is achieved if the modulation is not affected by the PLL. MCCS (Modulation Compensation Settings) E5 E4 E3 MCCS 0006 0 % 0017 0 % 0108 0 % 0119 0 % 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% With bits E0 - E2 In normal operation Lock detect output is used. All other settings are for test only. E2 E1 E0 Signal at Lock Detect Output CP Mode 0 0 0 Lock detect Active 0 0 1 PC out/2 Active 0 1 0 RC out/2 Active 0 1 1 MCCTEST: RC out divided by 512 Active 1 0 0 Lock detect High imp. 1 0 1 PC out/2 High imp. 1 1 0 RC out/2 High imp. 111 G F T E S T : R C o u t H i g h i m p .
22 T2802
4509F–DECT–10/03 Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Pin Symbol Min. Max. Unit Supply voltage regulator 10 V S_REG 3.2 4.7 V Supply voltage 7, 12, 14, 33, 42 V S 3.0 4.7 V Logic input voltage 1, 2, 3, 38, 39, 44-48 VIN -0.3 V S V Junction temperature T jmax 150 /g176C Storage temperature T stg -40 150 /g176C Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 25 K/W Operating Range Parameters Pin Symbol Min. Typ. Max. Unit Supply voltage regulator 10 V S_REG 3.2 3.6 4.6 V Supply voltage 7, 14, 33, 42 V S 2.9 3.0 4.6 V Supply voltage charge pump 12 V SCP VS 4.6 V Ambient temperature T amb -25 +85 /g176C
4509F–DECT–10/03
Electrical Characteristics
Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25/g176C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit IR Mixer (Pins 29, 30, 40 and 41) Input impedance Single ended, pins 29 or 30 Z in 110 + j12 /g87 Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Single ended, pins 29 or 30 NFDSB= NFSSB 10 dB Conversion gain R load = 200 /g87 Gconv 11 dB Input intercept point Single ended, pins 29 or 30 IIP3 -7 dBm Output impedance Differential, pins 40 and 41 Z out 175 + j145 /g87 IF Amplifier (Pins 26, 27, 34 and 35) Input impedance Differential, pins 34 and 35 Z in 1200 - j480 /g87 Lower cut-off frequency fl 3dB 90 MHz Upper cut-off frequency fu 3dB 130 MHz Power gain Gp 85 dB Bandwidth of external tank circuit Pins 26 and 27 BW3dB 10 MHz Noise figure NF 9 dB RSSI (Pins 25, 34 and 35) RSSI sensitivity At IF_IN1,2; pins 34 and 35 P min 20 dBµV RSSI compression At IF_IN1,2; pins 34 and 35 P max 100 dBµV RSSI dynamic range DR 80 dB RSSI resolution Slope of the RSSI has to be steady Acc /g1772d B RSSI rise time P in = 30 to 100 dBµV, pin 25 t r 1µ s RSSI fall time P in = 100 to 30 dBµV, pin 25 t f 1µ s Quiescent output voltage At Pin < 20 dBµV at IF_IN1, IF_IN2, Pin 25 Iout 0.4 V Maximum output voltage At Pin = 100 dBµV at IF_IN1, IF_IN2, Pin 25 Iout 1.9 V FM Demodulator, BB-filter (Pins 19, 20, 23 and 24) Co-channel rejection ratio At P in = -75 dBm at IR-mixer input CCRR 10 dB Sensitivity Quality factor of external tank circuit approximately 20, fres =F IF/2, pin 24 S0 . 5 V / M H z Amplitude of recovered signal Nominal deviation of signal /g1772 8 8k H z , p i n2 4 A 450 mVpp Corner frequency Pin 23: C = 68 pF f c 680 kHz Output voltage DC range Pin 24 V outDC 1V S - 1 V DEMOD_DAC range See bus protocol E6 to E10 /g68fIFcenter ±5 %
24 T2802
4509F–DECT–10/03 VCOs Frequency range TX-VCO, D12 (VS) = 1 RX-VCO, D12 (VS) = 0 fvco fvco 2400 2289 2500 2389 MHz MHz Tuning gain G tune 70 MHz/V Frequency control voltage range Pin 17 V tune 0.4 2.8 V VCO_DAC range See bus protocol D3 ... D6 /g68fvco,DAC /g1775% PLL Scaling factor prescaler S PSC 32/33 Scaling factor main counter S MC 40 - 47 Scaling factor swallow counter S SC 03 1 External reference input frequency AC coupled sinewave, pin 4 f REF_CLK 10.368 13.824 20.736 27.648 MHz MHz MHz MHz External reference input voltage AC coupled sinewave, pin 4 V REF_CLK 50 250 mV RMS Scaling factor reference counter S RC 3/4/6/8 Charge Pump (Pin 13) Output current VCP = VVS_CP /2, I_CPSW = ‘1’, Pin 48 ICP_nom 7.5 mA Output current VCP = VVS_CP /2, I_CPSW = ‘0’, Pin 48 ICP_nom 1.2 mA Current scaling ICP = ICP_nom + CPCS /g180 ICP_step (see bus protocol D1 ... D2) ICP_step 0.2 mA Leakage current I L /g177100 pA Gaussian Transmit Filter (Gaussian Shape B /g180/g32T = 0.5) Tx data filter clock 6 taps in filter f TXFCLK 6.912 MHz Frequency deviation GF FM_nom /g177400 kHz Frequency deviation scaling GFFM = GFFM_nom /g180 GFCS (see bus protocol D7 ... D9) GFCS 60 130 % Modulation Compensation Circuit Oversampling OVS 6 Digital sum variation DSV 85 Current scaling factor See bus protocol E3 ... E5 MCCS 60 130 % TX Driver (Pin 32) Maximum output power At L = 5.6 nH, pin 32 (see bus protocol E11 - E12) P TX 3d B m Minimum output power At L = 5.6 nH, pin 32 (see bus protocol E11 - E12) PTX -21 dBm Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25/g176C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit
4509F–DECT–10/03 RF leakage In RX mode P leak -47 dBm Output impedance At L = 5.6 nH, 2.5 GHz, pin 32 Z OUT 13 + j40 /g87 Ramp Generator (Pins 36 and 37) Minimum output voltage Pin 36 and 37 V min 0.7 V Maximum output voltage See bus protocol E6 - E10 V max 1.1 1.8 V Rise time C ramp = 270 pF at pin 37 t r 5µ s Fall time C ramp = 270 pF at pin 37 t f 5µ s Lock Detect and Test Mode Output (Pin 5) Lock detect output, test mode output locked = ‘1’, unlocked = ‘0’ test modes (see bus protocol E0 ... E2) LD Leakage current V OH = 4.6 V I L 5µ A Saturation voltage I OL = 0.5 mA V SL 0.4 V Auxiliary Regulator (Pins 8, 9 and 10) Output voltage V SREG = 3 V, pin 8 V REG 2.9 3.0 3.1 V Supply voltage rejection VPin10 = VDC + 0.1 Vpp fPin10 = 0.1 to 10 kHz CPin8 = 100 nF SVR TBD dB VCO Regulator (Pins 14, 15 and 12) Output voltage V SVCO = 3 V, pin 15 V REG_VCO 2.6 2.7 2.8 V 3-wire Bus Clock fClock 6.912 MHz Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, DATA_HOLD) (Pins 1, 2, 3, 38, 39, 44, 47 and 48) High input level = ‘1’ V iH 1.5 V Low input level = ‘0’ V iL 0.5 V High input current = ‘1’ I iH -5 5 µA Low input current = ‘0’ I iL -5 5 µA Standby Control (Pins 6, 45 and 46) Power Up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input level Pin 6 Pin 45 Pin 46 V PU_REG VPU_RX/TX VPU_PLL 2.0 V Standby PU_REG = ‘0‘ PU_RX/TX = ‘0‘ PU_PLL = ‘0‘ Low input level Pin 6 Pin 45 Pin 46 V PU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF 0.7 V Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25/g176C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit
26 T2802
4509F–DECT–10/03 Power Up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input current VPU = 3 V, pin 6 VPU = 4.6 V , pin 45 VPU = 3 V, pin 46 VPU = 4.6 V IPU_REG IPU_RX/TX IPU_PLL 100 200 125 300 100 150 400 µA µA µA µA Standby PU_xxxx = ‘0’ Low input current VPU = 0 V, pin 6 VPU = 0.5 V , pins 45, 46 IPU,OFF 0.1 µA µA Settling Time VS = 0 /g174 active operation Switched from VS = 0 to VS = 3V t soa < 10 µs Settling Time standby /g174 active operation Switched from PU = ‘0’ to PU = ‘1’ t ssa < 10 µs Settling Time active operation /g174 standby Switched from PU = ‘1’ to standby t sas < 2 µs Power Supply (Pins 7, 10, 12, 14, 33 and 42) Total supply current RX I S 85 mA RSSI only I S 82 mA TX I S 54 mA TX (MCC, GF active) I S 58 mA Standby current PU_RX/TX = GND I S 10 µA Supply current CP VVS_CP = 3 V, PLL in lock condition, Pin 13 ICP 1µ A Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25/g176C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit
Figure 6. Typical Application Circuit
48 I_CPSW
47 TX_DATA
46 PU_PLL
45 PU_RX/TX
44 PU_VCO
43 GND_PLL
42 VS_MIXER
41 MIXER_OUT2
40 MIXER_OUT1
39 TX_ON
38 RX_ON
37 RAMP_SET
12 VS_CP
11 GND_CP
10 VS_REG
9 REG_CTRL
8 VREG
7 VS_PLL
6 PU_REG
4 REF_CLOCK
3 ENABLE
2 DATA
1 CLOCK
28 T2802
4509F–DECT–10/03
Package Information
Ordering Information
Extended Type Number Package Remarks T2802-PLQ QFN48 Taped and reeled
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