T2801_06 ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Supply Voltage Range 3V to 4.6V (Unregulated) Auxiliary Voltage Regulator On-chip Low Current Consumption Few Low Cost External Components No Mechanical Tuning Required Non-blindslot and Blindslot Operation Unlimited Multislot Operation with Advanced Closed-loop Modulation Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz/20.736 MHz) TX Preamplifier with 0 dBm Output Power at 1.9 GHz and Ramp-signal Generator for SiGe Power Amplifier 1. Description The T2801 is an RF IC for low-power DECT applications. The QFN48 packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closed-loop modulation concept. No me chanical tuning is neces- sary in production. Figure 1-1. Block Diagram TANK PC RC GF MCC CP VCO f : n f : n CTRL LOGIC PD TX / RX SWITCH IR MIXER IF AMP 1 IF AMP 2 DEMOD BB FILTER 3-WIRE BUS DEMOD DAC RSSI TX DRIVER CLOCK DATA ENABLE RX_ON TX_ON PU_RX/TX PU_PLL TX_DATA RSSI BB_OUT CF DEMOD IF_TANKIF_IN MIXER OUT RF_IN TX_OUT VS_VCO CP LD REF_CLK VTUNEVREG VS_REG REG_CTRL VREG_VCO VCO REG RAMP GEN RAMP_OUT RAMP_SET AUX REG PU_VCO PU_REGGND_VCO D/A I_CPSW DECT Single-chip Transceiver T2801 Rev. 4567B–DECT–03/06
4567B–DECT–03/06 T2801 Table 1-1. Functional Block Description Name Description AUX REG Auxiliary voltage regulator BBF Baseband filter CP Charge pump DAC D/A converter for demodulator tuning DEMOD Demodulator GF Gaussian filter for transmit data IF AMP1 1st intermediate frequency amplifier IF AMP2 2nd intermediate frequency amplifier IR MIXER Image rejection mixer MCC Modulation compensation circuit PC Programmable counter PD Phase detector RAMP GEN Ramp-signal generator RC Reference counter RSSI Received signal-strength indicator TX DRIVER Buffer amplifier for TX_OUT TX/RX SWITCH Switches VCO signal to IR mixer resp. TX driver VCO Voltage-controlled oscillator VCO REG Voltage regulator for VCO
4567B–DECT–03/06 T2801 2. Pin Configuration Figure 2-1. Pinning QFN48 CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 T2801 RX_ON TX_ON M IXER_OUT1 PU_VCO TX_DATA VS_M IXER GND_PLL PU_RX/TX PU_PULL I_CPSW RAM P_SET M IXER_OUT2 CP GND_VCO VS_VCO GND1 VTUNE VREG_VCO BB_OUT DAC_DEC BB_CF REG_DEC DEM OD_TANK2 DEM OD_TANK1
4567B–DECT–03/06 T2801 Table 2-1. Pin Description Pin Symbol Function Configuration CLOCK DATA ENABLE 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input
4 REF_CLK Reference-frequency input
5 LD Lock-detect output
6 PU_REG Power-up input for auxiliary voltage
1,2,3 5k 5k VS_PLL GND_PLL VS_PLL REF_CLK 10k GND_PLL 10k GND_PLL 100 LD PU_REG 25k 25k GND_PLL
4567B–DECT–03/06 T2801
7 VS_PLL PLL supply voltage
REG_CTRL VS_REG Auxiliary voltage-regulator output Auxiliary voltage-regulator control output Auxiliary voltage-regulator supply voltage GND_CP VS_CP CP Charge-pump ground Charge-pump supply voltage Charge-pump output Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL VREG REG_CTRL VS_REG GND_PLL VS_PLL VS_CP CP GND_CP VS_PLL GND_PLL
4567B–DECT–03/06 T2801 VS_VCO VREG_VCO GND_VCO VCO voltage-regulator supply voltage VCO voltage-regulator control output VCO ground
17 VTUNE VCO tuning voltage input
18 GND1 Ground
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration VS_VCO GND_VCO VREG_VCO VS_PLL GND_PLL VTUNE GND_VCO VREG_VCO VS_PLL GND_PLL GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
4567B–DECT–03/06 T2801 DEMOD_TANK1 DEMOD_TANK2 Demodulator tank circuit Demodulator tank circuit
21 DAC_DEC Decoupling pin for VCO_DAC
22 REG_DEC Decoupling pin for VCO_REG
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration DEMOD TANK1 10k 10k DEMOD TANK2 VS_MIXER GND1 VS_IF GND2 DAC_DEC 10k GND_VCO 400 VREG_VCO VS_PLL GND_PLL REG_DEC 42k VREG_VCO GND_VCO VS_IF GND2
4567B–DECT–03/06 T2801
23 BB_CF Baseband filter corner-frequency control
24 BB_OUT Baseband filter output
25 RSSI Received signal-strength indicator output
IF_TANK1 IF_TANK2 IF tank circuit IF tank circuit Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration BB_CF VS_IF GND1 GND2 VS_IF GND1 BB_OUT GND2 VS_IF RSSI 13k GND2 VS_IF RSSI 13k GND2
4567B–DECT–03/06 T2801
28 GND2 Ground
RF_IN1 RF_IN2 RF input of image reject mixer RF input of image reject mixer
31 GND3 Ground
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL RF_IN1 GND2 VS_MIXER RF_IN2 GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
4567B–DECT–03/06 T2801
32 TX_OUT TX driver amplifier output for PA
33 VS_IF IF amplifier supply voltage
IF_IN1 IF_IN2 IF input of IF amplifier IF input of IF amplifier
36 RAMP_OUT Ramp-generator output for PA power
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration TX_OUT GND3 GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL IF_IN1 IF_IN2 4.3k VS_IF GND2 VS_MIXER GND2 RAMP_OUT VS_IF
4567B–DECT–03/06 T2801
37 RAMP_SET Slew-rate setting of ramping signal
RX_ON TX_ON RX control input TX control input MIXER_OUT1 MIXER_OUT2 Mixer output to SAW filter Mixer output to SAW filter Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration 100 RAMP SET VS_MIXER GND2 VS_IF RX_ON TX_ON 38, 39 5k 5k VS_IF GND1 GND2 270 270 MIXER_ OUT2 MIXER_ OUT1 GND2 VS_MIXER 42VS_IF
4567B–DECT–03/06 T2801 VS_MIXER GND_PLL Mixer supply voltage PLL ground
44 PU_VCO VCO power-up input
45 PU_RX/TX RX/TX power-up input
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL PU_VCO 44 5k 5k VS_VCO GND_VCO GND_PLL PU_RX/TX GND1 25k 25k GND_PLL
4567B–DECT–03/06 T2801
46 PU_PLL PLL power-up input
47 TX_DATA TX data input of Gaussian filter and
modulation-compensation circuit
48 I_CPSW Charge pump switch input controls charge
Table 2-1. Pin Description (Continued) Pin Symbol Function Configuration PU_RX/TX GND1 25k 25k GND_PLL TX_DATA 5k 5k VS_PLL GND_PLL I_CPSW VS_PLL GND_PLL
4567B–DECT–03/06 T2801 3. Functional Description
3.1 Receiver
The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = f IF/2 ([55 MHz) and finally to an inte- grated baseband filter BB. For demodulator tuning in production, an integrated 5-bit Digital-to-Analog (D/A) converter is provided to control the on-chip varicap diode.
3.2 Transmitter
The transmit data at TX_DATA is filtered by an integrated Gaussian Filter (GF) and fed to the fully integrated VCO operating at twice the output frequency. After modulation, the signal is fre- quency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typical +3 dBm out put power at TX_OUT. An integrated ramp-signal generator, RAMP_GEN, provides a ramp signal at RAMP_OUT for the external power amplifier. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin.
3.3 Synthesizer
The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully inte- grated VCO (including on-chip inductors and varact ors). An 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequency-divided to supply the desired fre- quency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (f PD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop m odulation concept based on the modulation com- pensation circuit MCC.
3.4 Power Supply
An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP tran- sistor is implemented. Multiple power-down and current saving modes are provided.
4567B–DECT–03/06 T2801 Figure 3-1. PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO Phase frequency Divider by 2 PA driver detector PD VCO Mixer VCO DAC fPD = 3.456 MHz GF_DATA Controlled phase shifting Modulation Gaussian compensation MCC filter GF Reference counter RC 6.912 MHz REF_CLK SMC 13.824MHz 4 20.736MHz 6
1.152 Mbit/s
PLL reference TX_DATA Frequency REF_CLK Baseband controller 310.368MHz ext. loop filter Charge pump
4567B–DECT–03/06 T2801 Table 3-1 shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Formula: TX: fANT = fVCO = 1.728 MHz x (32 x SMC + SSC) RX: fANT = 1.728 MHz x (32 x SMC + SSC) + fIF Table 3-1. LO Frequencies Mode f IF/MHz Channel f ANT/MHz f VCO/MHz S MC SSC TX C9 1881.792 1881.792 34 1 TX C8 1883.520 1883.520 34 2 TX C1 1895.616 1895.616 34 9 TX C0 1897.344 1897.344 34 10 TX C10 1899.072 1899.072 34 11 TX C11 1900.800 1900.800 34 12 TX C29 1931.904 1931.904 34 30 TX C30 1933.632 1933.632 34 31 RX 110.592 C9 1881.792 1771.200 32 1 RX 110.592 C8 1883.520 1772.928 32 2 RX 110.592 C1 1895.616 1785.024 32 9 RX 110.592 C0 1897.344 1786.752 32 10 RX 110.592 C10 1899.072 1788.480 32 11 RX 110.592 C11 1900.800 1790.208 32 12 RX 110.592 C29 1931.904 1821.312 32 30 RX 110.592 C30 1933.632 1823.040 32 31 RX 112.320 C9 1881.792 1769.472 32 0 RX 112.320 C8 1883.520 1771.200 32 1 RX 112.320 C1 1895.616 1783.296 32 8 RX 112.320 C0 1897.344 1785.024 32 9 RX 112.320 C10 1899.072 1786.752 32 10 RX 112.320 C11 1900.800 1788.480 32 11 RX 112.320 C29 1931.904 1819.584 32 29 RX 112.320 C30 1933.632 1821.312 32 30
4567B–DECT–03/06 T2801 4. Control Signals Table 4-1. Control Signals – Functions Signal Function I_CPSW Controls the charge pump current PU_REG Activates AUX voltage regulator supplying the complete transceiver PU_VCO Activates VCO voltage regulator which supplies only the VCO PU_RX/TX Activates RX/TX blocks PU_PLL Activates PLL circuits: PC, PD, CP , RC RX_ON Activates RX circuits: BBF , DEMOD, IF AMP , IR MIXER TX_ON Activates TX circuits: TX–DRIVER, RAMP GEN. Starts RAMP SIGNAL at RAMP OUT Data Word 1, Bit D10 Activates GF in TX mode Data Word 1, Bit D9 Activates MCC in TX mode Table 4-2. Control Signals – Modes Mode TX Mode RX Mode RSSI Only PU_REG 1 1 1 PU_VCO 1 1 1 PU_RX/TX 1 1 1 PU_PLL 1 1 1 RX_ON 0 1 1 TX_ON 1 0 1 BB filter OFF ON OFF Demodulator OFF ON OFF IF amplifiers and RSSI OFF ON ON IR mixer OFF ON ON RX switch OFF ON ON TX switch ON OFF OFF TX driver ON OFF OFF Ramp generator ON OFF OFF Programmable counter ON ON ON Voltage-controlled oscillator ON ON ON Gaussian filter ON OFF OFF Phase detector/charge pump ON ON ON Modulation compensation circuit ON OFF OFF Reference counter ON ON ON Typical current consumption/mA at V S = 3.2 V 54 85 80
4567B–DECT–03/06 T2801 5. Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. After enable returning to high condition, the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check made on how many pulses arrived during enable-low condition. During enable low condition, the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Data word 2 holds setup information, which is adjusted during production.
5.1 Data Word 1
5.2 Data Word 2
Data Bits Add. bit D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 RC SC MC VCOs 1 1 GF MCC GFCS VCODAC CPCS GF 1 E 1 0 E 9E 8E 7E 6E 5E 4E 3E 2E 1E 0A 0 DEMODDAC MCCS TEST 0
4567B–DECT–03/06 T2801 6. Data Word 1 Programs
6.1 PLL Settings
6.2 VCO Select (RX/TX VCO)
Note: Used to switch between RX/TX VCO Table 6-1. With the Reference Counter Bits D21-D22 RC (Referene Counter) D22 D21 S RC REF_CLK (MHz) 003 1 0 . 6 3 8 014 1 3 . 8 2 4 106 2 0 . 7 3 6 Table 6-2. With the Main Counter Bits D14-D15 MC (Main Counter) D15 D14 S RC 00 3 2 01 3 3 10 3 4 11 3 5 Table 6-3. With the Swallow Counter Bits D16-D20 SC (Swallow Counter) D20 D19 D18 D17 D16 S SC 000000 000011 000102 11101 2 9 11110 3 0 11111 3 1 Table 6-4. With bit D13 D13 VCOS (VCO Select)
0 RX-VCO
1 TX-VCO
4567B–DECT–03/06 T2801
6.3 Gaussian Filter On/Off
Note: GF is used only in TX mode
6.4 Modulation Compensation Circuit On/Off
Note: MCC is used only in TX mode
6.5 GFCS Adjustment
Note: Only in TXmode effective for setting the frequency deviation of the modulation Table 6-5. With bit D10 D10 GF (Gaussian Filter)
0 OFF
Table 6-6. With bit D9 D9 MCC (Modulation Compensation Circuit) Table 6-7. With bit D6 - D8 GFCS(Gaussian Filter Settings) D8 D7 D6 GFCS (%) 000 6 0 001 7 0 010 8 0 011 9 0 100 1 0 0 101 1 1 0 110 1 2 0 111 1 3 0
4567B–DECT–03/06 T2801
6.6 VCO_DAC Adjustment
Note: Used to pretune the VCO frequency in case of production tolerances of the device. Tuning voltage in locked condition should be around 1.8V at room temperature. This gives margin for ambient temperature changes
6.7 CPCS Adjustment
Note: Used to adjust the charge pump current. This can be used to compensate the change of the tun- ing sensitivity over frequency and device tolerances Table 6-8. With bit D3 - D5 Pretune DAYC Voltage D5 D4 D3 f VCO/% 000 - 5 001 . . . 010 . . . 011 . . . 100 . . . 101 . . . 110 . . . 1115 Table 6-9. With bit D0 - D2 CPCS (Charge-pump Current Settings) D2 D1 D0 CPCS 000 – 4 001 – 3 010 – 2 011 – 1 100 0 101 1 110 2 111 3
4567B–DECT–03/06 T2801 7. Data Word 2 Programs
7.1 DEMODDAC Adjustment
Note: Only in RX mode effective. Used to tune the demodulator center frequency and allows to compen- sate tolerances of extenal components and the T2801
7.2 MCCS Adjustment
Note: Only in TX mode effective. Adjusts the modu lation compensation circuit for closed loop modula- tion. This adjustment is done with a test sequence of a long stream of ,1' - ,0'. The correct setting is achieved, if the modulation is not affected by the PLL Table 7-1. With bits E6 - E10 Demod DAC Voltage E10 E9 E8 E7 E6 f IFcenter (%) 00000 – 5 00001 . . . 00010 . . . ... 11101 . . . 11110 . . . 11111 5 Table 7-2. With bits E3 - E5 MCCS (Modulation Compensation Settings) E5 E4 E3 MCCS (%) 00 0 6 0 00 1 7 0 01 0 8 0 01 1 9 0 1 0 0 100 1 0 1 110 1 1 0 120 1 1 1 130
4567B–DECT–03/06 T2801
7.3 TEST Mode Settings
Note: In normal operation Lock detect output is used. All other settings are for test only Figure 7-1. 3-wire Bus Protocol Timing Diagram Figure 7-2. TX DATA Timing Table 7-3. With bit E0 - E2 and D11 D11 E2 E1 E0 Signal at Lock Detect Output CP Mode
1000 L o c k d e t e c t A c t i v e
0001 R C o u t / 2 A c t i v e
1010 P C o u t / 2 A c t i v e
X 0 1 1 MCCTEST: RC out diviced by 512 Active 1100 L o c k d e t e c t H i g h i m p . 0101 R C o u t / 2 H i g h i m p . 1110 P C o u t / 2 H i g h i m p . X 1 1 1 GFTEST: RC out High imp. DATA CLOCK ENABLE TTTEC TS TC THTL TPER Table 7-4. 3-wire Bus Protocol Description Symbol Minimum Value Unit Clock period TPER 125 ns Set time data to clock TS 60 ns Hold time data to clock TH 60 ns Clock pulse width TC 60 ns Set time enable to clock TL 200 ns Hold time enable to data TEC 0 ns Time between two protocols TT 250 ns RefCLK TX_DATA TS TH Table 7-5. TX DATA Timing Values Parameters Symbol Value Remarks Set-up time TX DATA TS 10 ns TS and TH must be considered for both (falling and rising) edges of RefCLK when using REF_CLK = 10.368 MHz.Hold time TX DATA TH 10 ns
4567B–DECT–03/06 T2801 8. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Symbol Min. Max. Unit Supply voltage regulator, Pin 10 V S_REG 3.2 4.7 V Supply voltage, pins 7, 12, 14, 33 and 42 V S 3.0 4.7 V Logic input voltage, pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 VIN –0.3 V S V Junction temperature T jmax 150 °C Storage temperature T Stg –40 +150 °C 9. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thJA TBD K/W 10. Operating Range Parameters Symbol Min. Typ. Max. Unit Supply voltage regulator, Pins 10 V S_REG 3.2 3.6 4.6 V Supply voltage, pins 7, 12, 14, 33 and 42 V S 3.0 3.0 4.6 V Ambient temperature T amb –25 +85 °C
4567B–DECT–03/06 T2801 11. Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions /Pins Symbol Min. Typ. Max. Unit IR Mixer, Pins 29, 30, 40 and 41 Input impedance Pins 29 and 30 Z in 50 Ω Input matching Pins 29 and 30 VSWR in < 2:1 Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Pins 40 and 41 NFDSB = NFSSB 10 dB Conversion gain Rload = 200 Ω Gconv 11 dB Input interception point Pins 40 and 41 IIP3 –10 dBm IF Amplifier, Pins 26, 27, 34 and 35 Input impedance Pins 34 and 35 Z in 200 400 Ω Lower cut-off frequency fl 3dB 90 MHz Upper cut-off frequency fu 3dB 130 MHz Power gain Gp 85 dB Bandwidth of external tank circuit Pins 26 and 27 BW3dB 10 MHz Noise figure NF 9 dB RSSI, Pins 25, 34 and 35 RSSI sensitivity At IF_IN1, IF_IN2 Pins 34 and 35 P min 20 dBµV RSSI compression At IF_IN1, IF_IN2 Pins 34 and 35 Pmax 100 dBµV RSSI dynamic range DR 80 dB RSSI resolution Slope of the RSSI has to be steady Acc ±2 dB RSSI rise time P in = 30 to 100 dBµV, pin 25 t r 1µ s RSSI fall time P in = 100 to 30 dBµV, pin 25 t f 1µ s Quiescent output voltage At Pin < 20 dBµV at IF_IN1, IF_IN2, pin 25 Iout 0.45 µA Maximum output voltage At Pin = 100 dBµV at IF_IN1, IF_IN2, pin 25 Iout 2.25 µA FM Demodulator, BB-Filter Pins 19, 20, 23 and 24 Co-channel rejection ratio At Pin = –75 dBm at IR-mixer input CCRR 10 dB Sensitivity Quality factor of external tank circuit approximately 20, fres = FIF/2, Pin 24 S0 . 5 V / M H z Amplitude of recovered signal Nominal deviation of signal ± 288 kHz, Pin 24 A4 5 0 m V s s Corner frequency Pin 23: C = 68 pF f c 680 kHz Output voltage DC range Pin 24 V outDC 1V s – 1 V DAC for FM Demodulator (Internally Connected) DEMOD_DAC range (see bus protocol E6 ... E10) ∆f IFcenter ± 5%
4567B–DECT–03/06 T2801 VCO RX-VCO frequency range VCOS = ‘0’ Bit D13 f vco 1769 1824 MHz TX-VCO frequency range VCOS = ‘1’ Bit D13 f vco 1881 1934 MHz Tuning gain G tune 40 MHz/V Frequency control voltage range Pin 17 V tune 0.4 2.8 V VCO_DAC range (see bus protocol D3 ... D5) ∆fvco,DAC ±5 % PLL Scaling factor prescaler S PSC 32/33 Scaling factor main counter S MC 32/33/34/35 Scaling factor swallow counter S SC 03 1 External reference input frequency AC coupled sinewave, pin 4 f REF_CLK 10.368 13.824 20.736 MHz MHz MHz External reference input voltage AC coupled sinewave, pin 4 V REF_CLK 50 250 mV RMS Scaling factor reference counter S RC 3/4/6/8 Charge Pump, Pin 13 Output current VCP = VVS_CP / 2, I_CPSW = ‘1’, pin 48 ICP_nom ±6.5 mA Output current VCP = VVS_CP / 2, I_CPSW = ‘0’, pin 48 ICP_nom ±1.2 mA Current scaling ICP = ICP_nom + CPCS × ICP_step (see bus protocol D0 ... D2) ICP_step 0.2 mA Leakage current I L ±100 pA Gaussian Transmit Filter (Gaussian Shape B × T = 0.5) Tx data filter clock 12 taps in filter f TXFCLK 13.824 MHz Frequency deviation GF FM_nom ±350 kHz Frequency deviation scaling GFFM = GFFM_nom × GFCS (see bus protocol D6 ... D8) GFCS 60 130 % Modulation Compensation Circuit Oversampling OVS 6 Digital sum variation DSV 85 Current scaling factor (see bus protocol E3 ... E5) MCCS 60 130 % VCO Switch and TX Driver, Pin 32 Power gain At P in = –40 dBm Gp 30 dB Output impedance Pin 32 Z out 100 Ω Maximum output power Pin 32 P max 03 d B m Gain compression At TX_RF_OUT, Pin 32 P 1dB 1d B m Output interception point Pin 32 OIP3 10 dBm 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions /Pins Symbol Min. Typ. Max. Unit
4567B–DECT–03/06 T2801 Ramp Generator, Pins 36 and 37 Minimum output voltage According to RAMP_SET input V min 0.7 V Maximum output voltage According to RAMP_SET input V max 2.2 V Rise time C ramp = 270 pF at pin 37 t r 5µ s Fall time C ramp = 270 pF at pin 37 t f 5µ s Lock Detect and Test Mode Output Pin 5 Lock detect output, test mode output Locked = ‘1’, unlocked = ‘0’ Test modes (see bus protocol E0 ... E2) LD Leakage current V OH = 4.6V I L 5µ A Saturation voltage I OL = 0.5 mA V SL 0.4 V Auxiliary Regulator, Pins 8, 9 and 10 Output voltage V SREG = 3V, pin 8 V REG 2.9 3.0 3.1 V Supply voltage rejection VPin10 = VDC + 0.1Vpp fPin10 = 0.1 to 10 kHz CPin8 = 100 nF SVR TBD dB VCO Regulator; Pins 14, 15 and 12 Output voltage V SVCO = 3V, pin 15 V REG_VCO 2.6 2.7 2.8 V 3-wire Bus Clock f Clock 6.912 MHz Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, I_CPSW), Pins 1, 2, 3, 38, 39, 44, 47 and 48 High input level = ‘1’ V iH 1.5 V Low input level = ‘0’ V iL 0.5 V High input current = ‘1’ I iH -5 5 µA Low input current = ‘0’ I iL -5 5 µA Standby Control, Pins 6, 45 and 46 Power up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input level Pin 6 Pin 45 Pin 46 VPU_REG VPU_RX/TX VPU_PLL 2.0 V Standby PU_REG = ‘0‘ PU_RX/TX = ‘0‘ PU_PLL = ‘0‘ Low input level Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OF F VPU_PLL,OFF 0.7 V Power up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input current VPU = 3V, pin 6 VPU = 5.5V, pin 45 VPU = 3V, pin 46 VPU = 5.5V IPU_REG IPU_RX/TX IPU_PLL 100 200 125 300 100 150 400 µA µA µA µA Standby PU_xxxx = ‘0’ Low input current VPU = 0V, pin 6, VPU = 0.5V, pins 45, 46 IPU,OFF 0.1 µA µA 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions /Pins Symbol Min. Typ. Max. Unit
4567B–DECT–03/06 T2801 Settling Time VS = 0 → active operation Switched from VS = 0 to VS = 3V t soa < 10 µs Settling Time Standby → active operation Switched from PU = ‘0’ to PU = ‘1’ t ssa < 10 µs Settling Time Aactive operation → standby Switched from PU = ‘1’ to standby t sas < 2 µs Power Supply Pins 7, 10, 12, 14, 33 and 42 Total supply current RX I S 85 mA Total supply current RSSI only I S 82 mA Total supply current TX I S 54 mA Total supply current TX (MCC, GF active) I S 58 mA Standby current PU_RX/TX = GND I S 10 µA Supply current CP VVS_CP = 3V, PLL in lock condition, pin 13 ICP 1µ A 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions /Pins Symbol Min. Typ. Max. Unit
4567B–DECT–03/06 T2801 12. T2801 Aplication Circuit VCC BB_OUT RSSI
48 I_CPSW
47 TX_DATA
46 PU_PLL
45 PU_RX/TX
44 PU_VCO
43 GND_PLL
42 VS_MIXER
41 MIXER_OUT2
40 MIXER_OUT1
39 TX_ON
38 RX_ON
37 RAMP_SET
VS_VC O 14 VRE G_VC O 15 GND_VCO 16 VTUN E 17 GND1 18 DEMOD_TA NK1 19 DEMOD_TA NK2 20 DA C_DEC 21 REG_DEC 22 BB_CF 23 BB_OUT 24
12 VS_CP
ND_CP
10 VS_REG
9 REG
_CTRL
8 VREG
7 VS_PLL
6 PU_REG
4 REF_CLOCK
3 ENABLE
2 DATA
1 CLO
IF_TANK1 26 IF_TANK2 27 G ND2 28 RF_IN1 29 RF_IN2 30 G ND3 31 TX_O UT 32 VS_IF 33 IF_IN1 34 IF_IN2 35 RAM P_O UT 36 PU_V CO PU_RX/TX PU_PLL TX_DATA I_CPSW TX_ON RX_ON LD PU_REG CLOCK DA TA ENA BLE REF_CLK BC808 or similar 560 pF 220 pF 15 pF 15 pF 270 nH 33 pF 33 pF 180 nH 56 pF 470 nF
180 W 150 nF
2.2 nF 100 pF tbd tbd 18 pF 100 nH TX_OUT RF_IN SAW Filter TFS 112B tantal tantal 4.7 nF RA MP_OUT 68 pF T2801
4567B–DECT–03/06 T2801 14. Package Information 13. Ordering Information Extended Type Number Package Remarks T2801-PLQ QFN48 Taped and reeled 5.1±0.15 6.75 0.5 specifications according to DIN technical drawings Issue: 3; 24.01.03 Drawing-No.: 6.543-5068.01-4 10:1 Package: QFN 48 - 7 x 7 Exposed pad 5.1 x 5.1 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm 5.5 4837 0.42×45˚ 0.85+0.15 0.65+0.15 0.01-0.01 +0.04 0.4-0.10 +0.05 0.23-0.05 +0.07
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