T2801 ATMEL | Alldatasheet
Document overview
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Technical content
Features
Supply-voltage range 3 V to 4.6 V (unregulated) Auxiliary-voltage regulator on-chip Low current consumption Few low cost external components No mechanical tuning required Non-blindslot and blindslot operation Unlimited multislot operation with advanced closed- loop modulation Supports multiple reference clocks (10.368 MHz/ 13.824 MHz/ 20.736 MHz) TX preamplifier with 0 dBm output power at 1.9 GHz and ramp-signal generator for SiGe power amplifier Block Diagram TANK PC RC GF MCC CP VCO f : n f : n CTRL LOGIC PD TX / RX SWITCH IR MIXER IF AMP 1 IF AMP 2 DEMOD BB FILTER 3-WIRE BUS DEMOD DAC RSSI TX DRIVER CLOCK DATA ENABLE RX_ON TX_ON PU_RX/TX PU_PLL TX_DATA RSSI BB_OUT CF DEMOD IF_TANKIF_IN MIXER OUT RF_IN TX_OUT VS_VCO CP LD REF_CLK VTUNEVREG VS_REG REG_CTRL VREG_VCO VCO REG RAMP GEN RAMP_OUT RAMP_SET AUX REG PU_VCO PU_REGGND_VCO D/A I_CPSW Figure 1. Block diagram
Ordering Information
Extended Type Number Package Remarks T2801-PLH HP-VFQFP-N48 Taped and reeled
Figure 2. Pinning
Rev. A9, 11-Dec-01 3 (27) Pin Description Pin Symbol Function Configuration
1 CLOCK 3-wire-bus: Clock input VS_PLL
2 DA TA 3-wire-bus: Data input
1233 ENABLE 3-wire-bus: Enable input
1,2,3 5k 5k GND_PLL
4 REF_CLK Reference-frequency input VS_PLL
REF_CLK 10k GND_PLL 10k
5 LD Lock-detect output
GND_PLL 100 LD 6 PU_REG Power-up input for aux. voltage regulator PU_REG 25k 25k GND_PLL
Rev. A9, 11-Dec-01 Preliminary Information 4 (27) Pin Description (continued) Pin Symbol Function Configuration
7 VS_PLL PLL supply voltage
GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL 8 VREG Aux. voltage-regulator output REG_CTRL VS_REG 9 REG_CTRL Aux. voltage-regulator control output VREG 10 VS_REG Aux. voltage-regulator supply voltage GND_PLL
11 GND_CP Charge-pump ground VS_CP
12 VS_CP Charge-pump supply voltage CP
13 CP Charge-pump output
GND_CP
Rev. A9, 11-Dec-01 5 (27) Pin Description (continued) Pin Symbol Function Configuration
14 VS_VCO VCO voltage-regulator supply
VS_VCO VREG VCO
15 VREG_VCO VCO voltage-regulator control
VREG_VCO
16 GND_VCO VCO ground
GND_VCO
17 VTUNE VCO tuning voltage input
GND_VCO VREG_VCO
18 GND1 Ground
GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
Rev. A9, 11-Dec-01 Preliminary Information 6 (27) Pin Description (continued) Pin Symbol Function Configuration
19 DEMOD_TANK1 Demodulator tank circuit
DEMOD_ TANK1 10k 10k DEMOD_ TANK2 VS_MIXER
20 DEMOD_TANK2 Demodulator tank circuit
21 DAC_DEC Decoupling PIN for VCO_DAC
DAC_DEC 10k GND_VCO 400 VREG_VCO
22 REG_DEC Decoupling PIN for VCO_REG
REG_DEC 42k VREG_VCO GND_VCO
23 BB_CF Baseband filter corner-frequency
BB_CF VS_IF GND1
Rev. A9, 11-Dec-01 7 (27) Pin Description (continued) Pin Symbol Function Configuration
24 BB_OUT Baseband filter output VS_IF
BB_OUT
25 RSSI Received signal-strength indicator
VS_IF RSSI 13k GND2
26 IF_TANK1 IF tank circuit
IF_TANK1 VS_IF IF_TANK2
27 IF_TANK2 IF tank circuit
28 GND2 Ground
GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
Rev. A9, 11-Dec-01 Preliminary Information 8 (27) Pin Description (continued) Pin Symbol Function Configuration
29 RF_IN1 RF input of image reject mixer
VS_MIXER RF IN2
30 RF_IN2 RF input of image reject mixer
RF _IN1 GND2 RF _IN2
31 GND3 Ground
GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
32 TX_OUT TX driver amplifier output for PA TX_OUT
Rev. A9, 11-Dec-01 9 (27) Pin Description (continued) Pin Symbol Function Configuration
33 VS_IF IF amplifier supply voltage
GND_PLL GND2 GND1 GND3 GND_CP GND_VCO VS_MIXER VS_IF VS_VCO VS_CP VS_REG VS_PLL
34 IF_IN1 IF input of IF amplifier
IF IN1 IF IN24.3k VS_IF
35 IF_IN2 IF input of IF amplifier
IF_IN1 IF_IN2 4.3k GND2
36 RAMP_OUT Ramp-generator output for PA
power ramping VS_MIXER GND2 RAMP_OUT
Rev. A9, 11-Dec-01 Preliminary Information 10 (27) Pin Description (continued) Pin Symbol Function Configuration
37 RAMP_SET Slew-rate setting of ramping signal
RAMP_SET VS_MIXER GND2
38 RX_ON RX control input VS_IF
39 TX_ON TX control input RX_ON
TX_ON 38, 39 5k 5k GND1
40 MIXER_OUT1 Mixer output to SAW filter
270 270 MIXER_ OUT2 MIXER_ OUT1 VS_MIXER
41 MIXER_OUT2 Mixer output to SAW filter
Rev. A9, 11-Dec-01 11 (27) Pin Description (continued) Pin Symbol Function Configuration
42 VS_MIXER Mixer supply voltage
VS_VCO VS_CP VS_REG VS_PLL
43 GND_PLL PLL ground
GND_PLL GND_CP GND_VCO VS_MIXER VS_IF
44 PU_VCO VCO power-up input
PU_VCO 5k 5k VS_VCO GND_VCO
45 PU_RX/TX RX/TX power-up input
PU_RX/TX 25k 25k GND1
Rev. A9, 11-Dec-01 Preliminary Information 12 (27) Pin Description (continued) Pin Symbol Function Configuration
46 PU_PLL PLL power-up input
PU_ PLL 25k 25k 10k 10k 140k GND_ PLL 10k 20k
47 TX_DATA TX data input of Gaussian filter and
modulation-compensation circuit TX_DA TA 5k 5k VS_PLL GND_PLL
48 I_CPSW Charge pump switch input controls
I_CPSW VS_PLL GND_PLL
Rev. A9, 11-Dec-01 13 (27) Functional Description Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = f IF/2 (55 MHz) and finally to an integrated baseband filter BB. For demodulator tuning in production an integrated 5-bit dig- ital-to-analog (D/A) converter is provided to control the on-chip varicap diode. Transmitter The transmit data at TX_DA TA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typical +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, pro- vides a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. Synthesizer The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). An 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequency- divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detec- tor PD (f PD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC. Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is imple- mented. Multiple power-down and current saving modes are provided.
Rev. A9, 11-Dec-01 Preliminary Information 14 (27) PLL Principle RF_IN Programable counter PC ”– Main counter MC ”– Swallow counter SC fVCO = fPD x (SMC x 32 + SSC ) fVCO Phase frequency Divider by 2 PA driver detector PD VCO Mixer VCO DAC fPD = 3.456 MHz GF_DATA Controlled phase shifting Modulation Gaussian compensation MCC filter GF Reference counter RC 6.912 MHz REF_CLK SRC 13.824MHz 4 20.736MHz 6
1.152 Mbit/s
PLL reference TX_DATA Frequency REF_CLK Baseband controller 310.368MHz ext. loop filter Charge pump Figure 3.
Rev. A9, 11-Dec-01 15 (27) The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 1 LO frequencies Mode fIF/MHz Channel fANT /MHz fVCO /MHz SMC SSC TX C9 1881.792 1881.792 34 1 C8 1883.520 1883.520 34 2 C1 1895.616 1895.616 34 9 C0 1897.344 1897.344 34 10 C10 1899.072 1899.072 34 11 C11 1900.800 1900.800 34 12 C29 1931.904 1931.904 34 30 C30 1933.632 1933.632 34 31 RX 110.592 C9 1881.792 1771.200 32 1 C8 1883.520 1772.928 32 2 C1 1895.616 1785.024 32 9 C0 1897.344 1786.752 32 10 C10 1899.072 1788.480 32 11 C11 1900.800 1790.208 32 12 C29 1931.904 1821.312 32 30 C30 1933.632 1823.040 32 31 RX 112.320 C9 1881.792 1769.472 32 0 C8 1883.520 1771.200 32 1 C1 1895.616 1783.296 32 8 C0 1897.344 1785.024 32 9 C10 1899.072 1786.752 32 10 C11 1900.800 1788.480 32 11 C29 1931.904 1819.584 32 29 C30 1933.632 1821.312 32 30 Formula TX: f ANT = fVCO = 1.728 MHz × (32 × SMC + SSC ) RX: f ANT = 1.728 MHz × (32 × SMC + SSC ) + fIF
Rev. A9, 11-Dec-01 Preliminary Information 16 (27) Control Signals Table 2 Signal Function I_CPSW Controls the charge pump current PU_REG Activates AUX voltage regulator supplying the complete transceiver. PU_VCO Activates VCO voltage regulator which supplies only the VCO. PU_RX/TX Activates RX/TX switch. PU_PLL Activates PLL circuits: PC, PD, CP , RC RX_ON Activates RX circuits: BBF, DEMOD, IF AMP , IR MIXER TX_ON Activates TX circuits: TX-DRIVER, RAMP GEN. Starts RAMP SIGNAL at RAMP OUT. Data Word 1 Bit D10 Activates GF in TX mode. Data Word 1 Bit D9 Activates MCC in TX mode. Table 3 Mode TX Mode RX Mode RSSI Only PU_REG 1 1 1 PU_VCO 1 1 1 PU_RX/TX 1 1 1 PU_PLL 1 1 1 RX_ON 0 1 1 TX_ON 1 0 1 BB filter OFF ON OFF Demodulator OFF ON OFF IF amplifiers and RSSI OFF ON ON IR mixer OFF ON ON RX switch OFF ON ON TX switch ON OFF OFF TX driver ON OFF OFF Ramp generator ON OFF OFF Programmable counter ON ON ON V oltage-controlled oscillator ON ON ON Gaussian filter ON OFF OFF Phase detector / charge pump ON ON ON Modulation compensation circuit ON OFF OFF Reference counter ON ON ON Typ. current consumption / mA @ VS = 3.2 V 54 85 80
Rev. A9, 11-Dec-01 17 (27) Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DA TA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. After enable returning to high condition the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses arrived during enable-low condition. During enable low condition the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel in- formation together with settings, which are closely related with the channel. Dataword 2 holds setup informa- tion, which is adjusted during production. Data Word 1 MSB LSB Data bits Address bit D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 RC SC MC VCOS 1 1 GF MCC GFCS VCODAC CPCS 1 Data Word 2 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 A0 DEMODDAC MCCS TEST 0 Data Word 1 Programs PLL Settings With the Reference Counter bits D21 – D22 RC (Reference Counter) D22 D21 SRC REF_CLK 0 0 3 10.368 MHz 0 1 4 13.824 MHz 1 0 6 20.736 MHz With the Main Counter bits D14 – D15 MC (Main Counter) D15 D14 SMC 0 0 32 0 1 33 1 0 34 1 1 35 With the Swallow Counter bits D16 – D20 SC (Swallow Counter) D20 D19 D18 D17 D16 SSC 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31
Rev. A9, 11-Dec-01 Preliminary Information 18 (27) VCO Select (RX/TX VCO) With bit D13 Used to switch between RX/TX VCO D13 VCOS (VCO Select)
0 RX-VCO
1 TX-VCO
GF is used only in TX mode D10 GF (Gaussian Filter)
0 OFF
Modulation Compensation Circuit on/off With bit D9 MCC is used only in TX mode D9 MCC (Modulation Compensation Circuit) With bit D6 – D8 Only in TX mode effective for setting the frequency devi- ation of the modulation GFCS (Gaussian Filter Settings) D8 D7 D6 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% VCO_DAC Adjustment With bit D3 – D5 Used to pretune the VCO frequency in case of production tolerances of the device. Tuning voltage in locked condi- tion should be around 1.8 V at room temperature. This gives margin for ambient temperature changes. Pretune DAC Voltage D5 D4 D3 fVCO /% 0 0 0 –5 0 0 1 ... 0 1 0 ... 0 1 1 ... 1 0 0 ... 1 0 1 ... 1 1 0 ... 1 1 1 5 CPCS Adjustment With bit D0 – D2 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances. CPCS (Charge-Pump Current Settings) D2 D1 D0 CPCS 0 0 0 –4 0 0 1 –3 0 1 0 –2 0 1 1 –1 1 0 0 0 1 0 1 1 1 1 0 2 1 1 1 3
Rev. A9, 11-Dec-01 19 (27) Data Word 2 Programs DEMODDAC Adjustment With bits E6 – E10 Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of external components and the T2801. Demod DAC Voltage E10 E9 E8 E7 E6 fIFcenter % 0 0 0 0 0 –5 0 0 0 0 1 ... 0 0 0 1 0 ... ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 5 MCCS Adjustment With bits E3 – E5 Only in TX mode effective. Adjusts the modulation com- pensation circuit for closed loop modulation. This adjustment is done with a test sequence of a long stream of ,1‘ – ,0‘. The correct setting is achieved, if the modula- tion is not affected by the PLL. MCCS (Modulation Compensation Settings) E5 E4 E3 MCCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% TEST Mode Settings With bit E0 – E2 and D11 In normal operation Lock detect output is used. All other settings are for test only. D11 E2 E1 E0 Signal at lock detect output CP mode 1 0 0 0 Lock detect Active 0 0 0 1 RC out Active 1 0 1 0 PC out Active X 0 1 1 MCCTEST: RC out divided by 2048 Active 1 1 0 0 Lock detect High imp. 0 1 0 1 RC out High imp. 1 1 1 0 PC out High imp. X 1 1 1 GFTEST: RC out divided by 2 High imp.
Rev. A9, 11-Dec-01 21 (27) Operating Range Parameter Symbol Min. Typ. Max. Unit Supply voltage regulator Pins 10 V S_REG 3.2 3.6 4.6 V Supply voltage Pins 7, 12, 14, 33 and 42 V S 3.0 3.0 4.6 V Ambient temperature Tamb –25 +85 C
Electrical Characteristics
Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25°C Parameter Test Conditions / Pins Symbol Min. Typ. Max. Unit IR mixer Pins 29, 30, 40 and 41 Input impedance Pins 29 and 30 Zin 50 Ω Input matching Pins 29 and 30 VSWR in <2:1 Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Pins 40 and 41 NFDSB= NFSSB 10 dB Conversion gain R load = 200 Ω G conv 11 dB Input interception point Pins 40 and 41 IIP3 –10 dBm IF amplifier Pins 26, 27, 34 and 35 Input impedance Pins 34 and 35 Zin 200 400 Ω Lower cut-off frequency fl3dB 90 MHz Upper cut-off frequency fu3dB 130 MHz Power gain Gp 85 dB Bandwidth of external tank circuit Pins 26 and 27 BW3dB 10 MHz Noise figure NF 9 dB RSSI Pins 25, 34 and 35 RSSI sensitivity at IF_IN1, IF_IN2 Pins 34 and 35 Pmin 20 dB µV RSSI compression at IF_IN1, IF_IN2 Pins 34 and 35 Pmax 100 dB µV RSSI dynamic range DR 80 dB RSSI resolution Slope of the RSSI has to be steady Acc ±2 dB RSSI rise time Pin = 30 to 100 dBµV , Pin 25 tr 1 µs RSSI fall time Pin = 100 to 30 dBµV , Pin 25 tf 1 µs Quiescent output current @ P in < 20 dBµV at IF_IN1, IF_IN2 Pin 25 Iout 30 µA Maximum output current @ P in = 100 dBµV at IF_IN1, IF_IN2 Pin 25 Iout 150 µA
Rev. A9, 11-Dec-01 Preliminary Information 22 (27) Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25°C UnitMax.Typ.Min.SymbolTest Conditions / PinsParameter FM demodulator, BB-Filter Pins 19, 20, 23 and 24 Co-channel rejection ratio@ P in = –75 dBm at IR-mixer input CCRR 10 dB Sensitivity Quality factor of external tank circuit approx. 20, f res = FIF/2, Pin 24 S 0.5 V/MHz Amplitude of recovered signal Nominal deviation of signal ± 288 kHz, Pin 24 A 450 mVss Corner frequency Pin 23: C = 68 pF fc 680 kHz Output voltage DC range Pin 24 VoutDC 1 Vs–1 V DAC for FM demodulator (internally connected) DEMOD_DAC range (see bus protocol E6 ... E10)fIFcenter ± 5 % VCO RX–VCO frequency range VCOS = ‘0’ Bit D13 fvco 1750 1840 MHz TX–VCO frequency range VCOS = ‘1’ Bit D13 fvco 1860 1950 MHz Tuning gain G tune 40 MHz/V Frequency control voltage range Pin 17 V tune 0.4 2.8 V VCO_DAC range (see bus protocol D3 ... D5)Δfvco,DAC ± 5 % PLL Scaling factor prescaler SPSC 32 / 33 Scaling factor main counter SMC 32 / 33 / 34 / 35 Scaling factor swallow counter SSC 0 31 External reference input frequency AC coupled sinewave Pin 4 fREF_CLK 10.368 13.824 20.736 MHz MHz MHz External reference input voltage AC coupled sinewave Pin 4 V REF_CLK 50 250 mV RMS Scaling factor reference counter SRC 3 / 4 / 6 / 8 Charge pump Pin 13 Output current V CP = VVS_CP / 2, I_CPSW = ‘1’ Pin 48 ICP_nom ± 6.5 mA Output current V CP = VVS_CP / 2, I_CPSW = ‘0’ Pin 48 ICP_nom ± 1.2 mA Current scaling ICP = ICP_nom + CPCS * ICP_step (see bus protocol D0 ... D2) ICP_step 0.2 mA Leakage current IL ± 100 pA
Rev. A9, 11-Dec-01 23 (27) Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25°C UnitMax.Typ.Min.SymbolTest Conditions / PinsParameter Gaussian transmit filter (Gaussian shape B∗T = 0.5) Tx data filter clock 12 taps in filter fTXFCLK 13.824 MHz Frequency deviation GF FM_nom ±350 kHz Frequency deviation scalingGF FM = GFFM_nom * GFCS (see bus protocol D6 ... D8) GFCS 60 130 % Modulation compensation circuit Oversampling OVS 6 Digital sum variation DSV 85 Current scaling factor (see bus protocol E3 ... E5) MCCS 60 130 % VCO switch and TX driver Pin 32 Power gain @ P in = –40 dBm Gp 30 dB Output impedance Pin 32 Zout 100 Ω Maximum output power Pin 32 Pmax 0 3 dBm Gain compression @ TX_RF_OUT, Pin 32 P1dB 1 dBm Output interception point Pin 32 OIP3 10 dBm Ramp generator Pins 36 and 37 Minimum output voltage According to RAMP_SET input V min 0.2 V Maximum output voltage According to RAMP_SET input V max 1.95 V Rise time C ramp = 270 pF at Pin 37 tr 5 µs Fall time C ramp = 270 pF at Pin 37 tf 5 µs Lock detect and test mode output Pin 5 Lock detect output, test mode output locked = ‘1’, unlocked = ‘0’ test modes (see bus protocol E0 ... E2) LD Leakage current V OH = 4.6 V IL 5 µA Saturation voltage IOL = 0.5 mA V SL 0.4 V Auxiliary regulator Pins 8, 9 and 10 Output voltage V SREG = 3 V Pin 8 V REG 2.9 3.0 3.1 V Supply voltage rejection V Pin10 = VDC + 0.1 Vpp fPin10 = 0.1 to 10 kHz C Pin8 = 100 nF SVR t.b.d. dB VCO regulator Pins 14, 15 and 12 Output voltage V SVCO = 3 V Pin 15V REG_VCO 2.6 2.7 2.8 V 3-wire bus Clock fClock 6.912 MHz
Rev. A9, 11-Dec-01 Preliminary Information 24 (27) Electrical Characteristics (continued) Test conditions (unless otherwise specified): VS_REG = 3.2 V , Tamb = 25°C UnitMax.Typ.Min.SymbolTest Conditions / PinsParameter Logic input levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, I_CPSW) Pins 1, 2, 3, 38, 39, 44, 47 and 48 High input level = ‘1’ V iH 1.5 V Low input level = ‘0’ V iL 0.5 V High input current = ‘1’ IiH –5 5 µA Low input current = ‘0’ IiL –5 5 µA Standby control Pins 6, 45 and 46 Power up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input level Pin 6 Pin 45 Pin 46 V PU_REG V PU_RX/TX V PU_PLL 2.0 V Standby PU_REG = ‘0‘ PU_RX/TX = ‘0‘ PU_PLL = ‘0‘ Low input level Pin 6 Pin 45 Pin 46 V PU_REG,OFF V PU_RX/TX,OFF V PU_PLL,OFF 0.7 V Power up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input current V PU = 3 V Pin 6 V PU = 5.5 V Pin 45 V PU = 3 V Pin 46 V PU = 5.5 V IPU_REG IPU_RX/TX IPU_PLL 100 200 125 300 100 150 400 µA µA µA µA Standby PU_xxxx = ‘0’ Low input current V PU = 0 V Pin 6, V PU = 0.5 V Pins 45, 46 IPU,OFF 0.1 µA µA Settling time V S = 0 → active operation Switched from V S = 0 to VS = 3V tsoa < 10 µs Settling time standby → active operation Switched from PU = ‘0’ to PU = ‘1’ tssa < 10 µs Settling time active operation → standby Switched from PU = ‘1’ to standby tsas < 2 µs Power supply Pins 7, 10, 12, 14, 33 and 42 Total supply current RX IS 85 mApp y RSSI only IS 82 mA TX IS 54 mA TX (MCC, GF active) IS 58 mA Standby current PU_RX/TX = GND IS 1 10 µA Supply current CP V VS_CP = 3 V , PLL in lock condition Pin 13 ICP 1 µA
48 I_CPSW
47 TX_DA TA
46 PU_PLL
45 PU_RX/TX
44 PU_VCO
43 GND_PLL
42 VS_MIXER
41 MIXER_OUT2
40 MIXER_OUT1
39 TX_ON
38 RX_ON
37 RAMP_SET
12 VS_CP
11 GND_CP
10 VS_REG
9 REG_CTRL
8 VREG
7 VS_PLL
6 PU_REG
4 REF_CLOCK
3 ENABLE
2 DA TA
1 CLOCK
Figure 6. Application circuit
Rev. A9, 11-Dec-01 Preliminary Information 26 (27)
Package Information
Rev. A9, 11-Dec-01 27 (27) Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. V arious national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel products for any unintended or unauthorized application, the buyer shall indemnify Atmel against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel–wm.com Atmel Germany GmbH, P .O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423