STW12NK80Z STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 800V - 0.65Ω - 10.5A TO-247 Zener-Protected SuperMESH™Power MOSFET ■ TYPICAL R DS (on) = 0.65 Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ GATE CHARGE MINIMIZED ■ VERY LOW INTRINSIC CAPACITANCES ■ VERY GOOD MANUFACTURING REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip- based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is tak- en to ensure a very good dv/dt capability for the most demanding applications. Such series comple- ments ST full range of high voltage MOSFETs in- cluding revolutionary MDmesh™ products.

APPLICATIONS

■ HIGH CURRENT, HIGH SPEED SWITCHING ■ IDEAL FOR OFF-LINE POWER SUPPLIES

ORDERING INFORMATION

TYPE V DSS R DS(on) ID Pw STW12NK80Z 800 V < 0.75 Ω 10.5 A 190 W SALES TYPE MARKING PACKAGE PACKAGING STW12NK80Z W12NK80Z TO-247 TUBE TO-247 INTERNAL SCHEMATIC DIAGRAM

(/c108 ) Pulse width limited by safe operating area (1) ISD ≤10.5A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. (*) Limited only by maximum temperature allowed THERMAL DATA AVALANCHE CHARACTERISTICS GATE-SOURCE ZENER DIODE PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 800 V V DGR Drain-gate Voltage (RGS = 20 kΩ ) 800 V VGS Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 10.5 A ID Drain Current (continuous) at TC = 100°C 6.6 A IDM (/c108 ) Drain Current (pulsed) 42 A PTOT Total Dissipation at TC = 25°C 190 W Derating Factor 1.51 W/°C VESD(G-S) Gate source ESD(HBM-C=100pF, R=1.5KΩ) 6000 V dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns Tj Tstg Operating Junction Temperature Storage Temperature -55 to 150 °C Rthj-case Thermal Resistance Junction-case Max 0.66 °C/W Rthj-amb Tl Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 300 °C/W Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 10.5 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 400 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit BV GSO Gate-Source Breakdown Voltage Igs=± 1mA (Open Drain) 30 V

ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF DYNAMIC SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS . Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 800 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS , ID = 100 µA 3 3.75 4.5 V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 5.25 A 0.65 0.75 Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance V DS = 15 V, ID = 5.25 A 12 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25V, f = 1 MHz, VGS = 0 2620 250 pF pF pF C oss eq. (3) Equivalent Output Capacitance VGS = 0V, VDS = 0V to 640V 100 pF Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 400 V, ID = 5.25 A R G = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 640V, ID = 10.5 A, VGS = 10V nC nC nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time VDD = 400 V, ID = 5.25 A R G =4 . 7Ω VGS = 10 V (Resistive Load see, Figure 3) ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time VDD = 640 V, ID = 10.5 A, R G =4 . 7Ω, VGS = 10V (Inductive Load see, Figure 5) ns ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) 10.5 A A VSD (1) Forward On Voltage ISD = 10.5 A, VGS = 0 1.6 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 10.5 A, di/dt = 100A/µs VDD = 100 V, Tj = 150°C (see test circuit, Figure 5) 635 5.9 18.5 ns µC A

Static Drain-source On ResistanceTransconductance Thermal Impedance For TO-247Safe Operating Area For TO-247 Transfer CharacteristicsOutput Characteristics

Gate Charge vs Gate-source Voltage Normalized BVDSS vs TemperatureSource-drain Diode Forward Characteristics Normalized Gate Threshold Voltage vs Temp. Normalized On Resistance vs Temperature Capacitance Variations

Maximum Avalanche Energy vs Temperature

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm. inch A 4.85 5.15 0.19 0.20 D 2.20 2.60 0.08 0.10 E 0.40 0.80 0.015 0.03 F 1 1.40 0.04 0.05 F1 3 0.11 F2 2 0.07 F3 2 2.40 0.07 0.09 F4 3 3.40 0.11 0.13 G 10.90 0.43 H 15.45 15.75 0.60 0.62 L 19.85 20.15 0.78 0.79 L1 3.70 4.30 0.14 0.17 L2 18.50 0.72 L3 14.20 14.80 0.56 0.58 L4 34.60 1.36 L5 5.50 0.21 M 2 3 0.07 0.11 V 5º5 º V2 60º 60º Dia 3.55 3.65 0.14 0.143 TO-247 MECHANICAL DATA

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