STU2071

STU2071 STMICROELECTRONICS | Alldatasheet

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4B3T TWO-WIRE U INTERFACE CIRCUIT FOR LT AND NT APPLICATION 120 kbaud LINE SYMBOL RATE (120 SYM- BOLS PER FRAME) SCRAMBLER AND DESCRAMBLER AC- CORDING TO CCITT REC V.29 BARKER CODE (11 SYMBOLS) SYNCHRO- NIZATION WORD UNSCRAMBLED 1 KBIT/S HOUSEKEEPING CHANNEL ADAPTIVE ECHO CANCELLATION WITH TRANSVERSAL FILTERING ADAPTIVE DECISION FEEDBACK EQUALI- ZATION AUTOMATIC GAIN CONTROL PDM AD CONVERTER AUTOMATIC ACTIVATION AND DEACTIVA- TION WITH POLARITY ADAPTION AUTOMATIC CODE VIOLATION DETECTION POWER FEED UNIT CONTROL ADVANCED CL3 1.5 µm CMOS PROCESS

28 PIN DUAL-IN-LINE PLASTIC PACKAGE

V* DIGITAL INTERFACE SYSTEM OVERVIEW STU2071 (UIC) provides two transparent 64 kbit/s B channels, a transparent 16 kbit/s D channel, a transparent 1 kbit/s service channel and a 1 kbit/s maintenance channel for loop and error mes- sages on subscriber lines. UIC enables full duplex continuous data transmis- sion via the standard twisted pair telephone ca- ble. Adaptive Echo cancellation is used to restore the received data. An equalizer, done with an adaptive filter, restores the data which are dis- torted by the transmission line. The coefficient of the equalizer and echo cancel- ler are conserved during a power down. An all digital PLL performs both bit and frame synchroni- zation. The analog front end consists of receive path RX and transmit path TX, providing a full duplex ana- log interfacing to the twisted pair telephone cable. Before data are converted to analog signals, they pass through a digital filter (TX-filter) to reduce the high frequency components. After D/A con- version the signal is amplified and sent to the hy- brid. The received signal is converted back to digital data and passed through the RX matching filter to restore the line signal. The A/D convertor is a second order sigma/delta modulator which oper- ates with a clock of 15.36 MHz. After timing re- covery, achieved by a digital PLL, the received signal is equalized, in an adaptive digital filter, to correct for the frequency and group delay distor- tion of the line. Power supply status can be read via PFOFF. The UIC can disable its power supply (DISS), and two relay drivers outputs are provided (accessible via B2*) to control the power feed unit (RD1,RD2). This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. September 1994 DIP28 ORDERING NUMBER: STU2071B1 PLCC28 ORDERING NUMBER: STU2071FN

PIN CONNECTION (Top view) Figure 1: UIC Schematic Block Diagram 1234 2628 27 15141312 18 16 17 DVSS PFOFF LT TEST XTAL1 CLS XTAL2 DISS/COEF RESETN DIN TSP FR BURST DOUT LIN2 LIN1 LOUT2 AGND LOUT1 AVDD AVSS RD2 RD1 CL DVDD D93TL041 DIP28 PLCC28 STU2071

The UIC can be used in LT, LT-burst and in NT mode. Hereafter a list of the pin bias to set up the de- sired mode is given. In LT mode: Pins Value LT BURST In LT burst: Pins Value LT BURST time slot time slot time slot In NT: Pins Value LT BURST Test pins should always be tied to GND PIN DESCRIPTION Pin Name Function 1 DVSS(input) Digital Ground. 2 PFOFF(input) Power feed off. PFOFF=HIGH is coded by the A-bit indication HI accessible on DOUT. Active in LT mode only. 3 LT(input) LT/NT mode selection. 4 TEST(input) Test Mode. 5 DISS(output) A bit channel driven pin. Active in LT mode only. 6 RESETN(input) Hardware Reset. 7 DIN(input) Digital interface input. 8 TSP(input) Transmit single pulse. 1 KHz single pulse alternating positive and negative polarity is transmitted. 9 BURST(input) Burst mode selection. Active in LT mode only. 10 FR(in/out) 8KHz Digital interface frame clock; input in LT and output in NT mode. 11 DOUT(output) Digital interface output. 12 CL(in/out) Digital interface bit clock; input in LT and output in NT mode. 13 RD1(output) Power feeder relay driver. 14 RD2(output) Power feeder relay driver. 15, 16, 17 S2,S1,S0 Time slot pin strap (. Active in LT mode only. 18 DVDD(input) 5V +/-5% positive digital power supply. 19 AVSS(input) Analog Ground. 20 LOUT1(output) Output to the line. 21 AVDD(input) 5V +/-5% positive analog power supply. 22 AGND(input) Analog Ground. 23 LOUT2(output) Output to the line. 24,25 LIN1,LIN2(input) Inputs from the line (UK0). 26, 27 XTAL1,XTAL2(inputs) System clock input;nominal frequency is 15.36MHz. 28 CLS(output) Clock output synchronous to the line receive clock at 7.68MHz. STU2071

S2, S1, S0 input static 1 0 0 0 0 0 0 0 1 0 1 0 DIN DOUT input output 2048 kbit/s 256 kbit/s 256 kbit/s 256 kbit/s 256 kbit/s CLS (MHz) output 7.68 7.68 7.68 – 7.68 CL (KHz) input output 4096 512 512 512 512 FR (KHz) input output Figure 2: LT Schematic Application Diagram DIN: DOUT: CL: FR: XTAL2: CLS: Data input, datarate = 256 kbit/s, continuous Data output, datarate = 256 kbit/s, continuous Data clock input, f = 512 KHz Frame clock input, f = 8 KHz (1:1) System clock input, f = 15.36 MHz (Tx clock synchronous to system clock) Clock output, 7.68 MHz STU2071

Figure 3: LT Schematic Application Diagram DIN: DOUT: CL: FR: XTAL1/2: CLS: Data input, datarate = 256 kbit/s, continuous Data output, datarate = 256 kbit/s, continuous Data clock input, f = 512 KHz Frame clock input, f = 8 KHz (1:1)

15.36 MHz Xtal connection (Clock not synchronous to system clock)

Clock output, 7.68 MHz (used to synch S interface) STU2071

Figure 4: LT Burst Mode Schematic Application Diagram. DIN: DOUT: CL: FR: XTAL2: CLS: Data input, datarate = 2048 kbit/s, continuous Data output, datarate = 2048 kbit/s, continuous Data clock input, f = 4096 KHz Frame clock input, f = 8 KHz (1:1) System clock input, f = 15.36 MHz (Tx clock synchronous to system clock) Clock output, 7.68 MHz STU2071

15.36MHz PHASE COMPARATOR AND LOOP FILTER(*) UIC NTrep CLOUT 512KHz15.36MHz DOUT DIN CL FR XTAL1 XTAL2 HYBRID To line - LT side A-wire B-wireB-wire DC/DC 0V5V PLL circuit 50mH 50mH 2.2µF 2.2µF (*)1st order loop filter is sufficient (3dB frequency at 100Hz approx.) D94TL099 15.36MHz Figure 5: Repeater Block Diagram. STU2071

LINE FRAME STRUCTURE. The information flow across the subscriber line uses the frame structure here below. The length of one frame corresponds to 120 ternary symbols being transmitted within 1 ms. Figure 8: Burst Mode. 123456789 1 0 1 1 1 2 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 24 T1 T1 T1 T2 T2 T2 T2 T2 T2 T2 T2 T2 36 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 T2 48 T2 T2 T2 T2 T2 T2 T3 T3 T3 T3 T3 T3 60 LT ⇒ NT T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 T3 72 T3 T3 T3 T3 T3 T3 T3 T3 T3 T4 T4 T4 84 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 96 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 T4 108 T4 SW1 120 123456789 1 9 1 1 1 2 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 T5 24 M2 T5 T5 T5 T6 T6 T6 T6 T6 T6 T6 T6 36 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 T6 48 T6 SW2 60 NT ⇒ LT T6 T6 T6 T6 T6 T6 T7 T7 T7 T7 T7 T7 72 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 T7 84 T7 T7 T7 T7 T7 T7 T7 T7 T7 T8 T8 T8 96 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 108 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 T8 120 Agenda: M1, M2 Service Data (ternary) SW1, SW2 Synchronizing Word STU2071

Maintenance and service channel. The ternary symbols M1 and M2 represent non- scrambled data that can be transmitted at a rate of 1 kBaud. Those symbols are used for various purposes: - Maintenance Channel (control test loops (LT → NT) and frame errors (LT → NT) - Service channel (transparent user data and transmit messages from NT to LT) Encoding. The encoding of a binary bit stream is made such that 4 binary bits correspond to 3 symbols of ter- nary symbol stream. The encoding follows the rules of modified monitoring state 43 (MMS43). COMMAND / INDICATE CHANNEL (A bits) Command/Indicate codes are define depending on the mode selected (LT or NT). NT mode COMMANDS (DIN) ACT 1 0 0 0 Activate. Layer 1 is activated at the UK0 interface starting with a ’wake-up’ signal INFO U1W, followed by INFO U1A during synchronization and closed by INFO U1 when synch is gained. AW 0 0 0 0 Awake. Set the module interface from the power-down to the power-up state. No signal is emitted at UK0 interface. Even DIN pin pulled LOW can have the same effect. DC 1 1 1 1 Deactivation confirmation. The module interface is deactivated. The transmitter is disabled but the receiver is still enabled to recognize an awake signal. THe UIC is set in power down state. RES 1 1 0 1 Reset. Reset the UIC to the initial state. SY 1 1 0 0 Synchronize. Drive the UIC in connect through from module interface to line interface. Remark: Executing the command RES (1101) is functionally equivalent to pulling the RESETN pin (6) LOW, with one exception: a) RES command set pin DISS to HIGH (+5V) b) pulling RESETN LOW set pin DISS to LOW (0V). NT mode INDICATION (DOUT) ACT 1 0 0 0 Activate. The synchronous state of the receiver is reached. DC 1 1 1 1 Deactivation confirmation. The transmitter is disabled but the receiver remains enabled to detect awake signals at UK0 UIC is set in power down state. DEAC 0 0 0 0 Deactivate. A request to deactivate INFO U0 has been detected. CT 1 1 0 0 Connection Through. The UIC is fully activated. CTL2 1 1 1 0 Connection through with loop 2. A loop 2 command has been detected at UK0. L2 1 0 1 0 Loop 2. Synchronization has been reached during a Loop 2 activation procedure. RSYN 0 1 0 0 Resynchronization. The receiver has lost framing and is attempting to resynchronize. STU2071

Power consumption of most functions is reduced; module interface is not active; C/I messages can- not be exchanged. ACTIVATION DEACTIVATION The ACTIVATION procedure consists of three steps: AWAKE, SYNCHRONIZE and CONNECT THROUGH. Activation times are (max): COLDSTART 1 sec WARMSTART 170 msec The DEACTIVATION procedure consists of two steps: line DEACTIVATION and POWER DOWN. Deactivation time is (typ) 4 ms. OSCILLATOR Oscillators of 15.36 MHz are required. When in NT a tollerances of +/-30 ppm is allowed, it is ad- visable to use in LT a tollerances of +/-20 ppm. LINE RANGE The LINE RANGE depends on the cable section. Typically: up to 4.2Km with 0.4mm cable - 5.5Km - 0.5mm - - 8.0Km - 0.6mm - Assumed noise level for such performances is 10uV/SQRT(Hz) on a 200KHz bandwidth. LT CLOCK JITTER The phase jitter between Master Clock (15.36MHz) and interface clock (4.096MHz) should not exceed 50ns. LT mode COMMANDS (DIN) ACT 1 0 0 0 Activate. UIC is set in power-up state, executing the complete activation of Layer 1. The transparent channel transmission is enabled. AL 1 0 0 1 Analog Loop. The analog transmitter output is looped back to the receiver input which is disconnected from UK0 interface. A pseudo wake-up procedure is executed. L2 1 0 1 0 Loop 2. Command to close Loop 2 in NT. LTD 0 0 1 1 Line Transmission Disabled. UIC stops transmitting signals on the line and is powered down. DEAC 0 0 0 0 Deactivate. Request to deactivate UK0. RES 1 1 0 1 Reset. Reset the UIC to the initial state. SSP 0 1 0 1 Send Single Pulse. The UIC transmits single pulse at 1 ms time intervals with alternate polarity. L4 1 0 1 1 Repeter loop LT mode INDICATION (DOUT) ACT 1 0 0 0 Activation running. UIC is powered-up and the activation procedure is running. RDS 0 1 1 1 Running Digital Sum. Given during activation procedure. The receiver has reached synchronization. CT 1 1 0 0 Connection Through. Layer 1 activation procedure has been completed. B and D channels are transparently connected. DEAC 0 0 0 1 Deactivation running. UIC is deactivating in response of a DEAC, RES or LTD command. DC 1 1 1 1 Deactivation confirmation. UIC has completed the deactivation procedure. RSYN 0 1 0 0 Resynchronization. The receiver has lost framing and is attempting to resynchronize. HI 0 0 1 1 High Impedance. When pin PFOFF is HIGH indication HI is output and UIC starts transmitting INFO U0. Normally used to indicate that remote feeding has been switched off. STU2071

ELECTRICAL CHARACTERISTICS

Supply Voltages: DVDD = 5V +/- 5% AVDD = 5V +/- 5% AGND = 2.5V +/- 5% (max curr 0.25mA) Power consumption Active = max 280mW (line loaded at 150Ohm) Power down = Typ. 30mW = Max. 50mW DIGITAL INTERFACE STATIC CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit VIH High Level Input Voltage 3.5 V VIL Low Level Input Voltage 1.0 V VOH1 High Level Output Voltage all outputs except DOUT IOH1 = 0.4mA V DD - 0.66 V VOH2 High Level Output Voltage DOUT, (Open Drain) R to DVDD R = 1KΩ VOL1 Low Level Output Voltage all outputs except DOUT IOL1 = 0.4mA 0.33 V VOL2 Low Level Output Voltage DOUT, (Open Drain) IOL1 = 0.7mA 0.4 V C IN Inputs Capacitance, all inputs at DOUT if output is off pF pF C OUT Load Capacitance at all outputs except at DOUT 25 pF C OUT Load Capacitance at DOUT 150 pF IIN Input Leakage Current 1 µA STU2071

DIGITAL INTERFACE DYNAMIC CHARACTERISTICS Burst mode. Parameter Port from to Conditions C R to DVDD Min. Max. pF K Ω ns ns Rise Time tr Fall Time tf FR, CL FR, CL 1.0V 3.5V 3.5V 1.0V Setup Time ts Setup Time ts Setup Time ts Setup Time ts FR FR DIN MPF FR, i – FR, i + DIN +/– MPF +/– CL, i + CL, i + CL, i + CL, i + Hold Time th Hold Time th Hold Time th Hold Time th FR FR DIN MPF CL, i + CL, i + CL, i + CL, i + FR, i – FR, i + DIN +/– MPF +/– Delay Time td Delay Time td DOUT DOUT CL, i – CL, i – DOUT +/– DOUT +/– 150 150 200 Clock Width tc Clock Width tc CL, i CL, i CL +/– CL +/– CL +/– CL –/+ 239 100 249 144 + = rising edge – = falling edge STU2071

DIGITAL INTERFACE DYNAMIC CHARACTERISTICS (continued) Continuous mode. Parameter Port from to Conditions C R to DVDD Min. Max. pF K Ω ns ns Rise Time tr Fall Time tf FR, CL, i FR, CL, i 1.0V 3.5V 3.5V 1.0V Rise Time tr Fall Time tf FR, CL, o FR, CL, o 10% 90% 90% 10% Setup Time ts Setup Time ts Delay Time td Hold Time th Hold Time th Delay Time td DIN MPF FR DIN MPF DOUT DIN +/– MPF +/– CL, i + CL, i – CL, i – CL, i + CL, i + CL, i + FR, i + DIN +/– DIN +/– DOUT +/– 25 10 -200 100 100 200 500 Setup Time ts Setup Time th Delay Time td Delay Time td DIN DIN DOUT FR DIN +/–1 CL, o – CL. o + CL, o + CL, o + DIN +/– DOUT +/– FR,o + 100 -150 500 150 Clock Width tc Clock Width tp Pulse Width tp Pulse Width tp CL, i CL, i CL, i CL, i CL +/– CL +/– CL +/– CL +/– CL +/– CL +/– CL –/+ CL –/+ 1830 1830 850 850 2080 2080 1100 1100 + = rising edge – = falling edge STU2071

DIGITAL INTERFACE DYNAMIC CHARACTERISTICS (continued) Master clock. Parameter Port from to Conditions C Min. Max. pF ns ns Rise Time tr Fall Time tf XTAL2 XTAL2 1.0V 3.5V 3.5V 1.0V Rise Time tr Fall Time tf CLS CLS 10% 90% 90% 10% Pulse Width CLS CLS +/– CLS –/+ 25 20 + = rising edge – = falling edge Setup Time ts Hold Time th Delay min. td Delay max. td DIN, FR, i +/– CL, i + CL, i + CL, i – CL, i + CL, i – 2.5V 2.5V 2.5V 2.5V CL, i + DIN, FR, i +/– DOUT +/– DOUT +/– 2.5V 2.5V 0.4 / 4V 4 / 0.4V Delay min. td (negative) Delay max. td CL, i + CL, i + 2.5V 2.5V FR, i + FR, i + 3.5V Setup Time ts Hold Time ts Delay max. td Delay min. td (negative) Delay max. td DIN, +/– CL, o + CL, o + CL, o + CL, o + 2.5V 2.5V 2.5V 2.5V 2.5V CL, o + DIN +/– DOUT +/– FR, o + FR, o + 2.5V 2.5V 4 / 0.4V 0.33V VDD - 0.66V Pulse Width tp Clock Width tc CL, o +/– CL, o +/– 2.5V 2.5V CL, o –/+ CL, o +/– 2.5V 2.5V Pulse Width tp Clock Width tc CLS, MXCL +/– CLS, MXCL +/– 2.5V 2.5V CL, o –/+ CL, o +/– 2.5V 2.5V STU2071

DIP28 PACKAGE MECHANICAL DATA DIM. mm inch a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 D 37.34 1.470 E 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F 14.1 0.555 I 4.445 0.175 L 3.3 0.130 STU2071

PLCC28 PACKAGE MECHANICAL DATA DIM. mm inch A 12.32 12.57 0.485 0.495 B 11.43 11.58 0.450 0.456 D 4.2 4.57 0.165 0.180 D1 2.29 3.04 0.090 0.120 D2 0.51 0.020 E 9.91 10.92 0.390 0.430 e 1.27 0.050 e3 7.62 0.300 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.24 0.049 M1 1.143 0.045 STU2071

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. STU2071