STP8NC50 STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 500V - 0.7Ω - 8A TO-220/TO-220FP/I2PAK PowerMesh™II MOSFET ■ TYPICAL R DS (on) = 0.7 Ω ■ EXTREMELY HIGH dv/dt CAPABILITY ■ 100% AVALANCHE TESTED ■ NEW HIGH VOLTAGE BENCHMARK ■ GATE CHARGE MINIMIZED

DESCRIPTION

The PowerMESH ™ II is the evolution of the first generation of MESH OVERLAY™. The layout re- finements introduced greatly improve the Ron*area figure of merit while keeping the device at the lead- ing edge for what concerns swithing speed, gate charge and ruggedness.

APPLICATIONS

■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SWITH MODE POWER SUPPLIES (SMPS) ■ DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVES ABSOLUTE MAXIMUM RATINGS (•)Pulse width limited by safe operating area (*) Limited only by maximum temperature allowed TYPE V DSS R DS(on) ID STP(B)8NC50(-1) 500 V < 0.85 Ω 8 A STP8NC50FP 500 V < 0.85 Ω 8 A Symbol Parameter Value Unit STP(B)8NC50(-1) STP8NC50FP VDS Drain-source Voltage (VGS = 0) 500 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 500 V VGS Gate- source Voltage ±30 V ID Drain Current (continuos) at TC = 25°C 8 8(*) A ID Drain Current (continuos) at TC = 100°C 5.4 5.4(*) A IDM (● ) Drain Current (pulsed) 32 32(*) A PTOT Total Dissipation at TC = 25°C 135 40 W Derating Factor 1.075 0.32 W/°C dv/dt (1) Peak Diode Recovery voltage slope 3 V/ns VISO Insulation Withstand Voltage (DC) - 2000 V Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (1)ISD ≤8A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS , Tj ≤ TJMAX. INTERNAL SCHEMATIC DIAGRAM TO-220 TO-220FP 1 2 3 I²PAK

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (1) DYNAMIC TO-220/I2PAK TO-220FP Rthj-case Thermal Resistance Junction-case Max 0.93 3.12 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 300 °C Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 8A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR , VDD = 50 V) 600 mJ Symbol Parameter Test Conditions Min. Typ. Max. Unit V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 500 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1µ A VDS = Max Rating, TC = 125 °C 50 µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ±30V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS , ID = 250µA 234V R DS(on) Static Drain-source On Resistance VGS = 10V, ID = 4 A 0.7 0.85 Ω ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, VGS =1 0 V 8A Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (1) Forward Transconductance VDS > ID(on) x RDS(on)max, ID =4 A 7.5 S C iss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 1050 pF C oss Output Capacitance 165 pF C rss Reverse Transfer Capacitance 25 pF

ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON SWITCHING OFF SOURCE DRAIN DIODE Note: 1.Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 250 V, ID = 4 A R G = 4.7Ω VGS = 10 V (see test circuit, Figure 3) 19 ns tr Rise Time 14 ns Q g Total Gate Charge VDD = 400V, ID = 8 A, VGS = 10V 36 46 nC Q gs Gate-Source Charge 5 nC Q gd Gate-Drain Charge 18.2 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) Off-voltage Rise Time VDD = 400V, ID = 8 A, R G =4 . 7Ω, VGS = 10V (see test circuit, Figure 5) 13 ns tf Fall Time 15 ns tc Cross-over Time 26 ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD Source-drain Current 8 A ISDM (2) Source-drain Current (pulsed) 32 A VSD (1) Forward On Voltage ISD = 8 A, VGS = 0 1.6 V trr Reverse Recovery Time ISD =8 A, di/dt = 100A/µs VDD = 100V, Tj = 150°C (see test circuit, Figure 5) 470 ns Q rr Reverse Recovery Charge 3.2 µC IRRM Reverse Recovery Current 13.7 A Safe Operating Area for TO-220/I2PAK Safe Operating Area for TO-220FP

Thermal Impedence for TO-220FPThermal Impedence for TO-220/I2PAK Output Characteristics Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temp. Source-drain Diode Forward Characteristics Normalized On Resistance vs Temperature

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 4: Gate Charge test Circuit Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit Fig. 3: Switching Times Test Circuit For Resistive Load

DIM. mm inch A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 L4 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 A C D E F G Dia. TO-220 MECHANICAL DATA P011C

DIM. mm inch A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 L3 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 A B D E H G ¯ F 123F2 TO-220FP MECHANICAL DATA

DIM. mm inch A 4.4 4.6 0.173 0.181 A1 2.49 2.69 0.098 0.106 B 0.7 0.93 0.027 0.036 B2 1.14 1.7 0.044 0.067 C 0.45 0.6 0.017 0.023 C2 1.23 1.36 0.048 0.053 D 8.95 9.35 0.352 0.368 e 2.4 2.7 0.094 0.106 E 10 10.4 0.393 0.409 L 13.1 13.6 0.515 0.531 L1 3.48 3.78 0.137 0.149 L2 1.27 1.4 0.050 0.055 L B D E A CA1 e P011P5/E TO-262 (I2PAK) MECHANICAL DATA

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