STGAP2GSN STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 20
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin description and connection diagram
- 3 Electrical data
- 3.1 Absolute maximum ratings
- 3.2 Recommended operating conditions
- 3.3 Thermal data
- 4 Electrical characteristics
- 5 Isolation
- 6 Functional description
- 6.1 Gate driving power supply and UVLO
- 6.2 Power-up, power-down and “safe state”
- 6.3 Control inputs
- 6.4 Watchdog
- 6.5 Thermal shutdown protection
- 6.6 Standby function
- 7 Typical application
- 8 Layout
- 8.1 Layout guidelines and considerations
- 8.2 Layout example
- 9 Testing and characterization information
- 10 Package information
- 10.1 SO-8 package information
- 10.2 SO-8 Suggested land pattern
- 11 Ordering information
Features
- High voltage rail up to 1700 V
- Driver current capability: 2 A / 3 A source/sink @25 °C, VH = 6 V
- dV/dt transient immunity ±100 V/ns
- Input-output propagation delay: 45 ns
- Separate sink and source option for easy gate driving configuration
- UVLO function optimized for GaN
- Gate driving voltage up to 15 V
- 3.3 V, 5 V TTL/CMOS inputs with hysteresis
- Temperature shut-down protection
- Standby function
- Narrow body SO-8 package Application
- Motor driver for home appliances, factory automation, industrial drives and fans.
- 600/1200 V inverters
- Wireless chargers
- UPS
- Power supply units
- DC-DC converters
- Power Factor Correction
Description
The STGAP2GSN is a single gate driver which provides isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 2 A source and 3 A sink capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The device integrates protection functions including thermal shutdown ans UVLO with optimized level for Enhancement-mode GaN FETs, which enables easy design high efficiency and reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross- conduction in case of controller malfunction. The input to output propagation delay results contained within 45 ns, providing high PWM control accuracy. A standby mode is available to reduce idle power consumption. Product status link STGAP2GSN Product label Isolated 3 A single gate driver for Enhancement mode GaN FETs STGAP2GSN Datasheet DS14151 - Rev 1 - December 2022 For further information contact your local STMicroelectronics sales office.
1 Block diagram
Figure 1. STGAP2GSN Block diagram
2 Pin description and connection diagram
Figure 2. STGAP2GSN Pin connection (top view) Table 1. Pin Description 1 VDD Power supply Driver logic supply voltage. 2 IN+ Logic input Driver logic input, active high. 3 IN- Logic input Driver logic input, active low. 4 GND Power supply Driver logic ground. 5 VH Power supply Gate driving positive voltage supply. 6 GON Analog output Source output. 7 GOFF Analog output Sink output. 8 GNDISO Power supply Gate driving Isolated ground.
3 Electrical data
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
3.2 Recommended operating conditions
Table 3. Recommended operating conditions
- Actual limit depends on power dissipation and T J
3.3 Thermal data
Table 4. Thermal data
4 Electrical characteristics
Testing conditions: TJ = 25 °C, VH = 6 V, VDD = 5 V unless otherwise specified. Typical values are intended at TJ = 25 °C. Table 5. Electrical characteristics
100 V/ns
Electrical characteristics
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit IQDDSBY VDD Standby VDD quiescent supply current Standby mode 40 65 µA Logic inputs Vil IN+, IN- Low-level logic threshold voltage 0.29·VDD 0.33·VDD 0.37·VDD V Vih IN+, IN- High-level logic threshold voltage 0.58·VDD 0.66·VDD 0.70·VDD V IINh IN+, IN- INx logic “1” input bias current INx = 5 V 33 50 70 µA IINl IN+, IN- INx logic “0” input bias current INx = GND 1 µA Rpd IN+, IN- Inputs pull-down resistors INx = 5 V 70 100 150 kΩ Driver buffer section IGON GON Source short-circuit current TJ = 25 °C 2 A VGONH GON Source output high-level voltage IGON = 100 mA VH-0.15 VH-0.12 V RGON GON Source RDS_ON IGON = 100 mA 1.25 1.5 Ω IGOFF GOFF Sink short-circuit current TJ = 25 °C 3 A VGOFFL GOFF Sink output low-level voltage IGOFF = 100 mA 60 80 mV RGOFF GOFF Sink RDS_ON IGOFF = 100 mA 0.6 0.8 Ω Overtemperature protection TSD Shutdown temperature (1) 170 °C Thys Temperature hysteresis (1) 20 °C Standby tSTBY Standby time See Section 6.6 200 280 500 µs tWUP Wake-up time See Section 6.6 10 20 35 µs tawake Wake-up delay See Section 6.6 1 2 3 µs tstbyfilt Standby filter See Section 6.6 200 280 800 ns 1. Characterization data, not tested in production STGAP2GSN
5 Isolation
Table 6. Isolation and safety-related specifications Table 7. Isolation characteristics
2720 VPEAKVPR = 2720 V, tm = 10 s
3200 VPEAKVPR = 3200 V, tm = 1 s
Table 8. Isolation voltage
6 Functional description
6.1 Gate driving power supply and UVLO
allows implementation of either unipolar or bipolar gate driving. Figure 3. Power supply configuration for unipolar and bipolar gate driving different values in parallel provides both local storage for impulsive current supply and high-frequency filtering. value in the range between 1 µF and 10 µF should be placed close to it.
6.2 Power-up, power-down and “safe state”
- GOFF = ON state;
- GON = High Impedance; Such conditions are established at the end of the power-up of the isolated side (VH < VHon) and maintained untilthe device power down phase (VH < VHoff), regardless of the value of the input pins. When driving GaN switches, it is recommended to provide a smooth voltage transient to the VH supply pin duringpower ON, and to limit the VH rising slope according to Table 3. The device integrates a structure which clamps the driver output to a voltage not higher than SafeClp when VH voltage is not high enough to actively turn the internal GOFF MOSFET on. If VH positive supply pin is floating or not supplied the GOFF pin is therefore clamped to a voltage smaller than SafeClp. If the supply voltage VDD of the control section of the device is not supplied, the output is put in safe state, and remains in such condition until the VDD voltage returns within operative conditions. After power-up of both isolated and low voltage sides, the device output state depends on the status of the input pins. STGAP2GSN Functional description DS14151 - Rev 1 page 8/20
6.3 Control inputs
Table 9. STGAP2GSN inputs truth table (applicable when device is not in UVLO or "safe state")
6.4 Watchdog
state” until communication link is properly established again.
6.5 Thermal shutdown protection
temperature is lower than TSD-Thys.
6.6 Standby function
IQHSBY respectively, and the output remains in “safe state” (the output is actively forced low). standby the inputs can change from the “standby” value. than tstbyfilt, and then in the “standby” value for a time t such that tWUP < t < tSTBY. inputs state after a time tawake. Figure 4. Standby state sequences
7 Typical application
avoid gate spikes while the driver is not yet powered on. bedesign with minimum loop inductance; some recommendations are provided in Section 8 . Figure 5. Typical application diagram - Positive gate driving Figure 6. Typical application diagram - Negative gate driving
8 Layout
8.1 Layout guidelines and considerations
- The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop area and inductance that might cause noise, ringing and, in the worst cases, induced turn-on. Gate loop inductance is crucial especially in GaN applications, where the VGSth is typically lower than other technologies. To further minimize gate loop inductance, it is recommended to use an inner plane layer to route the gate current return path (Kelvin-Source to GNDISO) flowing just underneath gate resistors. Adequate vias to connect to the plane shall be placed near driver and power switch source pins.
- When driving GaN switches the use of a 10 kΩ pull-down resistor between Gate and Kelvin-Source is also recommended. Such resistor should be placed close to the GaN pins.
- If the power transistor provides Kelvin-Source pin, it shall be used for gate driving while using the standard source pin(s) only for load current. The standard source pin(s) and the Kelvin-Source pin shall not be shorted together on PCB.
- If the power transistor does not provide Kelvin-Source pin, the net connecting the driver (GNDISO pin) to the power switch source pin shall use a dedicated trace/plane. The trace/plane shall start just on power switch source pin to minimize path sharing between gate current and load current.
- SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to each supply rail pins. A 100 nF capacitor must be placed between VDD and GND and between VH and GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to provide local storage for pulsed current, a second capacitor with a value between 1 µF and 10 µF should also be placed close to the supply pins.
- It is good practice to add filtering capacitors close to logic inputs of the device (IN+, IN-), particularly for fast switching or noisy applications.
- To avoid degradation of the isolation between the primary and secondary side of the driver, there should not be any trace or conductive area below the driver.
- If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal ground or power planes through multiple vias of adequate size. These vias should be located close to theIC pins to maximize thermal conductivity.
8.2 Layout example
Figure 7. Half-bridge suggested PCB layout
9 Testing and characterization information
Figure 8. Timings definition Figure 9. CMTI test circuit
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
10.1 SO-8 package information
Table 10. SO-8 package dimensions
- Dimension “D” does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
Package information
DS14151 - Rev 1 page 13/20
Figure 10. SO-8 mechanical data
10.2 SO-8 Suggested land pattern
Figure 11. SO-8 suggested land pattern
Table 11. Device summary
Ordering information
DS14151 - Rev 1 page 15/20
Revision history
Table 12. Document revision history 21-Dec-2022 1 Initial release.
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