STE12PS STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 44
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin description
- 3 Functional description
- 3.1 Operating modes
- 3.2 Detection and classification
- 3.2.1 Detection
- 3.2.2 Classification
- 3.2.3 Detection and classification FSM
- 3.3 Power ON
- 3.3.1 Under load (disconnection)
- 3.3.2 Short circuit, overload and overcurrent
- 3.3.3 Thermal monitoring
- 3.5 Logic interface
- 3.7 Smart-power mode
- 3.8 Power boost mode - 30W
- 3.8.1 Four channels in Auto mode
- 3.8.2 Six channels in Manual mode
- 3.9 Measurement and parameter codings
- 4 I2C interface
- 5 I2C slave protocol overview
- 5.1 Functional description
- 5.2 Error cases
- 5.3 Interrupts
- 5.4 I2C device address
- 5.5 Register addressing: write command format
- 5.6 Register addressing: read command format
- 5.7 Parallel monitoring interface
Features
■ PSE power control device ■ Supports up to 12 independent, 4(a)or 6(b) 30W “boosted” ports ■ Wide operating range: up to 90V ■ IEEE 802.3af compliant ■ Open circuit detection: AC and DC methods ■ Advanced power management algorithm ■ Current sensing with as low as 500m Ω, external, series resistors ■ No need for external FETs ■ In-rush current control ■ Short-circuit protection ■ Adaptable signature detection capability ■ On-chip 3.3V SMPS controller ■ Low-noise, 12-bit ADC ■ Standard I2C interface ■ Parallel monitor interface
Description
STE12PS is designed to supply power over multiple Ethernet channels in order to avoid different, individual power supply units for applications such as Web cams, IP Phones, Bluetooth access points and WLAN access points. The equipment that provides the power to the twisted pair cabling is referred to as Power Sourcing Equipment (PSE). The PSE’s main functions are: looking for links to a Powered Device (PD), classifying a PD, supplying power to the link, monitoring power on the link, and removing power from the link. The STE12PS is fully programmable, supporting the detection and powering of IEEE802.3af as well as legacy PDs. The flexibility of the STE12PS allows the user to select a suitable system configuration: up to 12 ports as well as 4 (a) or 6(b) “boosted” channels. If needed, the STE12PS can also efficiently manage cases or applications where a limited amount of power is available to the ports (smart-power capability) by means of integrated, power MOSFET devices. All operations are controlled via the I 2C bus also notifying externally some ports status condition via dedicated pins. Ethernet port isolation can be easily maintained thanks to an integrated 3.3V SMPS power source and by means of optocouplers. The STE12PS has five address selection inputs to choose up to 32 possible different addresses. Power can be provided to the PD using either spare lines of the Ethernet cable or using the data wires, as specified by IEEE 802.3af. a. In AUTO mode b. In MANUAL mode PBGA23x23 PBGA23x23 Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) STE12PS Contents
1 Block diagram
Figure 1. STE12PS functional block diagram Figure 2. Typical application diagram
2 Pin description
Table 1. Analog pins description ground to improve ADC noise performance. C = 180pF . CDETSLOW O Detection rise/fall time capacitor (up to 25nF). Tr/f can be set from 1ns to 4ms. square wave with VL as upper limit and (VL-10V) as lower limit voltage. SFTSTR O Switched Mode Power Supply (SMPS) soft start capacitor, 200nF . ACSn O It provides a 50Hz AC disconnection signal for port “n”, n = 1, … 12. SPn I Detection classification and AC disconnection sensing port “n”, n = 1, … 12. CLK_GEN1 I Crystal oscillator pin1 for high performance clock generation. CLK_GEN2 I Crystal oscillator pin2 for high performance clock generation. MCLK O Master clock output for multi device configuration. CLK_GEN3 I Low profile clock input pin or clock input pin in multi-device configuration.
Table 2. Digital pins description configuration register Global_cfg2, STATUS_FLAG_EN bit. Detection/Classification flag. ‘0’→ Detection/Classification procedure is not running. Thermal monitoring (x = 0,1).
A or B alternative configuration mode select. 12- or 4-boost channel select. x = 0,1. Not connected the device works as DC-DC converter controller. value must match the mounted Rsense resistors. I2C_ADDRx I This defines the device address for the I 2C interface. x = 0, … 4. SCLIN I Serial clock input pin for the I 2C interface. pin, this connection becomes the standard bi-directional serial data line (SDA). this connection becomes the standard bi-directional serial data line (SDA). SCAN_EN I Reserved. Preset to ‘0’. Table 2. Digital pins description (continued)
Table 3. Power and ground pins description
Obsolete Product(s) - Obsolete Product(s) STE12PS Functional description
3 Functional description
The STE12PS architecture provides a complete PSE interface and smart digital controller to efficiently manage the functions in a PoE system. All operations can be controlled through R/W registers via a standard I2C bus interface. The STE12PS is designed to control power delivery of up to 12 separate lines. This is performed by controlling 12 integrated, power MOS transistors connected to the low side of the line - monitoring the line voltage and sensing line current by means of external, series sensing resistors (one per port). Turning on a port means to switch the relative MOS transistor thus controlling the inrush current in order to rise the port voltage up to 48V (typical battery voltage) after a valid PD signature has been detected. The flexibility of the STE12PS allows the user to select a suitable system configuration: 12 "standard", 4 or 6 "boosted" 30W channels, by means of pins CH_NUMn. Also, one can select the type of architecture (Endpoint PSE/ Alternative A or Midspan PSE/Alternative B) for all channels via pin A_BN_SEL. Some typical applications for the STE12PS include
- Ethernet switches/routers
- Midspan power supplies
- IP-PBX
- WLAN access points
3.1 Operating modes
The digital controller can operate in one of five possible modes for all the channels, selectable through the Global Configuration registers: Stand-by, Auto, Semi Auto, Manual or Power Down. When the reset condition is removed, the controller defaults to Power Down mode if the AUTO_START pin is tied low; if AUTO_START is tied HIGH the mode is configured in AUTO. The mode can be changed only during a limited amount of time (100ms), after the reset is released, accessing the Global Configuration registers before the detection procedure is started, or placing the device in STAND-BY mode via the I 2C interface. The characteristics of the Five possible operating modes are described below:
- STAND-BY: the controller allows only the read write operations suitable for changing programmability. To enable this mode set the reset bit 1 of the REG0x05.
- AUTO: the controller autonomously performs detection, classification and Power ON command without the need of host commands. A subset of status flags stored in the channels monitor registers is reported externally through the Status Flag Notifies pins allowing operation without the presence of the host controller.
- SEMIAUTO: after a triggering command the controller autonomously performs detection and classification waiting a dedicated command from host processor for the power on. Based on the detection and classification results reported in the Channels Status registers, the host controller can decide to power on the selected channel. The disconnection of a channel is automatic as in the AUTO mode, unless disabled.
- MANUAL: any action is performed manually. The host controller has the responsibility to force any state transition in the FSM. Then based on the measures performed automatically by the ADC on several parameters, the host controller can decide to
- POWER DOWN: the controller is put in power down state. No actions are performed until the power down mode is removed. For all operating modes, except power-down and stand-by, the power ON/OFF condition of each channel can also be managed, directly, by the host processor or controller via a dedicated command. Moreover, the power removal procedure is performed automatically (also in MANUAL mode) when a fault event has been detected (AC/DC disconnection, overload or overcurrent); this behavior can be changed configuring appropriately some dedicated enable/disable bits of channels event registers. With Priority Management in AUTO mode and Smart-power management enabled, it is also possible to set different priorities for different channels. The STE12PS will probe channels starting from those with the highest priority . In case of a shortage of available power, it is also possible to disable powering of newly detected, lower priority ports until the highest detected ones are served.
3.2 Detection and classification
3.2.1 Detection
Figure 3. IEEE802.3af detection circuit Table 12: Electrical characteristics, parameter Tdetd. D1(one per port) is external. otherwise it is internally emulated.
– a port capacitance of less than 4µF . by changing Gdl and Gdh via the logic interface. signature resistance is greater than 500k Ω, then the two second wait is avoided.
3.2.2 Classification
smart-power management (if enabled). The detected class is then stored in the Channel Status registers. voltage in order to arrive at a true power measurement result. Table 4. PD power classification
4 Optional - Reserved Ithcl3 < I class < Ithcl4
Obsolete Product(s) - Obsolete Product(s) Functional description STE12PS
3.2.3 Detection and classification FSM
This FSM manages all operations related to the detection and classification procedures. For these two procedures, the following assumptions are made: 1. A channel is detected ONL Y if: a) the channel has not yet been detected, and Channel Detection has been enabled, and b) the Backoff Detection timer and Subsequent Attempt timer are NOT running (after a corresponding fault detection or failed signature). 2. A channel is classified ONL Y if: a) Channel Classification is enabled, and b) the previous related detection procedure has reported an Rgood/Ggood value (Auto and SemiAuto modes). Three general macro operations can be performed:
- STARTUP: the following operations are related to the startup procedure: – RESET: reset and initialize all digital aspects of the STE12PS, – WAIT_POWER_UP: wait 100ms for completion of the power-up procedure. During this period, the I 2C bus is active - allowing the host to initialize registers while the detection procedure is waiting to start. – DETECTION START: all setting-up needed to start operations is performed in this state. The first battery voltage sample is latched in a dedicated register.
- DETECTION: the following operations are related to the detection procedure for the channel selected: – Low voltage detection command (4V) is issued via registers; detection timer is started to execute the command for a duration of ½Tdet ms. – Wait for 5ms to acquire a stable measurement. – Sampled sensing current values are acquired via A/D converter. – The samples previously acquired are averaged and the resulting value, reported into the Channels Monitor register, is compared against programmed min/max values. If the sensing current is higher than maximum allowed value, the detection procedure is considered as having FAILED: backoff timer is started (Alternative B) and an alarm flag raised according to the Channel Status registers. – If the sensing current results lower than the minimum allowed value the detection procedure is continued: the alarm flag is raised in the Channel Status registers. – The described operations are repeated for the High-Voltage detection command (8V). – Signature Resistance is calculated: – If 2µsec < Gmeas < Glow or Ghigh < Gmeas, then backoff timer is started (Alternative B) and detection result failure is reported in the Channel Status registers. – Else, Glow < Gmeas < Ghigh and the result of a successful detection is reported in the Channel Status registers.
- CLASSIFICATION: The following operations are related to the classification procedure for the corresponding channel – If classification is not enabled, the default Class 0 is assigned. – High Voltage detection command (17V) is issued via registers; detection timer is started to execute the command for 15ms duration. – Wait for 5ms to acquire a stable measurement – Sampled sensing current values are acquired via A/D converter. – Average the previously acquired samples and report the resulting value in a dedicated register. The power class is identified and the result is reported in the Channel Status registers. – Channel is ready to be powered: if the smart-power algorithm is enabled (via the MISCELLANEOUS registers) the channel is powered only if the required power is within the remaining power budget; the channel can be powered regardless of the power-check availability via registers. If the power availability check has a positive result (or it hasn’t been performed), the channel is powered. Otherwise, it is rejected, and the alarm flag raised in the Channel Events register. The channel number is registered into a scheduler FIFO so that power will again be available when the channel is ready to be switched-on.
Figure 4. Detection and classification equivalent architecture
Obsolete Product(s) - Obsolete Product(s) Functional description STE12PS
3.3 Power ON
After the classification phase the port will be powered. Once activated, the power-on sequencer manages the channel’s activation requests received through the signature detection circuitry. For the incoming channel, activation requests are stored in the power-on sequencer and then serviced, one at a time, only when the previously activated channel leaves the current limiting condition that normally occurs during power on due to the capacitive part of the load. (see also smart-power mode and special issues) A port is turned-on by ramping-up the voltage and increasing the current limit to its upper limit. After a programmable time (T inrush), if the port has reached full voltage and is out of current limitation, it is marked as powered. The related port power bit and the power class bits are set according to the class in the logic interface bit stream. The active ports are continuously monitored in order to detect a fault condition such as Short Circuit, Disconnection or Excess Power (overload).
3.3.1 Under load (disconnection)
Detection of a disconnection, if enabled (default condition), can be performed via a DC and/or AC method - default is DC ⊕ AC (logical OR):
- DC method If this method is selected via the logic interface and if the port current drops under 7.5mA for more than 10ms, then the STE12PS will detect a DC disconnection. If this condition persist for Tmpdo ( Table 12), then power is removed and the port is marked as free, enabling a new detection.
- AC method If this method is selected via the logic interface, the STE12PS probes the channels via coupling capacitors and detects when the AC load impedance, Zac, exceeds the maximum, 100kΩ limit for a time longer than 20ms. In this case, the PSE will detect an AC disconnection. If this condition persist for a time Tmpdo (Table 12), power is removed and the port is marked as free, enabling a new detection. Disconnection modes are as following: Disabled, DC method only, AC method only, both AC and DC (combined in OR ⊕ logic or in AND ⊗ logic).
Figure 5. Power ON and monitoring
3.3.2 Short circuit, overload and overcurrent
Table 12: Electrical characteristics, parameter Tshort). the Channel Event registers. longer than 65ms, typ. (see Table 12: Electrical characteristics, parameter Tovld). according to the power class. When the above conditions are met, the port is disconnected, and the fault bit is set HIGH.
Obsolete Product(s) - Obsolete Product(s) Functional description STE12PS Monitor overload FSM This FSM manages all operations related to monitoring an overload event. All operations described below are related to channels currently powered.
- STARTUP: the following operations are related to a startup procedure: – START: channel to be monitored is selected.
- POWER MEASUREMENT: the following operations are related to a power measurement procedure – SAMPLE Imeas: the current measurement is sampled and the next powered channel is prepared for the next monitor procedure. – MEASURE Power: the power is measured and its value is compared against the required Power class. – START MONITOR OVERLOAD: if the measured power exceeds the required power class the Tovld timer and the averaging process are started. – COUNTER RESET: T ovld timer is reset if the measured power doesn’t exceed the required
- POWER REMOVAL: the following operations are related to a power removal procedure: – COUNTER CHECK: all T ovld timers are checked, and those that have expired are identified. – POWER REMOVAL: all the channels whose timers have expired and whose average power exceeds the maximum are switched OFF through the POWER_EN(n) pins. – ALARM SET: for all the channels whose timers have expired, a corresponding alarm flag is raised in the Channel Event registers, and the related Ted timer is started.
Obsolete Product(s) - Obsolete Product(s) STE12PS Functional description Monitor overcurrent FSM This particular FSM manages all operations related to procedures that are able to monitor an overcurrent event. All operations described below are related to channels currently powered.
- STARTUP: – START: the channel to be monitored is selected.
- VOLT AGE BATTERY: – SAMPLE V bat: every 12 channels cycle the Vbat measurement is executed.
- OVERCURRENT CHECK: the following operations are related to an overcurrent check meas CHECK: if Imeas>Ilim the I_LIM_FLAG is raised and the next powered channel is prepared for the next monitor procedure. – START MONITOR: the T lim counter is started if I_LIM_FLAG is found asserted. – COUNTER RESET: if I_LIM_FLAG is found de-asserted T lim counter is reset taking into account that glitches of duration less than 10ms are filtered.
- POWER REMOVAL: the following operations are related to a power removal operation: – COUNTER CHECK: all the T lim timers are checked and those expired are identified. – POWER REMOVAL: all the channels whose timer is expired are switched OFF . – ALARM SET: for all the channels whose timers are expired a corresponding alarm flag is raised in the FAULT_EVENT_CHn register and the related Ted timer is started.
3.3.3 Thermal monitoring
The procedures performed by the digital controller are impacted by the thermal monitoring data indicating the measured temperature. Its behavior is based on a three-level control system 1. When the chip's internal temperature reaches 110°C, only the channels already powered will be serviced. Possible new ones, will be rejected, redetected and eventually processed when the internal temperature cools down to 100°C. This behavior can be disabled setting the proper bit register. 2. A second temperature threshold is set at 130°C. When this value is reached, the channels that are in current limiting or inrush condition are immediately switched OFF , and their reactivation, subject to positive redetection, will only be possible when the chip's internal temperature has cooled down to 100°C. This behavior can be disabled by setting the proper bit register. 3. The third temperature threshold is set at 150°C. When this temperature is reached, all activated channels will be immediately switched OFF , and their reactivation, subject to positive redetection, will only be possible when the chip's internal temperature has decreased to 100°C. This behavior cannot be disabled.
Obsolete Product(s) - Obsolete Product(s) Functional description STE12PS 3.4 Internal 3.3V/10V generator The STE12PS can be configured either as 3.3V and 10V generator or load by means of the S/U control input. In this manner, the need for extra, low-voltage batteries is avoided, greatly simplifying the system design. If S/U is left open, the device will operate as an SMPS controller. With the SMPS configured at 3.3V, the device can be used to power up a “1Amp” load with high efficiency voltage conversion. Figure 6 on page 19 shows a typical DC-DC, buck converter configuration for the 3.3V supply. The 10V supply is generated by means of an internal, linear regulator. The 3.3V supply can source up to 1A. In Figure 7, use of a small transformer for the 10V supply can save up to 0.3W for each powered device. Both the 3.3V and 10V supplies can power others devices. Figure 8 depicts a typical application with an external supply.
3.5 Logic interface
The STE12PS can operate autonomously - notifying, externally, ports status via dedicated pins (Parallel Monitor Interface) - or it can be controlled as a slave device via the I interface by a host processor. In the latter case, the host can perform system configurations, monitor status conditions and assert alarm flags making it possible to drive, manually, different operations for detection, classification and monitoring.
Figure 6. Simple SMPS
Figure 7. Advanced SMPS
Figure 8. With external power supplies
3.7 Smart-power mode
noise rejection as well as minimize 50 to 60Hz interference.
3.8 Power boost mode - 30W
3.8.1 Four channels in Auto mode
Channels in boost mode behave as master or slave according to the above table. performed with 3 classification impulses (total classification time 70ms).
3.8.2 Six channels in Manual mode
Figure 9 and according to the following table. Table 5. Power boost mode: master/slave channel parallelism Table 6. Power boost mode: master/slave channel parallelism
3.9 Measurement and parameter codings
Table 7. Measurement and parameter codings
- Rdet, Rdl and Rdh are the alternative to Gdet, Gdl and Gdh wh ich are the default. If Rdet measures more than 500kohms,
the “open-circuit” flag is raised, that is set HIGH.
4 I2C interface
SMPS power source and using optocouplers on I2C bus.(Figure 13). Figure 13. Isolated ethernet power system using optocouplers for I 2C interface
Obsolete Product(s) - Obsolete Product(s) STE12PS I2C slave protocol overview
5 I 2C slave protocol overview
The interface is capable of recognizing its own address (7 bit). Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the start condition contains the device address. A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must pull LOW the SDA line to acknowledge the transfer. The speed of the I2C interface is fixed at Fast I2C, that is, 100 to 400kHz.
5.1 Functional description
As soon as a start condition is detected, the address is received from the SDA line and sent to a shift register; then it is compared with the internal address that is composed by the five pins for the five LSB and by a hardwired value equal to “01” for the other two bits. In case of address mismatch the interface ignores it and waits for another Start condition. If address is matched the interface generates an acknowledge pulse. Following the address reception, POE digital controller receives bytes from the SDA line into the data register via an internal shift register or sends bytes from the data register to the SDA line through the internal shift register. After each byte reception an acknowledge pulse is generated by the controller. A Stop condition generated by the host processor, after the last data byte is transferred, closes the communication.
5.2 Error cases
An error state is generated when Stop or Start conditions are detected during a byte transfer. If it is a Stop then the interface discards the data, releases the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus.
5.3 Interrupts
Irq register bits indicate which signals can generate an interrupt. The register is read only and to clear the interrupt bits the corresponding source event has to be cleared. The logic OR condition of the interrupt bits causes the INTN pin assertion. The INTN assertion can be masked via the interrupt mask register Irq_mask.
5.4 I 2C device address
The device is required to have an I²C address of: 01xxxxxb(A6 down to A0). Pins I2C_ADDR[4:0] can be used to set the lower I2C address bits.
5.5 Register addressing: write command format
I2C write command format is shown in Figure 14. Figure 14. Write command
- S - I2C start condition
- P - I2C stop condition
- ACK – acknowledge
- NACK - not acknowledge
- R/W - read/write The device address is the value specified in I2C device address. The register address is an eight-bit value that is written into an internal Index Register. Each time a byte of data is written to, or read from the POE controller, the Index Register increments by one. If the initial value written to the Index Register is K, then the byte immediately following the Register Address byte is written to the register with an address of K. The next byte is written to the register with the address of K+1, and so on. An I 2C write command can contain from 0 to 255 write data bytes. Write commands to an unknown register location are ignored by the interface. As shown in Figure 14, bits are ordered with the most significant bit first. S 6 54 32 1 0 Device address W R/W ACK Register address (K) ACK 6543210 7 6 54 32 1 0 Write data ACK Write data (K + 1) ACK 6543210 7 6 54 32 1 0 Write data (K + N) P ACK
5.6 Register addressing: read command format
The general format of the read command is shown in Figure 15. address to the Index Register again. A read command can contain from 0 to 255 bytes. Figure 15. Read command
Obsolete Product(s) - Obsolete Product(s) I2C slave protocol overview STE12PS
5.7 Parallel monitoring interface
In order to monitor the status of the different ports without the I2C register addressing, a simple, output status interface has been implemented. This digital interface is comprised of 9 output pins: CH_SEL[3:0], POK, OVLD, OVCUR, AC_DC_DISCON and DET_CLASS. Bits CH_SEL[3:0] indicate the channel status flags (POK,..., DET_CLASS) that are currently notified, externally. CH_SEL is incremented every 60MCLK clock cycles. POK stands for Power OK. When HIGH, it indicates that the channel is currently powered-on in normal condition. OVLD stands for OverLoad and indicates a faulty condition due to abnormal power dissipation (more than Pclass) of a powered channel. OVCUR stands for OverCurrent, and it highlights a channel whose current has reached the power-on current limit of 425mA (typ. value). Bit AC_DC_DISCON goes HIGH when a powered channel fails in providing a correct MPS (maintain power signature). This typically happens when a PD is disconnected from the line. DET_CLASS indicates a situation where a channel is not yet powered and whose “signature” is currently being probed. Status flag notification is enabled by bit STATUS_FLAG_EN of the configuration register Global_cfg2. By default this bit is HIGH, that is, enabled. This information is particularly useful in simple applications without a microprocessor or for testing purposes. Another use is to easily build-up an LED graphical interface showing runtime status of the various channels.
6 Electrical specifications and timings
Table 8. Absolute maximum ratings Table 9. Operating range Table 10. Thermal data Table 11. ESD
Table 11. ESD (continued) Table 12. Electrical characteristics Tdbo Back-off time (midspan mode) 2 sec.
Table 12. Electrical characteristics (continued)
- See also timer programmability
7 Ball coordinates
Figure 16. Balls top view layout (as viewed through package)
4 A_BN_SEL AUTO_ST
2 NC P12_1-2
2 FSRp10_3 FSRp11_1-
2 FSRp11_3S S Rp11 AC S11 F SRp3_3 FSRp3_1-2 AC S3 NC SP7
Table 13. Pad coordinates
1 A CH_SEL0 2 P NC
1 AA P9_3 3 M FSRp5_3
1 AB SP9 3 N ACS1
1 B CH_SEL2 2 R NC
1 C vdd10 2 T NC
1 D SMPSGND 2 U NC
1 G RSENSE 2 Y NC
1 J SMPSVL 2 AB NC
1 L NC 3 B AC_DC_DISCON
1 M P5_1-2 3 C V3_3
1 T P1_1-2 3 G SenseProgPin0
1 U P1_3 3 H SenseProgPin1
1 V SP1 3 J ACS5
1 W NC 3 K SSRp5
1 Y P9_1-2 3 L FSRp5_1-2
2 A CH_SEL1 3 P SSRp1
2 B CH_SEL3 3 R FSRp1_1-2
2 C V10 3 T FSRp1_3
2 F NC 3 W FSRp9_1-2
2 G NC 3 Y FSRp9_3
2 J NC 3 AB P6_1-2
2 L NC 4 B DET_CLASS
4 AA NC 9 B TEST_MODE0
4 AB P6_3 9 C AUTO_START
4 E gnd 7 B I2C_ADDR2
4 F gnd 7 C I2C_ADDR4
4 G DGND 7 D CLK_GEN2
4 H DGND 7 W GND
4 L GND 7 AB P2_1-2
4 M GND 8 A CH_NUM1
4 N GND 8 B TEST_MODE1
4 P GND 8 C A_BN_SEL
4 T GND 8 W SSRp2
4 U GND 8 Y FSRp2_1-2
4 W GND 8 AB P2_3
4 Y ACS6 9 A CH_NUM0
5 AB SP6 9 W GND
5 B I2C_ADDR0 9 J gnd
5 C OVCUR 9 K GND
5 D gnd 9 L GND
5 W SSRp6 9 M GND
5 Y FSRp6_1-2 9 N GND
6 A SDAIN 9 Y FSRp2_3
6 B I2C_ADDR1 9 AA NC
6 C I2C_ADDR3 9 AB SP2
6 D CLK_GEN1 10 A AGND
6 Y FSRp6_3 10 C SCAN_EN
Table 13. Pad coordinates (continued)
10 AA NC 13 K GND
10 AB NC 13 L GND
10 L GND 12 AB P10_3
10 M GND 13 A Vbatref
10 N GND 13 B Vbatmon
10 P GND 13 C AGND
10 W GND 13 D GND
10 Y ACS10 13 J GND
11 A IDET_HVLV 13 M GND
11 AA NC 14 K GND
11 AB P10_1-2 14 L GND
11 B AGND 13 N GND
11 C AGND 13 P GND
11 D gnd 13 W GND
11 J gnd 13 Y FSRp10_3
11 K GND 13 AA NC
11 L GND 13 AB SP10
11 M GND 14 A AGND
11 N GND 14 B AGND
11 P GND 14 C AGND
11 W GND 14 D gnde
11 Y SSRp10 14 J gnd
12 A I_REF 14 M GND
12 AA NC 15 Y FSRp11_3
12 B IMON_HVLV 14 N GND
12 C AGND 14 P GND
12 D gnd 14 W GND
12 J gnd 14 Y FSRp11_1-2
12 K GND 14 AA NC
12 L GND 14 AB NC
12 M GND 15 A RESETN
12 N GND 15 B vdde
12 P GND 15 C vdde
12 W GND 15 D gnde
12 Y FSRp10_1-2 15 W GND
15 AA NC 19 K SSRp4
15 AB SP11 19 L GND
16 A PORn 19 M GND
16 AA NC 19 V GND
16 AB P11_3 19 W SSRp3
16 B vdde 19 N GND
16 C gnde 19 P GND
16 D vdd 19 R GND
16 W GND 19 T GND
16 Y SSRp11 19 U GND
17 A vdde 19 Y FSRp3_1-2
17 AA NC 20 D POWER_EN9
17 AB P11_1-2 20 E CdetSlow
17 B gnde 19 AA NC
17 C vdd 19 AB SP3
17 D vdd 20 A POWER_EN0
17 W GND 20 B POWER_EN3
17 Y ACS11 20 C POWER_EN6
18 A gnde 20 F RMONF
18 AA NC 20 M ACS12
18 AB NC 20 N SSRp12
18 B vdd 20 G FSRp8_1-2
18 C gnd 20 H FSRp8_3
18 D gnd 20 J ACS4
18 W GND 20 K FSRp4_1-2
18 Y FSRp3_3 20 L FSRp4_3
19 A vdd 20 P FSRp12_1-2
19 B gnd 20 R FSRp12_3
19 C gnd 20 T ACS7
19 D gnd 20 U SSRp7
19 E gnd 20 V FSRp7_1-2
19 F RMONS 20 W FSRp7_3
19 G HQgnd 20 Y ACS3
19 H ACS8 20 AA NC
19 J SSRp8 20 AB P3_3
21 A POWER_EN1 22 R P12_3
21 AB P3_1-2 22 T SP12
21 B POWER_EN4 22 U NC
21 C POWER_EN7 22 V P7_1-2
21 D POWER_EN10 22 W P7_3
21 E NC 22 Y SP7
21 F NC 22 AA NC
21 G NC 22 AB NC
21 H NC
21 J NC
21 K NC
21 L NC
21 M NC
21 N NC
21 P NC
21 R NC
21 T NC
21 U NC
21 V NC
21 W NC
21 Y NC
22 A POWER_EN2
22 B POWER_EN5
22 C POWER_EN8
22 D POWER_EN11
22 E NC
22 F P8_1-2
22 G P8_3
22 H SP8
22 J NC
22 K P4_1-2
22 L P4_3
22 M SP4
22 N NC
22 P P12_1-2
8 Package information - mechanical data
trademark. ECOPACK specifications are available at: www.st.com. Note: 1 Maximum mounted height, dimension A, is 1.77mm based on a 0.35mm ball pad diameter. Solder paste is 0.15mm thick and 0.35mm in diameter. 2 PBGA stands for Plastic Ball Grid Array.
3 The terminal A1 corner must be on the top surface by using a corner chamfer, ink,
metallized markings or some other feature of the package body or internal heatslug.
4 A distinguishing feature is allowed on the bottom surface of the package to identify terminal
5 Exact shape of each corner is optional. Table 14. Package dimensions
Figure 17. PBGA23x23 package mechanical drawing
9 Ordering information
Table 15. Order codes Table 16. Document revision history of four previously (cover page and Section 3.8). 17-Aug-2007 3 Added Table 11: ESD in Chapter 6.