ST8024T SITRONIX | Alldatasheet
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Technical content
Note: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change. Version 0.12 2008/01/24 P r e l i m i n a r y
Preliminary Ver 0.12 Page 2/26 2008/01/24 1. FEATURES Number of LCD drive outputs: 240 Supply voltage for LCD drive: +15.0 to +30.0 V Supply voltage for the logic system: +2.5 to +5.5 V Low power consumption Low output impedance (Segment mode) Shift clock frequency 15MHz(MAX.): VDD = +5.0 ± 0.5V 12MHz(MAX.): VDD = +3.0 to + 4.5V 8MHz(MAX.): VDD = +2.5 to + 3.0V Adopts a data bus system 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data Line latch circuits are reset when /DISPOFF active (Common mode) Shift clock frequency: 4 MHz (MAX.) Built-in 240-bit bi-directional shift register (divisible into 120 bits x 2) Available in a single mode (240-bit shift register) or in a dual mode (120-bit shift register x 2) Y 1->Y240 Single mode Y240->Y1 Single mode Y1->Yl20, Y121->Y240 Dual mode Y240->Y121, Yl20->Y1 Dual mode The above 4 shift directions are pin-selectable Shift register circuits are reset when /DISPOFF active 2. DESCRIPTION The ST8024T is a 240-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work stations. The ST8024T is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution LCD.
Preliminary Ver 0.12 Page 3/26 2008/01/24 3. BLOCK DIAGRAM 4. FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK FUNCTION Active Control In case of segment mode, controls the selection or non-selection of the chip. Following an LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. SP Conversion & Data Control In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time. Data Latch Control In case of segment mode, selects the state of the data latch which reads in the data bus s ignals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. Data Latch In case of segment mode, latches the data on the data bus. The latch state of each LCD drive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. Line Latch/ Shift Register In case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. Level Shifter The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the driver block. 4-Level Driver Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 levels (V0, V12, V43 or Vss) based on the S/C, FR and /DISPOFF signals. Control Logic Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip is non-selected. In case of common mode, controls the direction of data shift. 240-BIT 4-LEVEL DRIVER 240-BIT LEVEL SHIFTER 240-BIT LINE LATCH/SHIFT REGISTER DATA CONTROL SP CONVERSION & DATA CONTROL (4 to 8 or 8 to 8) CONTROL LOGIC ACTIVE CONTROL LEVEL SHIFTER
8 BIT
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 VDD VSS VSS V43L V12L V0L Y240Y239Y2Y1VSSV43RV12RV0R FR /DISPOFF EIO1 EIO2 LP XCK L/R MD S/C 16 16 16 240 240
Preliminary Ver 0.12 Page 4/26 2008/01/24 5. PIN DESCRIPTION (TCP TYPE) PS : Detail size see TCP drawing data SYMBOL I/O DESCRIPTION Y1-Y240 O LCD drive output V0L, V0R P Power supply for LCD drive V12L, V12R P Power supply for LCD drive V43L, V43R P Power supply for LCD drive L/R I Display data shift direction selection VDD P Power supply for logic system (+2.5 to +5.5 V) S/C I Segment mode/common mode selection EIO2, EIO1 I/O Input/output for chip selection at segment mode S hift data input/output for shift register at common mode DI0-DI6 I Display data input at segment mode DI7 I Display data input at segment mode/Dual mode data input at common mode XCK I Clock input for taking display data at segment mode /DISPOFF I Control input for output of non-select level LP I Latch pulse input for display data at segment mode/ Shift clock input for shift register at common mode FR I AC-converting signal input for LCD drive waveform MD I 4 or 8 bits mode selection input VSS P Ground (0 V) TEST1,TEST2 I C onnect to GND or floating
Preliminary Ver 0.12 Page 7/26 2008/01/24 7. FUNCTIONAL DESCRIPTION
7.1 Pin Functions
(Segment mode) SYMBOL FUNCTION VDD Logic system power supply pin, Connected to +2.5 to +5.5 V. GND Ground pin LGND Logic ground pin Do not short LGND with GND and Vss by ITO on LCD panel Connect it to GND on PCB or FPC. VSS Connect to GND by ITO on LCD panel. V0L, V0R V12L, V12R V43L, V43R Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that V SS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin DI7-DI0 Input pins for display data In 4-bit parallel mode, DI3-DI0 are the display data input pins, and DI7-DI4 must be connected to LGND or VDD . In 8-bit parallel mode, All DI7-Dl0 pins are the display data input pins. Refer to section 7.2.2. XCK Clock input pin for taking display data Data is read at the falling edge of the clock pulse. LP Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. L/R Input pin for selecting the reading direction of display data When set to LGND level "L", data is read sequentially from Y240 to Y1. When set to VDD level "H", data is read sequentially from Y1 to Y240. Refer to section 7.2.2. /DISPOFF Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and contro ls the LCD drive circuit. When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level Vss. When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is canceled, the driver outputs non-select level (V 12 or V43), then outputs the contents of the data latch at the next falling edge of the LP . At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. FR AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. MD Mode selection pin When set to LGND level "L", 8-bit parallel input mode is set. When set to VDD level "H", 4-bit parallel input mode is set. Refer to section 7.2.2. S/C Segment mode/common mode selection pin When set to VDD level "H", segment mode is set. ElO1, EIO2 Input/output pins for chip selection When L/R input is at LGND level "L", ElO1 is set for output, and EIO2 is set for input. When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output.
Preliminary Ver 0.12 Page 8/26 2008/01/24 During output, set to "H" while LP • XCK is "H" and after 240 bits of data have been read, set to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 240 bits of data have been read. Y1 -Y240 LCD drive output pins Corresponding directly to each bit of the data latch, one level (V0, V12, V43, or VSS ) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. (Common mode) SYMBOL FUNCTION VDD Logic system power supply pin, connected to +2.5 to +5.5 V. GND Ground pin LGND Logic ground pin Do not short LGND with GND and Vss by ITO on LCD panel Connect it to GND on PCB or FPC. VSS Connect to GND by ITO on LCD panel. V0L, V0R V12L, V12R V43L, V43R Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. ElO1 Shift data input/output pin for bi-directional shift register Output pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H". When L/R = H, ElO1 is used as input pin, it will be pulled down. When L/R = L, ElO1 is used as output pin, it won't be pulled down. Refer to section 7.2.2. EIO2 Shift data input/output pin for bi-directional shift register Input pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H". When L/R = L, EIO2 is used as input pin, it will be pulled down. When L/R = H, EIO2 is used as output pin, it won't be pulled down. Refer to section 7.2.2. LP Shift clock pulse input pin for bi-directional shift register Data is shifted at the falling edge of the clock pulse. L/R Input pin for selecting the shift direction of bi-directional shift register Data is shifted from Y240 to Y1 when set to LGND level "L", and data is shifted from Y1 to Y240 when set to VDD level "H". Refer to section 7.2.2. /DISPOFF Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level LGND. W hen set to "L”, the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP . At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. FR AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. MD Mode selection pin When set to LGND level "L", single mode operation is selected; when set to VDD level
Preliminary Ver 0.12 Page 9/26 2008/01/24 "H" dual mode operation is selected. Refer to section 7.2.2. DI7 Dual mode data input pin According to the data shift direction of the data shift register, data can be input starting from the 121st bit. When the chip is used in dual mode, DI 7 will be pulled down. When the chip is used in single mode, DI7 won't be pulled down. Refer to section 7.2.2. S/C Segment mode/common mode selection pin When set to LGND level "L", common mode is set. DI6-DI0 Not used Connect DI6-DI0 to LGND or VDD , avoiding floating. XCK Not used XCK is pulled down in common mode, so connect to LGND or open. Y1 -Y240 LCD drive output pins Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS ) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
7.2 Functional Operations
7.2.1 Truth table
(Segment Mode) FR LATCH DATA /D ISPOFF LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240) L L H V43 L H H VSS H L H V12 H H H V0 X X L VSS (Common Mode) FR LATCH DATA /D ISPOFF LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240) L L H V43 L H H V0 H L H V12 H H H VSS X X L VSS NOTES: VSS < V43 < V12 < V0 L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage which is assigned by specification for each power pin.
Preliminary Ver 0.12 Page 10/26 2008/01/24
7.2.2 Relationship between the display data and LCD drive output Pins
(Segment Mode) (a) 4-bit Parallel Input Mode NUMBER OF CLOCKSMD L/R EIO1 EI02 DATA INPUT 60 CLOCK 59 CLOCK 58 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK DI0 Y1 Y5 Y9 … Y229 Y233 Y237 Dl1 Y2 Y6 Y10 … Y230 Y234 Y238 DI2 Y3 Y7 Y11 … Y231 Y235 Y239H L Output Input DI3 Y4 Y8 Y12 … Y232 Y236 Y240 DI0 Y240 Y236 Y232 … Y12 Y8 Y4 Dl1 Y239 Y235 Y231 … Y11 Y7 Y3 DI2 Y238 Y234 Y230 … Y10 Y6 Y2H H Input Output DI3 Y237 Y233 Y229 … Y9 Y5 Y1 (b) 8-bit Parallel Input Mode NUMBER OF CLOCKSMD L/R EIO1 EI02 DATA INPUT 30 CLOCK 29 CLOCK 28 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK DI0 Y1 Y9 Y17 … Y217 Y225 Y233 Dl1 Y2 Y10 Y18 … Y218 Y226 Y234 DI2 Y3 Y11 Y19 … Y219 Y227 Y235 DI3 Y4 Y12 Y20 … Y220 Y228 Y236 DI4 Y5 Y13 Y21 Y221 Y229 Y237 DI5 Y6 Y14 Y22 Y222 Y230 Y238 DI6 Y7 Y15 Y23 Y223 Y 231 Y239 L L Output Input DI7 Y8 Y16 Y24 Y224 Y232 Y240 DI0 Y240 Y232 Y224 … Y24 Y16 Y8 Dl1 Y239 Y231 Y223 … Y23 Y15 Y7 DI2 Y238 Y230 Y222 … Y22 Y14 Y6 DI3 Y237 Y229 Y221 … Y21 Y13 Y5 DI4 Y236 Y228 Y220 … Y20 Y12 Y4 Dl5 Y235 Y227 Y219 … Y19 Y11 Y3 DI6 Y234 Y226 Y218 … Y18 Y10 Y2 L H Input Output DI7 Y233 Y225 Y217 … Y17 Y9 Y1 (Common Mode) MD L/R DATA TRANSFER DIRECTION EIO1 EI02 DI7 L Y240 Y1 Output Input XL (Single) H Y1 Y240 Input Output X Y240 Y121L Y120 Y1 Output Input Input Y1 Y120 H (Dual) H Y121 Y240 Input Output Input NOTES: L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care "Don't care" should be fixed to "H" or "L", avoiding floating.
Preliminary Ver 0.12 Page 11/26 2008/01/24
7.2.3 Connection examples of plural segment drivers
(a) When L/R = “L” Y240 Y240 Y240Y1 Y1Y1 EIO2 EIO2 EIO2EIO1 EIO1EIO1 XCK LP MD FR DI7-DI0 XCK LP MD FR DI7-DI0 XCK LP MD FR DI7-DI0 XCK LP MD FR DI7-DI0 L/R L/RL/R LGND Top data Last data Data flow (b) When L/R = “H” Y240 Y240 Y240Y1 Y1Y1 EIO2 EIO2 EIO2EIO1 EIO1EIO1 XCK LP MD FR DI7-DI0 XCK LP MD FR DI7-DI0 L/R L/RL/R VDD Top data Last data Data flow XCK LP MD FR DI 7-DI0 XCK LP MD FR DI 7-DI0 LGND
Preliminary Ver 0.12 Page 12/26 2008/01/24
7.2.4 Timing chart of 4-device cascade connection of segment drivers
n* n* n* n* n* 11111 22222 device A device B device C device D TOP DATA LAST DATA *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode EO (device C) EO (device B) EO (device A) EI (device A) DI7 - DI0 XCK LP FR
Preliminary Ver 0.12 Page 13/26 2008/01/24
7.2.5 Connection examples for plural common drivers
(a) Single Mode (L/R = ”L”) (b) Single Mode (L/R = “H”) Y240 Y240 Y240Y1 Y1Y1 EIO2 EIO2 EIO2EIO1 EIO1EIO1 FR L/R /DISPOFF MD FR DI7 LP /DISPOFF LGND (V DD ) First Last LP LGND V DD FLM L/R /DISPOFF MD FR DI7 LP L/R /DISPOFF MD FR DI7 LP Y240 Y240 Y240Y1 Y1Y1 EIO2 EIO2 EIO2EIO1 EIO1EIO1 LP LGND FR /DISPOFF L/R LP MD FR LGND (VDD ) First Last FLM /DISPOFF L/R LP MD FR DI7 /DISPOFF L/R LP MD FR DI /DISPOFF DI7
Preliminary Ver 0.12 Page 14/26 2008/01/24 (c) Dual Mode (L/R = “L”) Y240 Y240 Y240Y1 Y1Y1 EIO2 EIO2 EIO2EIO1 EIO1EIO1 LP LGND FR /DISPOFF L/R LP MD FR DI7 LGND (V DD ) First Last 2 FLM1 /DISPOFF L/R LP MD FR DI7 /DISPOFF L/R LP MD FR DI7 /DISPOFF First 2Last 1 Y121 Y120 FLM2 VDD (d) Dual mode (L/R = “H”) Y240 Y240 Y240Y1 Y1Y1 EIO2 EIO2 EIO2EIO1 EIO1EIO1 FR L/R /DISPOFF MD FR DI7 LP /DISPOFF LGND (VDD ) First 1 Last 2 LP LGND VDD FLM1 L/R /DISPOFF MD FR DI7 LP L/R /DISPOFF MD FR DI7 LP Last 1 First 2 Y120 Y121 FLM2
Preliminary Ver 0.12 Page 15/26 2008/01/24 8. PRECAUTIONS Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. The details are as follows, When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power It is advisable to connect the serial resistor (50 to 100 ) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level LGND on /DISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here VDD LGND VDD LGND GND VDD /DISPOFF
Preliminary Ver 0.12 Page 16/26 2008/01/24 9. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL APPLICABLE PINS R ATING UNIT NOTE Supply voltage (1) V DD VDD -0.3 to +7.0 V V0 V0L, V0R -0.3 to +33.0 V V12 V12L, V12R -0.3 to V0 + 0.3 V V43 V43L, V43R -0.3 to V0 + 0.3 VSupply voltage (2) VSS VSS -0.3 to V0 + 0.3 V Input voltage VI DI7-DI0, XCK, LP , L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF -0.3 to VDD + 0.3 V 1,2 Storage temperature TSTG -45 to +125 °C NOTES: 1. TA = +25 °C 2. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V). 10. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL APPLICABLE PINS MIN. T YP . MAX. UNIT NOTE Supply voltage (1) VDD VDD +2.5 +5.5 V Supply voltage (2) V0 V0L, V0R +15.0 +30.0 V 1 , 2 Operating temperature T OPR -25 +70 °C NOTES: 1. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V). 2. Ensure that voltages are set such that VSS < V43 < Vl2 < V0.
Preliminary Ver 0.12 Page 17/26 2008/01/24 11. ELECTRICAL CHARACTERISTICS
11.1 DC Characteristics
(Segment Mode) (LGND=V SS =GND = 0V, VDD = +2.5 ~ +5.5 V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70°C) PARAMETER SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP .MAX. UNIT NOTE Input "Low" voltage VIL 0.2VDD V Input "High" voltage VIH DI7-DI0, XCK, LP , L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF 0.8VDD V Output "Low" voltage VOL IOL = +0.4 mA +0.4 V Output "High" voltageVOH IOH = -0.4 mA EIO1, EIO2 VDD -0.4 V ILIL VI = LGND -10.0 µA Input leakage currentILIH VI = VDD DI7-DI0, XCK, LP , L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF +10.0 µA V0=30V 1.5 2.0Output resistance R ON |VON | =0. 5V V0=20V Y1-Y240 2.0 2.5 k Standby current I STB LGND+GND+VSS 75.0 µA 1 Supply current (1) (Non-selection) IDD1 VDD 2.0 mA 2 Supply current (2) (Selection) IDD2 VDD 12.0 mA 3 Supply current (3) I 0 V0L, V0R 1.5 mA 4 NOTES: 1. VDD = +5.0 V, V0 = +30.0 V, Vi = LGND. 2. VDD = +5.0 V, V0 = +30.0 V, fXCK = 15 MHz, no-load, El = VDD . The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +5.0 V, V0 = +30.0 V, fXCK = 15 MHz, no-load, El = LGND. The input data is turned over by data taking clock (4-bit parallel input mode). over by data taking clock (4-bit parallel input mode). (Common Mode) (LGND=V SS =GND = 0V, VDD = +2.5 ~ +5.5V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C) PARAMETER SYMBOL COND ITIONS APPLICABL E PI NS MI N. TYP . MAX. UNIT NOTE Input "Low" voltage VIL 0.2VDD V Input "High" voltage VIH DI7-DI0, XCK, LP , L/R FR, MD, S/C, EIO1, EIO2, /DISPOFF 0.8VDD V Output "Low" voltage VOL IOL = +0.4 mA +0.4 V Output "High" voltageVOH IOH = -0.4 mA EIO1, EIO2 VDD -0.4 V ILIL VI = LGND DI7-DI0, XCK, LP , L/R FR, MD, S/C, EIO1, EIO2, /DISPOFF -10.0 µA Input leakage current ILIH VI = VDD DI6-DI0, LP , L/R, FR, MD, S/C, /DISPOFF +10.0 µA Input pull-down current IPD VI = VDD DI7, XCK, EIO1, EIO2 100.0 µA V0=30V 1.5 2.0Output resistance R ON |VON | =0. 5V V0=20V Y1-Y240 2.0 2.5 k Standby current I SPD LGND+GND+VSS 75.0 µA 1 Supply current (1) I DD VDD 120.0 µA 2 Supply current (2) I 0 V0L, V0R 240.0 µA 2 NOTES: 1. VDD = +5.0 V, V0 = +30.0 V, VI = LGND
Preliminary Ver 0.12 Page 18/26 2008/01/24
11.2 AC Characteristics
(Segment Mode 1) (LGND=VSS = GND = 0 V, VDD = +5.0±0.5 V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C) PARAMETER SYMBOL CONDI TIONS MIN T YP . MAX. UNIT NOTE Shift clock period tWCK t R ,tF 10ns 66 ns 1 Shift clock "H" pulse width tWCKH 23 ns Shift clock "L" pulse width tWCKL 23 ns Data setup time tDS 15 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise timetLD 0 ns Shift clock fall to latch pulse fall time tSL 50 ns Latch pulse rise to shift clock rise timetLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 41 ns Output delay time (2) tPD1 , tPD2 CL = 15 pF 1.2 µs Output delay time (3) tPD3 CL = 15 pF 1.2 µs NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL )/2 is maximum in the case of high speed operation. (Segment Mode 2) (LGND=VSS =GND = 0V, VDD = +3.0 ~ +4.5V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to +70 °C) PARAMETER SYMBOL CONDITIONS MIN. TYP . MAX. UNIT NOTE Shift clock period tWCK t R ,tF 10ns 82 ns 1 Shift clock "H" pulse width tWCKH 28 ns Shift clock "L” pulse width tWCKL 28 ns Data setup time tDS 20 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise timetLD 0 ns Shift clock fall to latch pulse fall time tSL 65 ns Latch pulse rise to shift clock rise timetLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 57 ns Output delay time (2) tPD1 , tPD2 CL = 15 pF 1.2 µs Output delay time (3) tPD3 CL = 15 pF 1.2 µs NOTES: 1. Takes the cascade connection into consideration. 2. (t WCK - tWCKH - tWCKL )/2 is maximum in the case of high speed operation.
Preliminary Ver 0.12 Page 19/26 2008/01/24 (Segment Mode 3) (LGND=VSS =GND = 0V, VDD = +2.5 ~ +3.0V, V0 = + 15.0 ~ +30.0V, TOPR = -25 to+70 °C) PARAMETER SYMBOL CONDITIONS MIN. TYP . MAX. UNIT NOTE Shift clock period tWCK t R ,tF 10ns 130 ns 1 Shift clock "H" pulse width tWCKH 35 ns Shift clock "L” pulse width tWCKL 35 ns Data setup time tDS 25 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise timetLD 0 ns Shift clock fall to latch pulse fall time tSL 80 ns Latch pulse rise to shift clock rise timetLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tD CL = 15 pF 80 ns Output delay time (2) tPD1 , tPD2 CL = 15 pF 1.2 µs Output delay time (3) tPD3 CL = 15 pF 1.2 µs NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL )/2 is maximum in the case of high speed operation. (Common Mode) (LGND=V SS = 0 V, VDD = +2.5 ~ +5.5V, V0 = +15.0 ~ +30.0V, TOPR = -25 to +70° C) PARAMETER SYMBOL CONDITIONS M IN. TYP . MAX. UNIT Shift clock period tWLP tR ,tF 20ns 250 ns VDD = +5.0± 0.5V 15 nsShift clock "H" pulse width tWLPH VDD = +2.5+ 4.5V 30 ns Data setup time tSU 30 ns Data hold time tH 50 ns Input signal rise time tR 50 ns Input signal fall time tF 50 ns /DISPOFF removal time tSD 100 ns /DISPOFF "L" pulse width tWDL 1.2 µs Output delay time (1) tDL CL = 15 pF 200 ns Output delay time (2) tPD1 , t PD2 CL = 15 pF 1.2 µs Output delay time (3) t PD3 CL = 15 pF 1.2 µs
Preliminary Ver 0.12 Page 20/26 2008/01/24
11.3 Timing Chart of Segment Mode
/DISPOFF Y1 - Y240 tPD1 tPD3 tPD2 Fig. 8 Timing Characteristics (3) LP XCK DI7 - DI0 /DISPOFF tWLPH tLD tSL tLH tLS tWCKH tFtR tWCK tDS tDH TOP DATALAST DATA tWDL tSD tWCKL tS 12 n* tD LP XCK EI EO *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode
Preliminary Ver 0.12 Page 21/26 2008/01/24
11.4 Timing Chart of Common Mode
/DISPOFF tWDL tSD tDL tHtSU tWLP tR tWLPH tF FR LP /DISPOFF Y1 - Y240 tPD1 tPD3 tPD2
Preliminary Ver 0.12 Page 22/26 2008/01/24 12. APPLICATION CIRCUIT
12.1 Application Circuit for Module
Preliminary Ver 0.12 Page 23/26 2008/01/24 13. PAD DIAGRAM Unit : um Pad# Name X Y P ad# Name X Y P ad# Name X Y
Preliminary Ver 0.12 Page 24/26 2008/01/24
Preliminary Ver 0.12 Page 25/26 2008/01/24 272 Y196 - 3979.00 250.10 295 Y219 - 5175.00 250.10
13.1 Gold Bump Size
Pad No. X Y Area (um2) 1~10, 65~74 87.50 44.30 3876.2500 11, 12 , 63, 64 116.60 42.30 4932.1800 13, 62 160.20 33.30 5334.6600 14~17, 60, 61 92.50 42.30 3912.7500 18, 19, 21~26, 50~53, 55~59 131.30 42.40 5567.1200 20, 54 152.35 42.40 6459.6400 27~36 134.30 42.40 5694.3200 37 94.30 44.40 4186.9200 38 103.85 37.85 3930.7225 39, 40 85.65 57.75 4946.2875 41 117.20 52.25 6123.7000 42~49 140.80 42.40 5969.9200 196 91.00 81.00 7371.0000 75, 317 33.00 81.00 2673.0000 76~195, 197~316 37.00 81.00 2997.0000 Wafer thickness = 480±20um, Bump pad height = 15um, strength=30g
Preliminary Ver 0.12 Page 26/26 2008/01/24 14. REVISION REVISION DESCRIPTION P AGE DATE
0.10 First release 1-26 2006/12/11
0.11 Change Max. operating voltage to +30V Change Standby Current Application Pin to LGND+GND+VSS 1-26 2007/04/20
0.12 Change operating temperature to 70°C 16-19 2008/01/24
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