ST7565V

ST7565V SITRONIX | Alldatasheet

Document overview

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Technical content

65 x 132 Dot Matrix LCD Controller/Driver Ver 1.5b 1/72 2009/09/14 FFEE AA TTUU RR EE SS /circle6 Direct display of RAM data through the display data RAM. /circle6 RAM capacity : 65 x 132 = 8580 bits /circle6 Display duty selectable by select pin 1/65 duty : 65 common x 132 segment 1/49 duty : 49 common x 132 segment 1/33 duty : 33 common x 132 segment 1/55 duty : 55 common x 132 segment 1/53 duty : 53 common x 132 segment /circle6 High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported. /circle6 Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction selects, power saver, common output status select, V 5 voltage regulation internal resistor ratio set. /circle6 Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of 2X/3X/4X/5X/6X , where the step-up voltage reference power supply can be input externally). High-accuracy voltage adjustment circuit (Thermal gradient –0.05%/° C ) V 5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. /circle6 CR oscillator circuit equipped internally (external clock can also be input) /circle6 Extremely low power consumption Operating power when the built-in power supply is used (an example) 60uA (V DD – VSS = VDD – V SS2 =3.0 V, Quad voltage, Conditions: When displays pattern OFF and the normal mode is selected. /circle6 Power supply operate on the low 1.8 voltage Logic power supply V DD – VSS = 1.8V to 3.3V Boost reference voltage: VDD – VSS2 = 2.4V to 3.3V Booster maximum voltage limited V OUT = -13.5V Liquid crystal drive power supply: V DD – V5 = 4.0V to 12.0 V /circle6 Wide range of operating temperatures: –30 to 85° C /circle6 CMOS process /circle6 Shipping forms include bare chip and TCP. /circle6 These chips not designed for resistance to light or resistance to radiation. GG EE NN EE RR AA LL DD EE SS CC RR IIPP TTIIOO NN The ST7565V is a single-chip dot matrix LCD driver that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the ST7565V contain 65x132 bits of display data RAM and there is a 1-to-1 correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The ST7565V chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65x132 dot display (capable of displaying 8 columnsx4 rows of a 16x16 dot kanji font). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power LCD driver power supply, resistors for LCD driver power voltage adjustment and a display clock CR oscillator circuit, the ST7565V can be used to create the lowest power display system with the fewest components for high-performance portable devices. PART NO. V RS temperature gradient V RS range

Ver 1.5b 2/72 2009/09/14 SS TT77556655VV PP aadd AA rrrraannggeemm eenntt((CC OO GG )) Chip Size: 9,336 μm x 1,000 μm Bump Pitch: 58 μm(Min.) Bump Size: PAD No. 001 ～012 40 μm x 90 μm PAD No. 013 ～102 56 μm x 60 μm PAD No. 103 ～114 40 μm x 90 μm PAD No. 115 90 μm x 25.5 μm PAD No. 116 ～128 90 μm x 40 μm PAD No. 129 ～276 40 μm x 90 μm PAD No. 277 ～289 90 μm x 40 μm PAD No. 290 90 μm x 25.5 μm Bump Height: 18 μm Chip Thickness: 635 μm 15µm 15µm 15µm 15µm /circle6 Add new booster ratio 5 times and 6 times /circle6 Use select pin to define display duty as following table SEL 3 , 2 , 1 DUTY BIAS 0 , 0 , 0 1/65 1/9 or 1/7 0 , 0 , 1 1/49 1/8 or 1/6 0 , 1 , 0 1/33 1/6 or 1/5 0 , 1 , 1 1/55 1/8 or 1/6 1 , 0 , 0 1/53 1/8 or 1/6 30µm 24µm 38µm 30µm 15µm 15µm 15µm 15µm

Ver 1.5b 3/72 2009/09/14 PP aadd CC eenntteerr CC oooorrddiinnaatteess ((11//6655 DD uuttyy)) UU nniittss:: μμmm PAD No. PIN Name X Y

1 COM[53] 4241 374

2 COM[54] 4183 374

3 COM[55] 4125 374

4 COM[56] 4067 374

5 COM[57] 4009 374

6 COM[58] 3951 374

7 COM[59] 3893 374

8 COM[60] 3835 374

9 COM[61] 3777 374

10 COM[62] 3719 374

11 COM[63] 3661 374

12 COMS1 3603 374

13 TEST6 3443 389

14 FR 3369 389

15 CL 3295 389

17 VSS 3147 389

19 CS2 2999 389

20 VDD 2925 389

22 A0 2777 389

23 VSS 2703 389

24 /WR(R/W) 2629 389 25 /RD(E) 2555 389

26 VDD 2481 389

27 D0 2407 389

28 D1 2333 389

29 D2 2259 389

30 D3 2185 389

31 D4 2111 389

32 D5 2037 389

33 D 6 1963 389

34 D7 1889 389

35 VDD 1815 389

36 VDD 1741 389

37 VDD 1667 389

38 VSS 1593 389

39 VSS 1519 389

40 VSS2 1445 389

41 VSS2 1371 389

42 VOUT 1297 389

43 VOUT 1223 389

44 CAP5- 1149 389

45 CAP5- 1075 389

46 CAP1+ 1001 389

47 CAP1+ 927 389

No. PIN Name X Y

48 CAP3- 853 389

49 CAP3- 779 389

50 CAP1+ 705 389

51 CAP1+ 631 389

52 CAP1- 557 389

53 CAP1- 483 389

54 CAP2- 409 389

55 CAP2- 335 389

56 CAP2+ 261 389

57 CAP2+ 187 389

58 CAP4- 113 389

59 CAP4- 39 389

60 VSS -35 389

61 VSS -109 389

62 VRS -183 389

63 VRS -257 389

64 VDD -331 389

65 VDD -405 389

66 V1 -479 389

67 V1 -553 389

68 V2 -627 389

69 V2 -701 389

70 V3 -775 389

71 V3 -849 389

72 V4 -923 389

73 V4 -997 389

74 V5 -1071 389

75 V5 -1145 389

76 VR -1219 389

77 VR -1293 389

78 VDD -1367 389

79 VDD -1441 389

80 TEST0 -1515 389

81 TEST1 -1589 389

82 TEST2 -1663 389

83 TEST3 -1737 389

84 TEST4 -1811 389

85 TEST5 -1885 389

86 VDD -1959 389

87 M/S -2033 389

88 CLS -2107 389

89 VSS -2181 389

90 C86 -2255 389

91 P/S -2329 389

92 VDD -2403 389

94 VSS -2551 389

Ver 1.5b 4/72 2009/09/14 PAD No. PIN Name X Y

95 IRS -2625 389

96 VDD -2699 389

97 SEL1 -2773 389

98 VSS -2847 389

99 SEL2 -2921 389

100 VDD -2995 389

101 SEL3 -3069 389

102 VSS -3143 389

103 COM[31] -3606 374

104 COM[30] -3664 374

105 COM[29] -3722 374

106 COM[28] -3780 374

107 COM[27] -3838 374

108 COM[26] -3896 374

109 COM[25] -3954 374

110 COM[24] -4012 374

111 COM[23] -4070 374

112 COM[22] -4128 374

113 COM[21] -4186 374

114 COM[20] -4244 374

115 (NC) -4542 404

116 COM[19] -4542 351

117 COM[18] -4542 293

118 COM[17] -4542 235

119 COM[16] -4542 177

120 COM[15] -4542 119

121 COM[14] -4542 61

122 COM[13] -4542 3

123 COM[12] -4542 -55

124 COM[11] -4542 -113

125 COM[10] -4542 -171

126 COM[9] -4542 -229

127 COM[8] -4542 -287

128 COM[7] -4542 -345

129 COM[6] -4267 -374

130 COM[5] -4209 -374

131 COM[4] -4151 -374

132 COM[3] -4093 -374

133 COM[2] -4035 -374

134 COM[1] -3977 -374

135 COM[0] -3919 -374

136 COMS2 -3861 -374

137 SEG[0] -3803 -374

138 SEG[1] -3745 -374

139 SEG[2] -3687 -374

140 SEG[3] -3629 -374

141 SEG[4] -3571 -374

142 SEG[5] -3513 -374

143 SEG[6] -3455 -374

144 SEG[7] -3397 -374

145 SEG[8] -3339 -374

146 SEG[9] -3281 -374

No. PIN Name X Y

147 SEG[10] -3223 -374

148 SEG[11] -3165 -374

149 SEG[12] -3107 -374

150 SEG[13] -3049 -374

151 SEG[14] -2991 -374

152 SEG[15] -2933 -374

153 SEG[16] -2875 -374

154 SEG[17] -2817 -374

155 SEG[18] -2759 -374

156 SEG[19] -2701 -374

157 SEG[20] -2643 -374

158 SEG[21] -2585 -374

159 SEG[22] -2527 -374

160 SEG[23] -2469 -374

161 SEG[24] -2411 -374

162 SEG[25] -2353 -374

163 SEG[26] -2295 -374

164 SEG[27] -2237 -374

165 SEG[28] -2179 -374

166 SEG[29] -2121 -374

167 SEG[30] -2063 -374

168 SEG[31] -2005 -374

169 SEG[32] -1947 -374

170 SEG[33] -1889 -374

171 SEG[34] -1831 -374

172 SEG[35] -1773 -374

173 SEG[36] -1715 -374

174 SEG[37] -1657 -374

175 SEG[38] -1599 -374

176 SEG[39] -1541 -374

177 SEG[40] -1483 -374

178 SEG[41] -1425 -374

179 SEG[42] -1367 -374

180 SEG[43] -1309 -374

181 SEG[44] -1251 -374

182 SEG[45] -1193 -374

183 SEG[46] -1135 -374

184 SEG[47] -1077 -374

185 SEG[48] -1019 -374

186 SEG[49] -961 -374

187 SEG[50] -903 -374

188 SEG[51] -845 -374

189 SEG[52] -787 -374

190 SEG[53] -729 -374

191 SEG[54] -671 -374

192 SEG[55] -613 -374

193 SEG[56] -555 -374

194 SEG[57] -497 -374

195 SEG[58] -439 -374

196 SEG[59] -381 -374

197 SEG[60] -323 -374

198 SEG[61] -265 -374

Ver 1.5b 5/72 2009/09/14 PAD No. PIN Name X Y

199 SEG[62] -207 -374

200 SEG[63] -149 -374

201 SEG[64] -91 -374

202 SEG[65] -33 -374

203 SEG[66] 25 -374

204 SEG[67] 83 -374

205 SEG[68] 141 -374

206 SEG[69] 199 -374

207 SEG[70] 257 -374

208 SEG[71] 315 -374

209 SEG[72] 373 -374

210 SEG[73] 431 -374

211 SEG[74] 489 -374

212 SEG[75] 547 -374

213 SEG[76] 605 -374

214 SEG[77] 663 -374

215 SEG[78] 721 -374

216 SEG[79] 779 -374

217 SEG[80] 837 -374

218 SEG[81] 895 -374

219 SEG[82] 953 -374

220 SEG[83] 1011 -374

221 SEG[84] 1069 -374

222 SEG[85] 1127 -374

223 SEG[86] 1185 -374

224 SEG[87] 1243 -374

225 SEG[88] 1301 -374

226 SEG[89] 1359 -374

227 SEG[90] 1417 -374

228 SEG[91] 1475 -374

229 SEG[92] 1533 -374

230 SEG[93] 1591 -374

231 SEG[94] 1649 -374

232 SEG[95] 1707 -374

233 SEG[96] 1765 -374

234 SEG[97] 1823 -374

235 SEG[98] 1881 -374

236 SEG[99] 1939 -374

237 SEG[100] 1997 -374

238 SEG[101] 2055 -374

239 SEG[102] 2113 -374

240 SEG[103] 2171 -374

241 SEG[104] 2229 -374

242 SEG[105] 2287 -374

243 SEG[106] 2345 -374

244 SEG[107] 2403 -374

245 SEG[108] 2461 -374

No. PIN Name X Y

246 SEG[109] 2519 -374

247 SEG[110] 2577 -374

248 SEG[111] 2635 -374

249 SEG[112] 2693 -374

250 SEG[113] 2751 -374

251 SEG[114] 2809 -374

252 SEG[115] 2867 -374

253 SEG[116] 2925 -374

254 SEG[117] 2983 -374

255 SEG[118] 3041 -374

256 SEG[119] 3099 -374

257 SEG[120] 3157 -374

258 SEG[121] 3215 -374

259 SEG[122] 3273 -374

260 SEG[123] 3331 -374

261 SEG[124] 3389 -374

262 SEG[125] 3447 -374

263 SEG[126] 3505 -374

264 SEG[127] 3563 -374

265 SEG[128] 3621 -374

266 SEG[129] 3679 -374

267 SEG[130] 3737 -374

268 SEG[131] 3795 -374

269 COM[32] 3853 -374

270 COM[33] 3911 -374

271 COM[34] 3969 -374

272 COM[35] 4027 -374

273 COM[36] 4085 -374

274 COM[37] 4143 -374

275 COM[38] 4201 -374

276 COM[39] 4259 -374

277 COM[40] 4542 -345

278 COM[41] 4542 -287

279 COM[42] 4542 -229

280 COM[43] 4542 -171

281 COM[44] 4542 -113

282 COM[45] 4542 -55

283 COM[46] 4542 3

284 COM[47] 4542 61

285 COM[48] 4542 119

286 COM[49] 4542 177

287 COM[50] 4542 235

288 COM[51] 4542 293

289 COM[52] 4542 351

290 (NC) 4542 404

Ver 1.5b 6/72 2009/09/14 PP aadd CC eenntteerr CC oooorrddiinnaatteess ((11//4499 DD uuttyy)) UU nniittss:: μμmm PAD No. PIN Name X Y

1 COM[37] 4241 374

2 COM[38] 4183 374

3 COM[39] 4125 374

4 COM[40] 4067 374

5 COM[41] 4009 374

6 COM[42] 3951 374

7 COM[43] 3893 374

8 COM[44] 3835 374

9 COM[45] 3777 374

10 COM[46] 3719 374

11 COM[47] 3661 374

24 /WR(R/W) 2629 389 25 /RD(E) 2555 389 No. PIN Name X Y

Ver 1.5b 7/72 2009/09/14 PAD No. PIN Name X Y

103 Reserve -3606 374

104 Reserve -3664 374

105 Reserve -3722 374

106 Reserve -3780 374

107 Reserve -3838 374

108 Reserve -3896 374

109 Reserve -3954 374

110 Reserve -4012 374

115 (NC) -4542 404 No. PIN Name X Y

Ver 1.5b 8/72 2009/09/14 PAD No. PIN Name X Y No. PIN Name X Y

269 Reserve 3853 -374

270 Reserve 3911 -374

271 Reserve 3969 -374

272 Reserve 4027 -374

273 Reserve 4085 -374

274 Reserve 4143 -374

275 Reserve 4201 -374

276 Reserve 4259 -374

277 COM[24] 4542 -345

278 COM[25] 4542 -287

279 COM[26] 4542 -229

280 COM[27] 4542 -171

281 COM[28] 4542 -113

282 COM[29] 4542 -55

283 COM[30] 4542 3

284 COM[31] 4542 61

285 COM[32] 4542 119

286 COM[33] 4542 177

287 COM[34] 4542 235

288 COM[35] 4542 293

289 COM[36] 4542 351

290 (NC) 4542 404

Ver 1.5b 9/72 2009/09/14 PP aadd CC eenntteerr CC oooorrddiinnaatteess ((11//3333 DD uuttyy)) UU nniittss:: μμmm PAD No. PIN Name X Y

1 COM[21] 4241 374

2 COM[22] 4183 374

3 COM[23] 4125 374

4 COM[24] 4067 374

5 COM[25] 4009 374

6 COM[26] 3951 374

7 COM[27] 3893 374

8 COM[28] 3835 374

9 COM[29] 3777 374

10 COM[30] 3719 374

11 COM[31] 3661 374

24 /WR(R/W) 2629 389 25 /RD(E) 2555 389 No. PIN Name X Y

Ver 1.5b 10/72 2009/09/14 PAD No. PIN Name X Y

111 Reserve -4070 374

112 Reserve -4128 374

113 Reserve -4186 374

114 Reserve -4244 374

115 (NC) -4542 404

116 Reserve -4542 351

117 Reserve -4542 293

118 Reserve -4542 235

119 Reserve -4542 177

No. PIN Name X Y

Ver 1.5b 11/72 2009/09/14 PAD No. PIN Name X Y No. PIN Name X Y

277 Reserve 4542 -345

278 Reserve 4542 -287

279 Reserve 4542 -229

280 Reserve 4542 -171

281 Reserve 4542 -113

282 Reserve 4542 -55

283 Reserve 4542 3

284 Reserve 4542 61

285 COM[16] 4542 119

286 COM[17] 4542 177

287 COM[18] 4542 235

288 COM[19] 4542 293

289 COM[20] 4542 351

290 (NC) 4542 404

Ver 1.5b 12/72 2009/09/14 PP aadd CC eenntteerr CC oooorrddiinnaatteess ((11//5555 DD uuttyy)) UU nniittss:: μμmm PAD No. PIN Name X Y

1 COM[43] 4241 374

2 COM[44] 4183 374

3 COM[45] 4125 374

4 COM[46] 4067 374

5 COM[47] 4009 374

6 COM[48] 3951 374

7 COM[49] 3893 374

8 COM[50] 3835 374

9 COM[51] 3777 374

10 COM[52] 3719 374

11 COM[53] 3661 374

24 /WR(R/W) 2629 389 25 /RD(E) 2555 389 No. PIN Name X Y

Ver 1.5b 13/72 2009/09/14 PAD No. PIN Name X Y 115 (NC) -4542 404 No. PIN Name X Y

Ver 1.5b 14/72 2009/09/14 PAD No. PIN Name X Y No. PIN Name X Y

274 COM[27] 4143 -374

275 COM[28] 4201 -374

276 COM[29] 4259 -374

277 COM[30] 4542 -345

278 COM[31] 4542 -287

279 COM[32] 4542 -229

280 COM[33] 4542 -171

281 COM[34] 4542 -113

282 COM[35] 4542 -55

283 COM[36] 4542 3

284 COM[37] 4542 61

285 COM[38] 4542 119

286 COM[39] 4542 177

287 COM[40] 4542 235

288 COM[41] 4542 293

289 COM[42] 4542 351

290 (NC) 4542 404

Ver 1.5b 15/72 2009/09/14 PP aadd CC eenntteerr CC oooorrddiinnaatteess ((11//5533 DD uuttyy)) UU nniittss:: μμmm PAD No. PIN Name X Y

1 COM[41] 4241 374

2 COM[42] 4183 374

3 COM[43] 4125 374

4 COM[44] 4067 374

5 COM[45] 4009 374

6 COM[46] 3951 374

7 COM[47] 3893 374

8 COM[48] 3835 374

9 COM[49] 3777 374

10 COM[50] 3719 374

11 COM[51] 3661 374

24 /WR(R/W) 2629 389 25 /RD(E) 2555 389 No. PIN Name X Y

Ver 1.5b 16/72 2009/09/14 PAD No. PIN Name X Y 115 (NC) -4542 404 No. PIN Name X Y

Ver 1.5b 17/72 2009/09/14 PAD No. PIN Name X Y No. PIN Name X Y

275 COM[26] 4201 -374

276 COM[27] 4259 -374

277 COM[28] 4542 -345

278 COM[29] 4542 -287

279 COM[30] 4542 -229

280 COM[31] 4542 -171

281 COM[32] 4542 -113

282 COM[33] 4542 -55

283 COM[34] 4542 3

284 COM[35] 4542 61

285 COM[36] 4542 119

286 COM[37] 4542 177

287 COM[38] 4542 235

288 COM[39] 4542 293

289 COM[40] 4542 351

290 (NC) 4542 404

Ver 1.5b 18/72 2009/09/14 BB LLOO CC KK DD IIAA GG RR AA MM MPU INTERFACE ( Parallel and Serial Command decoder Status Bus holder DISPLAY DATA RAM

65 X 132 = 8580

circuit Display timing generator circuit

132 SEGMENT

64 COMMON

COM output control circuit COMSVDD VR VRS IRS VOUT HPM CAP1+ CAP1- CAP2+ CAP2- CAP3+ CAP4- CAP5- Power Supply Circuit VSS2 VSS Voltage booster circuit Voltage Regulato r circuit Voltage followe r circuit SEG0 SEG131 COM0 COM63 COMS M/S CL DOF FR CLS D7(SI) D6(SCL) P/S C86 CS2 /RES CS1 RW(/WR) E(/RD) SEL3 SEL2 SEL1

Ver 1.5b 19/72 2009/09/14 PP IINN DD EE SS CC RR IIPP TTIIOO NN SS Power Supply Pins Pin Name I/O Function No. of Pins VDD Power Supply Shared with the MPU power supply terminal Vcc. 13 VSS Power Supply This is a 0V terminal connected to the system GND. 10 VSS2 Power Supply This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. 2 VRS Power Supply This is the internal-output VREG power supply for the LCD power supply voltage regulator. 2 V1, V2, V3, V4, Power Supply This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. VDD (= V0) ≧V1 ≧V2 ≧V3 ≧V4 ≧V5 When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. 1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY 1/9*V5,1/7*V5 2/9*V5,2/7*V5 7/9*V5,5/7*V5 8/9*V5,6/7*V5 1/8*V5,1/6*V5 2/8*V5,2/6*V5 6/8*V5,4/6*V5 7/8*V5,5/6*V5 1/6*V5,1/5*V5 2/6*V5,2/5*V5 4/6*V5,3/5*V5 5/6*V5,4/5*V5 1/8*V5,1/6*V5 2/8*V5,2/6*V5 6/8*V5,4/6*V5 7/8*V5,5/6*V5 1/8*V5,1/6*V5 2/8*V5,2/6*V5 6/8*V5,4/6*V5 7/8*V5,5/6*V5 LCD Power Supply Pins Pin Name I/O Function No. of Pins CAP1+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. 4 CAP1– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 CAP2+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. 2 CAP2– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. 2 CAP3– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 CAP4– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. 2 CAP5– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 VOUT O DC/DC voltage converter. Connect a capacitor between this terminal and VSS. 2 VR I Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. IRS = “L” : the V5 voltage regulator internal resistors are not used . IRS = “H” : the V5 voltage regulator internal resistors are used .

Ver 1.5b 20/72 2009/09/14 System Bus Connection Pins Pin Name I/O Function No. of Pins D5 to D0 D6 (SCL) D7 (SI) I/O This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = “L”) : D7 : serial data input (SI) ; D6 : the serial clock input (SCL). D0 to D5 are set to high impedance. When the chip select is not active, D0 to D7 are set to high impedance. A0 I This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = “H”: Indicates that D0 to D7 are display data. A0 = “L”: Indicates that D0 to D7 are control data. /RES I When /RES is set to “L,” the settings are initialized. The reset operation is performed by the /RES signal level. 1 /CS1 CS2 I This is the chip select signal. When /CS1 = “L” and CS2 = “H,” then the chip select becomes active, and data/command I/O is enabled. 2 /RD (E) I

• When connected to an 8080 MPU, this is active LOW. (E) This pin is connected to the /RD signal of the 8080 MPU, and the ST7565V series data bus is in an output status when this signal is “L”.
• When connected to a 6800 Series MPU, this is active HIGH. This is the 6800 Series MPU enable clock input terminal. /WR (R/W) I
• When connected to an 8080 MPU, this is active LOW. (R/W) This terminal connects to the 8080 MPU /WR signal. The signals on the data bus are latched at the rising edge of the /WR signal.
• When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write. C86 I This is the MPU interface switch terminal. C86 = “H”: 6800 Series MPU interface. C86 = “L”: 8080 MPU interface. P/S I This is the parallel data input/serial data input switch terminal. P/S = “H”: Parallel data input. P/S = “L”: Serial data input. The following applies depending on the P/S status: P/S Data/Command Data Read/Write Serial Clock “H” A0 D0 to D7 /RD, /WR X “L” A0 SI (D7) Write only SCL (D6) When P/S = “L”, D0 to D5 fixed “H”. /RD (E) and /WR (R/W) are fixed to either “H” or “L”. With serial data input, It is impossible read data from RAM .

Ver 1.5b 21/72 2009/09/14 Pin Name I/O Function No. of Pins CLS I Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = “H” : used Internal oscillator circuit . CLS = “L” : used external clock input .(internal oscillator is disable) When CLS = “L”, input the display clock through the CL terminal. M/S I This terminal selects the master/slave operation for the ST7565V Series chips. Master operation outputs the timing signals that are required for the LC D display, while slave operation input the timing signals required for the liquid crystal display, Synchronizing the liquid crystal display system. M/S = “H” Master operation M/S = “L” Slave operation M/S CLS Oscillator Circuit Power Supply Circuit CL FR DOF “H” “H” “L” Enabled Disabled Enabled Enabled Output Input Output Output Output Output “L” “H” “L” Disabled Disabled Disabled Disabled Input Input Input Input Input Input CL I/O This is the display clock input terminal The following is true depending on the M/S and CLS status. M/S CLS CL “H” “H” “L” Output Input “L” “H” “L” Input Input FR O This is the liquid crystal alternating current signal terminal. 1 /DOF O This is the LCD blanking control terminal. 1 IRS I This terminal selects the resistors for the V5 voltage level adjustment. IRS = “H”: Use the internal resistors IRS = “L”: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal /HPM I This is the power control terminal for the power supply circuit for liquid crystal drive. /HPM = “H”: Normal mode /HPM = “L”: High power mode SEL3 SEL2 SEL1 I These pins are DUTY selection. SEL 3 , 2 , 1 DUTY BIAS 0 , 0 , 0 1/65 1/9 or 1/7 0 , 0 , 1 1/49 1/8 or 1/6 0 , 1 , 0 1/33 1/6 or 1/5 0 , 1 , 1 1/55 1/8 or 1/6 1 , 0 , 0 1/53 1/8 or 1/6 TEST0 ~ 6 I These are terminals for IC testing. They are set to open. 6

Ver 1.5b 22/72 2009/09/14 LCD Driver Pins Pin Name I/O Function No. of Pins SEG0 to SEG131 O These are the LCD segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD , V2, V3, and V5. Output Voltage RAM DATA FR Normal Display Reverse Display H H V DD V 2 H L V 5 V 3 L H V 2 V DD L L V 3 V 5 Sleep Mode V DD 132 COM0 to COMn O Through a combination of the contents of the scan data and with the FR signal, a single level is selected from V DD , V 1, V 4, and V 5. Scan Data FR Output Voltage H H V 5 H L V DD L H V 1 L L V 4 Sleep Mode V DD COMS O These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used. I/O PIN ITO Resister Limitation PIN Name ITO Resister FR, /DOF, C86, P/S, M/S, /HPM,SEL1…SEL3, CLS, IRS No Limitation TEST0… 6 Floating VDD , VSS , VSS2 , VOUT , VR, VRS <100 Ω V1, V2, V3, V4, V5, CAP1+, CAP1 –, CAP2+, CAP2 –, CAP3 –, CAP4 –, CAP5 – <300 Ω /CS1, CS2, CL, E, R/W, A0, D0…D7, <1K Ω /RES <10K Ω

Ver 1.5b 23/72 2009/09/14 DD EE SS CC RR IIPP TTIIOO NN OO FF FFUU NN CC TTIIOO NN SS The MPU Interface Selecting the Interface Type With the ST7565V chips, data transfers are done through an 8-bit parallel data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/ S terminal polarity to the “H” or “L” it is possible to select either parallel data input or serial data input as shown in Table 1. Table 1 P/S /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0 H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0 L: Serial Input /CS1 CS2 A0 — — — SI SCL (HZ) “—” indicates fixed to either “H” or to “L” The Parallel Interface When the parallel interface has been selected (P/S =“H”), then it is possible to connect directly to either an 8080-system MPU or a 6800 Series MPU (shown in Table 2) by selecting the C86 terminal to either “H” or to “L”. Table 2 C86 (P/S=H) /CS1 CS2 A0 E(/RD) R/W(/WR) D7~D0 H: 6800 Series /CS1 CS2 A0 E R/W D7~D0 L: 8080 Series /CS1 CS2 A0 /RD /WR D7~D0 Moreover, data bus signals are recognized by a combination of A0, /RD (E), /WR (R/W) signals, as shown in Table 3. Table 3 Shared

6800 Series 8080 Series

1 1 0 1 Reads the display data 1 0 1 0 Writes the display data 0 1 0 1 Status read 0 0 1 0 Write control data (command)

Ver 1.5b 24/72 2009/09/14 The Serial Interface When the serial interface has been selected (P/S = “L”) then when the chip is in active state (/CS1 = “L” and CS2 = “H”) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = “H”, the data is display data, and when A0 = “L” then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 CS1 CS2 SI SCL Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. The Chip Select The ST7565V have two chip select terminals: /CS1 and CS2. The MPU interface or the serial interface is enabled only when /CS1 = “L” and CS2 = “H”. When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, /RD, and /WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. The Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC ) requirement alone in accessing the ST7565V. Wait time may not be considered. And, in the ST7565V, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy r e a d i s r e qu i r e d whe n eve r t he ad d r es s se t u p or write cycle operation is conducted. This relationship is shown in Figure 2.

Ver 1.5b 25/72 2009/09/14 The Busy Flag When the busy flag is “1” it indicates that the ST7565V is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time (tCYC ) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. N N+1 N+2 N+3 N+3N+2N+1N DATA BUS Holder Write Signal WR MPU Internal Timing Writing DATA WR MPU Reading N N n n+1 RD Preset N Increment N+1 N+2 n n+1N n+2 Address Preset Read Signal Column Address Bus Holder Internal Timing Address Set Dummy Read Data Read #n Data Read #n+1 Figure 2

Ver 1.5a 26/72 2009/02/23 Display Data RAM The display data RAM stores the dot data for the LCD. It has a 65 (8 page x 8 bit +1) x 132 bit structure. As is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the LCD display common direction; there are few constraints at the time of display data transfer when multiple ST7565V are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). Display data RAM COM0 COM1 COM2 COM3 COM4 Liquid crystal display Figure 3 The Page Address Circuit Page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special RAM for icons, and only display data D0 is used. (see Figure 4) The Column Addresses The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementing of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to respective both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. As is shown in Figure 4, Table 4 SEG Output ADC SEG0 SEG 131 (D0) “0” (D0) “1” 0 (H) → Column Address → 83 (H) 83 (H) ← Column Address ← 0 (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for ST7565V , the detail is shown page.11 The display area is a 65 line area for the ST7565V. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed.

Ver 1.5b 27/72 2009/09/14 Page Address D3 D2 D1 D0 Data Line Address When the common output is normal COM Output D0 00H COM0 D1 01H COM1 D2 02H COM2 D3 03H COM3 D4 04H COM4 D5 05H COM5 D6 06H COM6 0 0 0 0 Page 0 07H COM7 D0 08H COM8 D1 09H COM9 D2 0AH COM10 D3 0BH COM11 D4 0CH COM12 D5 0DH COM13 D6 0EH COM14 0 0 0 1 Page 1 0FH COM15 D0 10H COM16 D1 11H COM17 D2 12H COM18 D3 13H COM19 D4 14H COM20 D5 15H COM21 D6 16H COM22 0 0 1 0 Page 2 17H COM23 D0 18H COM24 D1 19H COM25 D2 1AH COM26 D3 1BH COM27 D4 1CH COM28 D5 1DH COM29 D6 1EH COM30 0 0 1 1 Page 3 1FH COM31 D0 20H COM32 D1 21H COM33 D2 22H COM34 D3 23H COM35 D4 24H COM36 D5 25H COM37 D6 26H COM38 0 1 0 0 Page 4 27H COM39 D0 28H COM40 D1 29H COM41 D2 2AH COM42 D3 2BH COM43 D4 2CH COM44 D5 2DH COM45 D6 2EH COM46 0 1 0 1 Page 5 2FH COM47 D0 30H COM48 D1 31H COM49 D2 32H COM50 D3 33H COM51 D4 34H COM52 D5 35H COM53 D6 36H COM54 0 1 1 0 Page 6 37H COM55 D0 38H COM56 D1 39H COM57 D2 3AH COM58 D3 3BH COM59 D4 3CH COM60 D5 3DH COM61 D6 3EH COM62 0 1 1 1 Page 7 3FH COM63 1 0 0 0 D0 Page 8 COMS ADC Column address Regardless of the display start line address, 1/65duty => 64th line, 1/49duty =>48th line. S123 S124 S125 S126 S127 S128 S129 S130 S131 LCD Out 1/33duty =>32th line, 1/55duty =>54th line, 1/53duty =>52th line. Figure 4

Ver 1.5b 28/72 2009/09/14 The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S= “H” and CLS = “H”. When CLS = “L” the oscillation stops, and the external clock is input through the CL terminal. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Two-frame alternating current drive waveform 64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 VDD COM0 VDD COM1 VDD RAM Data SEGn FR CL Figure 5

Ver 1.5b 29/72 2009/09/14 The Common Output Status Select Circuit In the ST7565V chips, the COM output scan direction can be selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized. Table 6 COM Scan Direction Status 1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY Normal Reverse COM0 → COM63 COM63 → COM0 COM0 → COM47 COM47 → COM0 COM0 → COM31 COM31 → COM0 COM0 → COM53 COM53 → COM0 COM0 → COM51 COM51 → COM0 Common output pins Duty Com dir com[0:15] com[16:23] com[24:26] com[27:36] com[37:39] com[40:47] com[48:63] coms 0 com[0:63] coms 1/65 1 com[63:0] coms 0 com[0:23] reserve com[24:47] coms 1/49 1 com[47:24] reserve com[23:0] coms 0 com[0:15] reserve com[16:31] coms 1/33 1 com[31:16] reserve com[15:0] coms 0 com[0:26] reserve com[27:53] coms 1/55 1 com[53:27] reserve com[26:0] coms 0 com[0:25] reserve com[26:51] coms 1/53 1 com[51:26] reserve com[25:0] coms

Ver 1.5b 31/72 2009/09/14 The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the LCD drivers. They are Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations. Table 7 bit function Status “1” “0” Booster circuit control bit Voltage regulator circuit control bit (V/R circuit) Voltage follower circuit control bit (V/F circuit) ON OFF ON OFF ON OFF The Control Details of Each Bit of the Power Control Set Command Table 8 Use Settings D2 D1 D0 Voltage booster Voltage regulator Voltage follower External voltage input Step-up voltage Only the internal power supply is used 1 1 1 ON ON ON VSS2 Used Only the voltage regulator circuit and the voltage follower circuit are used 0 1 1 OFF ON ON V OUT , V SS2 Open Only the V/F circuit is used 0 0 1 OFF OFF ON V5, V SS2 Open Only the external power supply is used 0 0 0 OFF OFF OFF V 1 to V5 Open Reference Combinations * The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–. * While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the ST7565V chips it is possible to product a 2X,3X,4X,5X or 6X step-up of the V DD – VSS2 voltage levels. 6X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, between CAP2+ and CAP4–,between CAP1+ and CAP5–, and between V SS2 and VOU T, to produce a voltage level in the negative direction at the VOUT terminal that is 6 times the voltage level between V DD and V SS 2. 5X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, between CAP2+ and CAP4–,and between V SS2 and VOU T, to produce a voltage level in the negative direction at the VOUT t erminal that is 5 times the voltage level between V DD and V SS 2. 4X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, and between V SS2 and VOU T, to produce a voltage level in the negative direction at the VOUT terminal that is 4 times the voltage level between V DD and V SS 2. 3X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2– and between V SS2 and V OUT , and short between CAP3– and VOUT to produce voltages level in the negative direction at the VOUT terminal that is 3 times the voltage difference between V DD and V SS 2. 2X step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between V SS2 and V OUT , leave CAP2+ open, and short between CAP2–, CAP3– and VOUT to produce a voltage in the negative direction at the VOUT terminal that Is twice the voltage between VDD and V SS 2. The step-up voltage relationships are shown in Figure 7

Ver 1.5b 32/72 2009/09/14 2x voltage booster circuit CAP1+ CAP1- CAP5- OPEN VDD / V SS2 VOUT CAP2+ OPEN CAP4- OPEN CAP2- CAP3- 3x voltage booster circuit CAP1+ CAP1- CAP5- OPEN VDD / V SS2 VOUT CAP4- OPEN CAP3- CAP2+ CAP2- 4x voltage booster circuit CAP1+ CAP1- CAP5- OPEN VDD / V SS2 VOUT CAP4- OPEN CAP2+ CAP2- CAP3- 5x voltage booster circuit CAP1+ CAP1- CAP5- OPEN VDD / V SS2 VOUT CAP4- CAP2+ CAP2- CAP3- 6x voltage booster circuit CAP1+ CAP1- VDD / V SS2 VOUT CAP4- CAP2+ CAP2- CAP3- CAP5- C1 2x boost voltage relationship VSS2 VDD =0V VOUT <=2x(V SS2 -V DD ) Do NOT over voltage limitation 3x boost voltage relationship VOUT <=3x(V SS2 -V DD ) Do NOT over voltage limitation VSS2 VDD =0V 4x boost voltage relationship VOUT <=4x(V SS2 -V DD ) Do NOT over voltage limitation VSS2 VDD =0V 6x boost voltage relationship VOUT <=6x(V SS2 -V DD ) Do NOT over voltage limitation VSS2 VDD =0V 5x boost voltage relationship VOUT <=5x(V SS2 -V DD ) Do NOT over voltage limitation VSS2 VDD =0V Figure 7 * The V SS2 voltage range must be set so that the V OUT voltage does not exceed the absolute maximum rated value. * For compatibility with ST7565P, V OUT can connect a capacitor to V SS2 or V DD . If don’t have to consider the compatibility issue, “Connect V OUT to V SS2 ”.

Ver 1.5b 33/72 2009/09/14 The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the LCD driver voltage V5 through the voltage regulator circuit. Because the ST7565V chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V 5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. (VREG thermal gradients approximate -0.05%/° C) (A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V 5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V 5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V5 voltage can be calculated using equation A-1 over the range where Figure 8 ( ) Rb Ra+1 VEVV5 = = ( ) Rb Ra+1 (1 - α 162 ) VREG [∵ V EV = (1 - α 162 ) VREG] Internal Ra Internal Rb VEV(constant voltage supply+electronic volume) VDD

Ver 1.5b 34/72 2009/09/14 VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25° C is as shown in Table 9. Table 9 Part no. Equipment Type Thermal Gradient VREG ST7565V Internal Power Supply –0.05 %/° C –2.1V α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume registers. Table 10 shows the value for α depending on the electronic volume register settings. Rb/Ra is the V 5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V5 voltage regulator internal resistor ratio register. Table 10 D5 D4 D3 D2 D1 D0 αα αα 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 V 5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table 11 Register ST7565V 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Figures 9, 10 show V5 voltage measured by values of the internal resistance ratio resistor for V5 voltage adjustment and electric volume resister for each temperature grade model.

Ver 1.5b 35/72 2009/09/14 00 00 -1 -1 -1 -1 -2 -2 -2 -2 -3 -3 -3 -3 -4 -4 -4 -4 -5 -5 -5 -5 -6 -6 -6 -6 -7 -7 -7 -7 -8 -8 -8 -8 -9 -9 -9 -9 -10 -10 -10 -10 -11 -11 -11 -11 -12 -12 -12 -12 -13 -13 -13 -13 -14 -14 -14 -14 -15 -15 -15 -15 00H 1FH 3FH V 5 U N IT:V 000 001 010 011 100 101 110 111 V 5 voltage regulator internal resistor ratio set D 2,D 1,D 0 Electronic volum e registered D 5 ~ D 0 Ta = 25 °C and booster off ,regulator,follow er on V SS=-3V Figure 9 : (1) For ST7565V the Thermal Gradient = -0.05%/° C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. Setup example: When selecting Ta = 25° C and V5 = –7V for an ST7565V on which Temperature gradient = –0.05%/° C. Using Figure 9 and the equation A-1, the following setup is enabled. At this time, the variable range and the notch width of the V5 voltage is, as shown Table 13, as dependent on the electronic volume. Table 12 Register Contents D5 D4 D3 D2 D1 D0 For V5 voltage regulator Electronic Volume — — — 0 1 0 1 0 0 1 0 1 Table 13 V5 Min Typ Max Units Variable Range Notch width –8.4 (63 levels) –7.0 (central value) –5.1 (0 level) [V] 51 [mV]

Ver 1.5b 36/72 2009/09/14 (B) When an External Resistance is Used (The V 5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V5 can also be set without using the V 5 voltage regulator internal resistors (IRS terminal = “L”) by adding resistors Ra’ and Rb’ between V DD and V R , and between V R and V 5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V 5 through commands. In the range where | V 5 | < | V OUT |, the V 5 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’. ( ) Rb' Ra'+1 VEVV5 = = ( ) Rb' Ra'+1 (1 - α 162 ) VREG [∵ V EV = (1 - α 162 ) VREG] External resistor Ra' V EV(fixed voltage power supply+electronic volume) VDD External resistor Rb' Figure 11 Setup example: When selecting Ta = 25° C and V 5 = –7 V for ST7565V the temperature gradient = –0.05%/° C. When the central value of the electron volume register is V REG = –2.1V so, according to equation B-1, = ( ) Rb' Ra'+1 (1 - 31 162 ) (-2.1)-7V = ( ) Rb' Ra'+1 (1 - α 162 ) VREGV5 Moreover, when the value of the current running through Ra’ and Rb’ is set to 5 uA, Ra’ + Rb’ = 1.4M Ω (Equation B-3) Consequently, by equations B-2 and B-3, =Rb' Ra' 3.12 Ra' = 340kΩ Rb' = 1060kΩ At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14. Table 14 V5 Min Typ Max Units Variable Range Notch width –8.6 (63 levels) –7.0 (central value) –5.3 (0 level) [V] 52 [mV]

Ver 1.5b 37/72 2009/09/14 (C) When External Resistors are Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V 5. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V 5 by commands to adjust the liquid crystal display brightness. In the range where | V 5 | < | V OUT | the V 5 voltage can be calculated by equation C-1 below based on the R 1 and R 2 (variable resistor) and R 3 settings, where R 2 can be subjected to fine adjustments ( Δ R 2). ( ) R3+R2-ΔR2 R1+ΔR2+1 VEVV5 = = ( )+1 (1 - α 162 ) VREG [∵ V EV = (1 - α 162 ) VREG] R3+R2-ΔR2 R1+ΔR2 External resistor R1 VEV(fixed voltage power supply+electronic volume) VDD External resistor R3 VR ΔR2 External resistor R2 Rb' Ra' Figure 12 Setup example: When selecting Ta = 25° C and V5 = –5 to –9 V (using R2) for an ST7565V the temperature gradient = –0.05%/° C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and V REG = –2.1 V so, according to equation C-1, when ΔR 2 = 0 Ω, in order to make V5 = –9 V, R3+R2 R1+1-9V= ) (1 - 31 162 ) (-2.1) When ΔR 2 = R2, in order to make V = –5 V, 162 ) (-2.1) When the current flowing VDD and V5 is set to 5 uA, R1 + R 2 + R 3 = 1.4M Ω (Equation C-4) With this, according to equation C-2, C-3 and C-4, R1 = 264kΩ R2 = 211kΩ R3 = 925kΩ The V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15. Table 15 V5 Min Typ Max Units Variable Range Notch width –8.7 (63 levels) –7.0 (central value) –5.3 (0 level) [V] 53 [mV]

Ver 1.5b 39/72 2009/09/14 Reference Circuit Examples 1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor is used. (Example where V SS 2 = VSS , with 4x step-up) (2) When the voltage regulator internal resistor is not used. (Example where VSS 2 = VSS , with 4x step-up) VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7565V IRS M/S V DD VDD VSS VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7565V IRS M/S V DD VSS VDD CAP4- CAP5- CAP4- CAP5- 2. When the voltage regulator circuit and V/F circuit alone are used (1) When the V 5 voltage regulator internal resistor is not used. (2) When the V 5 voltage regulator internal resistor is used. VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7565V IRS M/S V DD VSS VDD VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7565V IRS M/S V DD VDD VSS External power supply External power supply CAP4- CAP5- CAP4- CAP5-

Ver 1.5b 40/72 2009/09/14 (3) When the V/F circuit alone is used (4) When the built-in power is not used VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7565V IRS M/S V DD VDD VSS External power supply VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7565V IRS M/S VDD VDD VSS External power supply CAP4- CAP5- CAP4- CAP5- * 1. Because the VR terminal input impedance is high, use short leads and shielded lines. * 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings:

• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value.
• Next turn all the power supplies ON and determine C1. Item Set value units 1.0 to 4.7 0.1 to 4.7 uF uF C1 and C2 are determined by the size of the LCD being driven

Ver 1.5b 41/72 2009/09/14 The Reset Circuit When the /RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = “L”) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: 1/65 DUTY = 1/9 bias 1/49,1/55,1/53 DUTY = 1/8 bias 1/33 DUTY = 1/6 bias 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = “L”) 8. Power saving clear 9. V 5 voltage regulator internal resistors Ra and Rb separation 10. Output conditions of SEG and COM terminals SEG=VDD , COM=VDD 11. Read modify write OFF 12. Display start line set to first line 13. Column address set to Address 0 14. Page address set to Page 0 15. Common output status normal 16. V 5 voltage regulator internal resistor ratio set mode clear 17. Electronic volume register set mode clear Electronic volume register : 18. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 18 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the /RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an over current may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on ST7565V,it is necessary that /RES is “H” when the external liquid crystal power supply is turned on. This IC has the function to discharge V 5 when /RES is “L,” and the external power supply short-circuits to VDD when /RES is “L.” This means that an internal resistor is connected between VDD and V5. While /RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. The VDD level is output from the SEG and COM output terminals after a successful hardware reset.

Ver 1.5b 42/72 2009/09/14 CC OO MM MM AA NN DD SS The ST7565V identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. <Explanation of Commands> Display ON/OFF This command turns the display ON and OFF. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 1 1 1 1 Display ON Display OFF When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details. Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Line address 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Page address 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 0 0

Ver 1.5b 43/72 2008/09/14 Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 Column address High bits → Low bits → 0 1 0 0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0

0 A3 A2 A1 A0 0 0 0 0 0 0 0 1

0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0 BUSY BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process. BUSY = 0: A new comm and can be accepted . if the cycle time can be satisfied, there is no need to check for BUSY conditions. ADC This shows the relationship between the column address and the segment driver. 0: Reverse (column address 131-n ↔ SEG n) 1: Normal (column address n ↔ SEG n) (The ADC command switches the polarity.) ON/OFF ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) RESET This indicates that the chip is in the process of initialization either because of a / RES signal or because of a reset command. 0: Operating state 1: Reset in progress Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write data

Ver 1.5b 44/72 2008/09/14 Display Data Read This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read data ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 0 0 0 Normal Reverse Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 1 1 0 RAM Data “H” LCD ON voltage (normal) RAM Data “L” LCD ON voltage (reverse) Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 1 0 0 Normal display mode Display all points ON When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the Sleep Mode Set section.

Ver 1.5b 45/72 2009/09/14 LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. Select Status E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias 0 1 0 1 0 1 0 0 0 1 0 1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias Read/Modify/Write This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. Yes No Read-Modify-Write Done Page Address Set Column Address Set Finished? Dummy Read Read-Modify-Write Cycle Data Read Modify Data Data Write (at same Address) Figure 24 Command Sequence For read modify write

Ver 1.5b 46/72 2009/09/14 Figure 25 End This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 Reset This command initializes the display start line, the column address, the page address, the common output mode, the V 5 voltage regulator internal resistor ratio, the electronic volume, and the read/modify/write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details. The reset operation is performed after the reset command is entered. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 0 The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset command must not be used instead. Common Output Mode Select This command can select the scan direction of the COM output terminal. For details, see the function explanation in “Common Output Mode Select Circuit.” Selected Mode E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 1/65duty 1/49duty 1/33duty 1/55duty 1/53duty 0 1 0 1 1 0 0 0 * * * Normal Reverse COM0 →COM63 COM63 →COM0 COM0 →COM47 COM47 →COM0 COM0 →COM31 COM31 →COM0 COM0 →COM53 COM53 →COM0 COM0 →COM51 COM51 →COM0 * Disabled bit Column address Read-modify-write mode set N N+1 N+2 N+3 N+m N End Return

Ver 1.5b 47/72 2009/09/14 Power Controller Set This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode 0 0 1 0 1 0 Booster circuit: OFF Booster circuit: ON Voltage regulator circuit: OFF Voltage regulator circuit: ON 0 1 0 Voltage follower circuit: OFF Voltage follower circuit: ON V5 Voltage Regulator Internal Resistor Ratio Set This command sets the V 5 voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage Regulator circuit " and table 11 . E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Rb/Ra Ratio 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 Small Large The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1

Ver 1.5b 48/72 2009/09/14 Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V 5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 | V5 | 0 1 0 * * 0 0 0 0 0 1 * * 0 0 0 0 1 0 * * 0 0 0 0 1 1 * * 1 1 1 1 1 0 * * 1 1 1 1 1 1 Small Large * Inactive bit (set “0”) When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) The Electronic Volume Register Set Sequence Figure 26

Ver 1.5b 50/72 2009/09/14 The Booster Ratio (Double Byte Command) This command makes it possible to select step-up ratio. It is used when the power control set have turn on the internal booster circuit. This command is a two byte command used as a pair with the booster ratio select mode set command and the booster ratio register set command, and both commands must be issued one after the other. Booster Ratio Select Mode Set When this command is input, the Booster ratio register set command becomes enabled. Once the booster ratio select mode has been set, no other command except for the booster ratio register command can be used. Once the booster ratio register set command has been used to set data into the register, then the booster ratio select mode is released. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 1 0 0 0 Booset Ratio Register Set By using this command to set two bits of data to the booster ratio register,it can be select what kind of the booster ratio can be used. When this command is input, the booster ratio select mode is released after the booster ratio register has been set. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Booster ratio select 0 1 0 2x,3x,4x * Inactive bit (set “0”) When the booster ratio select function is not used, set this to (0, 0) 2x,3x,4x step-up mode The booster ratio Register Set Sequence Booster Ratio Set Done Booster Ratio Select Mode Set Booster Ratio Register Set Set Complete? Yes No Figure 29

Ver 1.5b 51/72 2009/09/14 NOP Non-OPeration Command E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 1 Test This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a “L” signal to the /RES input by the reset command or by using an NOP. E R/W A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 1 1 * * * Inactive bit Note: The ST7565V maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the ST7565V . Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed p eriodically to prevent the effects of unanticipated noise.

Ver 1.5b 52/72 2009/09/14 Table 16: Table of ST7565V Commands (Note) *: disabled data Command Code Command A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Function (1) Display ON/OFF 0 1 0 1 0 1 0 1 1 1 0 LCD display ON/OFF 0: OFF, 1: ON (2) Display start line set 0 1 0 0 1 Display start address Sets the display RAM display start line address (3) Page address set 0 1 0 1 0 1 1 Page address Sets the display RAM page address (4) Column address set upper bit Column address set lower bit 0 1 0 0 1 0 0 0 0 1 Most significant column address 0 0 0 0 Least significant column address Sets the most significant 4 bits of the display RAM column address. Sets the least significant 4 bits of the display RAM column address. (5) Status read 0 0 1 Status 0 0 0 0 Reads the status data (6) Display data write 1 1 0 Write data Writes to the display RAM (7) Display data read 1 0 1 Read data Reads from the display RAM (8) ADC select 0 1 0 1 0 1 0 0 0 0 0 Sets the display RAM address SEG output correspondence 0: normal, 1: reverse (9) Display normal/ reverse 0 1 0 1 0 1 0 0 1 1 0 Sets the LCD display normal/ reverse 0: normal, 1: reverse (10) Display all points ON/OFF 0 1 0 1 0 1 0 0 1 0 0 Display all points 0: normal display 1: all points ON (11) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 Sets the LCD drive voltage bias ratio 0: 1/9 bias, 1: 1/7 bias (ST7565V) (12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 Column address increment At write: +1 At read: 0 (13) End 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write (14) Reset 0 1 0 1 1 1 0 0 0 1 0 Internal reset (15) Common output mode select 0 1 0 1 1 0 0 0 * * * Select COM output scan direction 0: normal direction 1: reverse direction (16) Power control set 0 1 0 0 0 1 0 1 Operating mode Select internal power supply operating mode (17) V5 voltage regulator internal resistor ratio set 0 1 0 0 0 1 0 0 Resistor ratio Select internal resistor ratio(Rb/Ra) mode (18) Electronic volume mode set Electronic volume register set 0 1 0 1 0 0 0 0 0 0 1 0 0 Electronic volume value Set the V5 output voltage electronic volume register (19) Sleep Mode Set 0 1 0 1 0 1 0 1 1 0 0 0: Display Mode 1: Normal Mode (20) Booster ratio set 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 step-up value select booster ratio 00: 2x,3x,4x 01: 5x 11: 6x (21) NOP 0 1 0 1 1 1 0 0 0 1 1 Command for non-operation (22) Test 0 1 0 1 1 1 1 * * * * Command for IC test. Do not use this command

Ver 1.5b 53/72 2009/09/14 CC OO MM MM AA NN DD DD EE SS CC RR IIPP TTIIOO NN Instruction Setup: Reference (1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1. When the built-in power is being used immediately after turning on the power: * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting

Ver 1.5b 54/72 2009/09/14 2. When the built-in power is not being used immediately after turning on the power: * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting *8: Command description; Sleep mode (multiple commands)

Ver 1.5b 55/72 2009/09/14 (2) Data Display Write Display Data (After Initialized) Data setup by Data Write (6) Display Data Write ...*12 Function setup by command (user setting) (2) Display Start Line Set ...*9 (3) Page Address Set ...*10 (4) Column Address Set ...*11 Function setup by command (user setting) (1) Display ON/ OFF ...*13 End of Write Display Data Notes: Reference items *9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying all the data at the data display start (when the display is ON) in white. (3) Power OFF *14 Notes: Reference items *14: The logic circuit of this IC’s power supply V DD - VSS controls the driver of the LCD power supply VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures:

• After turning off the internal power supply, make sure that the potential V 5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS ). 6. Description of Function, 6.7 Power Circuit *15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (19) Sleep Mode Set *16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (19) Sleep Mode Set

Ver 1.5b 56/72 2009/09/14 Refresh It is recommended to turn on the refresh sequence regularly at a specified interval. Precautions on Turning off the power <Turning the power (V DD - VSS ) off> 1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS ) OFF

• Observe tL > tH .
• When tL < tH , an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of V1 ~ V5) and the driver’s discharging capacity. Reset Power save Power Off tL 1.8V VSS VSS tH COM SEG V DD RES Since the power (V DD -V SS ) is cut off, the output comes not to be fixed. VOUT Above Vth of the LCD Panel. Under Vth of the LCD Panel. Depends on the LCD Module characteristic (around 0.2~1V).

Ver 1.5b 57/72 2009/09/14 <Turning the power (VDD - VSS ) off : When command control is not possible.> 2) Reset (The LCD powers (VDD - VSS ) are off.) → Power (VDD - VSS ) OFF

• Observe tL > tH .
• When tL < tH , an irregular display may occur. For tL, make the power (VDD - VSS ) falling characteristics longer or consider any other method. tH is determined according to the external capacity C2 (smoothing capacity of V1 to V5) and the driver’s discharging capacity. Reset Power Off tL 1.8V VSS COM SEG VDD RES Since the power (V DD -V SS ) is cut off,the output comes not be fixed. tH VSS Above Vth of the LCD Panel. VOUT Under Vth of the LCD Panel. Depends on the LCD Module characteristic (around 0.2~1V). <Reference Data> V5 voltage falling (discharge) time (tH ) after the process of operation → power save → reset. V5 voltage falling (discharge) time (tH ) after the process of operation → reset. 5.0 4.0 3.0 2.4 1.8 1.00.50 100 VDD-VSS(V) C2 : V1 to V5 capacity (uF) V5 voltage falling time (mSec) Figure 31

Ver 1.5b 58/72 2009/09/14 AA BB SS OO LLUU TTEE MM AA XX IIMM UU MM RR AA TTIINN GG SS Unless otherwise noted, VDD = 0V Table 17 Parameter Symbol Conditions Unit Power Supply Voltage VSS –3.6 ~ +0.3 V Power supply voltage (V DD standard) V SS2 –3.6 ~ +0.3 V Power supply voltage (V DD standard) V 5, V OUT –13.5 ~ +0.3 V Power supply voltage (V DD standard) V 1, V 2, V 3, V 4 V 5 to +0.3 V Input voltage VIN –0.3 to V DD + 0.3 V Output voltage VO –0.3 to V DD + 0.3 V Operating temperature TOPR –30 to +85 ° C Storage temperature TCP Bare chip T STR –55 to +100 –65 to +150 ° C VDD VSS2,V1 to V4 V5.,VOUT VDD VSS VCC GND System (MPU) side ST7565S chip side Figure 30 Notes and Cautions 1. The V SS2 , V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well.

Ver 1.5b 59/72 2009/09/14 DD CC CC HH AA RR AA CC TTEE RR IISS TTIICC SS Unless otherwise specified, VSS = –3.0V, VDD = 0V, Ta = –30 to 85° C Table 18 Rating Item Symbol Condition Min. Typ. Max. Units Applicable Pin Operating Voltage (1) Vss -3.3 — -1.8 V Vss*1 Operating Voltage (2) V SS2 (Relative to VDD ) –3.3 — –2.4 V V SS2 0.4 x V5 — V DD V 1, V2 Operating Voltage (3) V SS2 (Relative to VDD ) V5 — 0.6 x V 5 V V3, V4 High-level Input Voltage VIHC 0.8 x V DD — V DD V *3 Low-level Input Voltage VILC V SS — 0.2 x V DD V *3 High-level Output Voltage VOHC I OH = –0.5 mA 0.8 x V DD — V DD V *4 Low-level Output Voltage VOLC I OL = 0.5 mA V SS — 0.2 x V DD V *4 Input leakage current I LI V IN = VDD or VSS –1.0 — 1.0 μA *5 Output leakage current I LO V IN = VDD or VSS –3.0 — 3.0 μA *6 V5 = –13.0 V — 2.0 3.5 Liquid Crystal Driver ON Resistance R ON Ta = 25° C (Relative To V KΩ SEGn COMn *7 Static Consumption Current ISSQ — 0.01 2 μA VSS , VSS2 Output Leakage Current I 5Q V5 = –13.0V (Relative to VDD ) — 0.01 10 μA V5 Input Terminal Capacitance C IN Ta = 25° C , f = 1 MHz — 5.0 8.0 pF Internal Oscillator fOSC 17 20 24 kHz *8 External Input fCL 1/65 duty 1/33 duty Ta = 25° C 17 20 24 kHz CL Internal Oscillator fOSC 25 30 35 kHz *8 Oscillator Frequency External Input fCL 1/49 duty 1/53 duty 1/55 duty Ta = 25° C 25 30 35 kHz CL

Ver 1.5b 60/72 2009/09/14 Table 19 Rating Item Symbol Condition Min. Typ. Max. Units Applicable Pin Input voltage V SS2 (Relative To VDD ) –3.3 — –2.4 V V SS2 Supply Step-up output voltage Circuit VOUT (Relative To VDD ) –13.5 — — V V OUT Voltage regulator Circuit Operating Voltage VOUT (Relative To VDD ) –13.5 — –6.0 V V OUT Voltage Follower Circuit Operating Voltage V5 (Relative To VDD ) –12.0 — –4.0 V V 5 * 9 Internal Power Base Voltage V RS Ta = 25° C , (Relative To V DD ) –0.05%/° C

• Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used . Table 20 Rating Test pattern Symbol Condition Min. Typ. Max. Units Notes Display Pattern OFF IDD VDD = 3.0 V, V5 – VDD = –11.0 V — 16 27 μA *11 Display Pattern Checker IDD VDD = 3.0 V, V5 – VDD = –11.0 V — 19 32 μA *11
• Dynamic Consumption Current : During Display, with the Internal Power Supply ON Table 21 Rating Test pattern Symbol Condition Min. Typ. Max. Units Notes Normal Mode — 60 100 Display Pattern OFF IDD VDD = 3.0 V, Quad step-up voltage. V5 – VDD = –11.0 V High-Power Mode — 98 163 μA *12 Normal Mode — 70 117 Display Pattern Checker IDD VDD = 3.0 V, Quad step-up voltage. V5 – VDD = –11.0 V High-Power Mode — 105 175 μA *12
• Consumption Current at Time of Power Saver Mode : VSS = -3.0 V Table 22 Rating Item Symbol Condition Min. Typ. Max. Units Notes Sleep mode IDD Ta = 25° C — 0.1 4 μA

Ver 1.5b 61/72 2009/09/14

• The Relationship Between Oscillator Frequency f OSC , Display Clock Frequency fCL and the Liquid Crystal Frame Rate Frequency fFR Table 23 Item fCL fFR Used internal oscillator circuit fOSC / 4 fOSC / (4*65) 1/65 DUTY Used externa l display clock External input (fCL ) fCL / 260 Used internal oscillator circuit fOSC / 4 fOSC / (4*49) 1/49 DUTY Used external display clock External input (fCL ) fCL / 196 Used internal oscillator circuit fOSC / 8 fOSC / (8*33) 1/33 DUTY Used external display clock External input (fCL ) fCL / 264 Used internal oscillator circuit fOSC / 4 fOSC / (4*55) 1/55 DUTY Used external display clock External input (fCL ) fCL / 220 Used internal oscillator circuit fOSC / 4 fOSC / (4*53) 1/53 DUTY Used external display clock External input (fCL ) fCL / 212 (fFR is the liquid crystal alternating current period, and not the FR signal period.) References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the V DD system and the V5 system is. This applies when the external power supply is being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), /RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, M/S, C86, P/S, /DOF, /RES, IRS, and /HPM terminals. *4 The D0 to D7, FR, /DOF, and CL terminals. *5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, M/S, C86, P/S, /RES, IRS, and /HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V 1, V2, V3, and V4). These are specified for the operating voltage (3) range. R ON = 0.1 V / ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.) *8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the ST7565V , the temperature range approximately –0.05%/° C. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. The ST7565V is 1/9 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. *12 It is the value on a ST7565V having the VREG temperature gradient is –0.05%/° C when the V5 voltage regulator internal resistor is used.

Ver 1.5b 62/72 2009/09/14 TTIIMM IINN GG CC HH AA RR AA CC TTEE RR IISS TTIICC SS System Bus Read/Write Characteristics 1 (For the 8080 Series MPU) tAH8tAW8 tCYC8 tCCLR,tCCLW tCCHR,tCCHW tDS8 tACC8 tOH8 tDH8 CS1 (CS2="1") WR,RD D0 to D7 (Write) D0 to D7 (Read) Figure 37 Table 24 (VDD = 3.3V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH8 0 — Address setup time tAW8 0 — System cycle time tCYC8 240 — Enable L pulse width (WRITE) tCCLW 100 — Enable H pulse width (WRITE) WR tCCHW 100 — Enable L pulse width (READ) tCCLR 140 — Enable H pulse width (READ) RD tCCHR 100 WRITE Data setup time tDS8 40 — WRITE Address hold time tDH8 20 — READ access time tACC8 C L = 100 pF — 70 READ Output disable time D0 to D7 tOH8 C L = 100 pF 5 135 ns

Ver 1.5b 63/72 2009/09/14 Table 25 (VDD = 2.7V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH8 0 — Address setup time tAW8 0 — System cycle time tCYC8 400 — Enable L pulse width (WRITE) tCCLW 220 — Enable H pulse width (WRITE) WR tCCHW 180 — Enable L pulse width (READ) tCCLR 220 — Enable H pulse width (READ) RD tCCHR 180 — WRITE Data setup time tDS8 40 — WRITE Address hold time tDH8 20 — READ access time tACC8 C L = 100 pF — 140 READ Output disable time D0 to D7 tOH8 C L = 100 pF 10 160 ns Table 26 (VDD = 1.8V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH8 0 — Address setup time tAW8 0 — System cycle time tCYC8 640 — Enable L pulse width (WRITE) tCCLW 360 — Enable H pulse width (WRITE) WR tCCHW 280 — Enable L pulse width (READ) tCCLR 360 — Enable H pulse width (READ) RD tCCHR 280 WRITE Data setup time tDS8 80 — WRITE Address hold time tDH8 30 — READ access time tACC8 C L = 100 pF — 240 READ Output disable time D0 to D7 tOH8 C L = 100 pF 10 520 ns *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≦ (tCYC8 – tCCLW – tCCHW ) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR ) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between /CS1 being “L” (CS2 = “H”) and /WR and /RD being at the “L” level.

Ver 1.5b 64/72 2009/09/14 System Bus Read/Write Characteristics 2 (For the 6800 Series MPU) tAH6tAW6 tCYC6 tCCLR,tCCLW tCCHR,tCCHW tDS6 tACC6 tOH6 tDH6 CS1 (CS2="1") E R/W D0 to D7 (Write) D0 to D7 (Read) Figure 38 Table 27 (VDD = 3.3V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH6 0 — Address setup time tAW6 0 — System cycle time tCYC6 275 — Enable L pulse width (WRITE) tEWLW 140 — Enable H pulse width (WRITE) WR tEWHW 140 — Enable L pulse width (READ) tEWLR 130 — Enable H pulse width (READ) RD tEWHR 130 WRITE Data setup time tDS6 40 — WRITE Address hold time tDH6 25 — READ access time tACC6 C L = 100 pF — 70 READ Output disable time D0 to D7 tOH6 C L = 100 pF 5 225 ns

Ver 1.5b 65/72 2009/09/14 Table 28 (VDD = 2.7V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH6 0 — Address setup time tAW6 0 — System cycle time tCYC6 400 — Enable L pulse width (WRITE) tEWLW 220 — Enable H pulse width (WRITE) WR tEWHW 180 — Enable L pulse width (READ) tEWLR 220 — Enable H pulse width (READ) RD tEWHR 180 — WRITE Data setup time tDS6 40 — WRITE Address hold time tDH6 25 — READ access time tACC6 C L = 100 pF — 140 READ Output disable time D0 to D7 tOH6 C L = 100 pF 10 250 ns Table 29 (VDD = 1.8V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH6 0 — Address setup time tAW6 0 — System cycle time tCYC6 640 — Enable L pulse width (WRITE) tEWLW 360 — Enable H pulse width (WRITE) WR tEWHW 280 — Enable L pulse width (READ) tEWLR 360 — Enable H pulse width (READ) RD tEWHR 280 — WRITE Data setup time tDS6 80 — WRITE Address hold time tDH6 30 — READ access time tACC6 C L = 100 pF — 240 READ Output disable time D0 to D7 tOH6 C L = 100 pF 10 430 ns *1 The input signal rise time and fall time ( tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≦ (tCYC6 – tEWLW – tEWHW ) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR ) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.

Ver 1.5b 66/72 2009/09/14 The Serial Interface tCSH CS1 (CS2="1") SI SCL tCCSS tSAS tSAH tSCYC tSLW tSHW tSDHtSDS tf tr Figure 39 Table 30 (VDD = 3.3V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period Tscyc 100 — SCL “H” pulse width Tshw 50 — SCL “L” pulse width SCL TSLW 50 — Address setup time TSAS 20 — Address hold time Tsah 20 — Data setup time Tsds 20 — Data hold time SI TSDH 20 — CS-SCL time Tcss 20 — CS-SCL time CS Tcsh 40 — ns Table 31 (VDD = 2.7V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period Tscyc 120 — SCL “H” pulse width TSHW 60 — SCL “L” pulse width SCL TSLW 60 — Address setup time TSAS 30 — Address hold time TSAH 25 — Data setup time TSDS 30 — Data hold time SI TSDH 25 — CS-SCL time TCSS 30 — CS-SCL time CS TCSH 60 — ns

Ver 1.5b 67/72 2009/09/14 Table 32 (VDD = 1.8V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period TSCYC 200 — SCL “H” pulse width TSHW 80 — SCL “L” pulse width SCL TSLW 80 — Address setup time TSAS 60 — Address hold time TSAH 30 — Data setup time TSDS 60 — Data hold time SI TSDH 30 — CS-SCL time TCSS 40 — CS-SCL time CS TCSH 100 — ns *1 The input signal rise and fall time ( tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.

Ver 1.5b 68/72 2009/09/14 Reset Timing Internal status tRW tR During reset Reset complete RES Figure 41 Table 36 (VDD = 3.3V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tR — — 1.5 us Reset “L” pulse width /RES tRW 1.5 — — us Table 37 (VDD = 2.7V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tR — — 2.0 us Reset “L” pulse width /RES tRW 2.0 — — us Table 38 (VDD = 1.8V, Ta = –30 to 85° C) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tR — — 3.0 us Reset “L” pulse width /RES tRW 3.0 — — us *1 All timing is specified with 20% and 80% of V DD as the standard.

Ver 1.5b 70/72 2009/09/14 ST7565S Slave ST7565S Master M/S FR CL DOF FR CL DOF Output Input VDD VSS CLS CLS M/S ST7565S Slave ST7565S Master M/S FR CL DOF FR CL DOF Output Input VDD VSS CLS CLS M/S ST7565S SLAVE ST7565V SLAVE ST7565V SLAVE ST7565V MASTER ST7565V MASTER CC OO NN NN EE CC TTIIOO NN SS BB EE TTWW EE EE NN LLCC DD DD RR IIVV EE RR SS ((RR EE FFEE RR EE NN CC EE EE XX AA MM PP LLEE )) The liquid crystal display area can be enlarged with ease through the use of multiple ST7565V Series chips. Use a same equipment type. (1) ST7565V (master) ↔ ST7565V (slave) Figure 43-1

Ver 1.5b 72/72 2009/09/14 Revisions Version 0.1 - Preliminary. Version 0.2 - update Pad Center Coordinates page 2,3,4,5 Version 0.2a - update ABSOLUTE MAXIMUM RATINGS and DC CHARACTERISTICS Version 0.2b - update DC CHARACTERISTICS , Pad Arrangement Version 0.2c - update AC CHARACTERISTICS (serial) Version 0.2d - update PIN DESCRIPTIONS M/S Version 0.2e - update ABSOLUTE MAXIMUM RATINGS and DC CHARACTERISTICS Version 0.2f - update Master and Slave reference example. Version 0.3 - update Pad Center Coordinates (1/65 , 1/49 , 1/33 , 1/55 , 1/53 Duty) page 3..17 Version 0.3a - update Pad Diagram page2 and v5 regulator voltage diagram(figure 9) page35 Version 0.3b - Logic power supply VDD – VSS = 1.8V to 3.3 V (+10% Range) , VOUT= -13V (+10% Range) Version 0.3c - Modify page-38 The temperature grade of the Internal Power Supply for ST7565V (-0.05%/° C) Figure 14 Version 0.4 - Delete recommended to connect an external resistor to stabilize potentials of V 1, V2, V3 and V4 Version 1.0 - Transition to ST7565V Version 1.1 - Modify Tdh (data hold time) and page53,54 initial flow Version 1.2 - Modify Voltage range and Temperature range. Version 1.3 - Add ITO resistance limitation - Modify the description of DC characteristics. - Modify function description. - Redraw figures. - Redraw the PAD DIAGRAM. - Highlight the HPM (High Power Mode) description. - Put emphasis on the power OFF procedure (Page 56-57). Version 1.4 - Fix Ver. 1.3: Booster Circuit mistake (Booster X6, Page 32). Version 1.5 - Remove static indicator function. - Modify timing characteristics.. Version 1.5a - Modify mistake of Status Read. Version 1.5b - Modify the mistake of The Reset Circuit.