ST7921 SITRONIX | Alldatasheet
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96CH Segment Driver For Dot Matrix LCD Ver 1.6 1/11 2005/05/24 /square6 Features : /circle6 Display driving bias : static to 1/5 /circle6 Power supply for logic : 2.7V ~ 5.5V /circle6 Power supply for LCD voltage (V 0~V SS ) : 3V ~ 7V /circle6 Dot matrix LCD driver with two 48 channel outputs /circle6 Bias voltage (V0 ~ V4) /circle6 Input/Output signals /square6 Input : Serial display data and control pulse from controller IC /square6 Output : 48 X 2 channels waveform for LCD driving /square6 General Description : ST7921 is a segment driver for dot matrix type LCD display. It features 96 channels with 48 X 2 bits bi-directional shift registers, data latches, LCD drivers and logic control circuits. It is fabricated by high voltage CMOS process with low current consumption. The ST7921 can convert serial data received from an LCD controller, such as ST7920, into parallel data and send out LCD driving waveforms to the LCD panel. The ST7921 is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCD. The LSI can be used as segment driver.
Ver 1.6 2/11 2005/05/24 /square6 ST7921 Functional Block SEGMENT DRIVER SEGMENT DRIVER BIDIRECTIONAL SHIFTER(48bits) BIDIRECTIONAL SHIFTER(48bits) DATA LATCH(48bits) DATA LATCH(48bits) CONTOL CL2 CL1 M DL1 SHL1 DR1 DL2 SHL2 DR2 V DD VSS
Ver 1.6 3/11 2005/05/24 /square6 Pin Description : Pin Name Purpose Description I/O VDD POWER for logic N/A VSS GROUND for logic N/A LCD Power for LCD driving voltage I S1-S48 segment LCD driver output for part 1 O SHL1 direction direction control for part 1 segment s I DL1, DR1 data in /out If SHL1 = 1 then DL1=out, DR1=in If SHL1 = 0 then DL1=in, DR1=out I/O S49-S96 segment LCD driver output for part 2 O SHL2 direction direction control for part 2 segment s I DL2, DR2 data in/out If SHL2 = 1 then DL2=out, DR2=in If SHL2 = 0 then DL2=in, DR2=out I/O M alternation Alternate the LCD driving waveform I CL1 latch clock latch the data after shift is compl eted I CL2 shift clock shift the data into the segments I
Ver 1.6 4/11 2005/05/24 /square6 Pad Arrangement * chip substrate must connect to VSS 5678 23491 (0,0 Size: 4720x2560 um Coordinate: center Min. PAD Pitch: 120um G792E “GSM792E” Marking: Easy to find the PAD Circle here to find the first PAD
Ver 1.6 5/11 2005/05/24 /square6 Bonding Description Pad No. Pad Name X Y Pad No. Pad Name X Y
1 S[50] -2240 -1160 29 S[78] 1140 -1160
2 S[51] -2110 -1160 30 S[79] 1260 -1160
3 S[52] -1980 -1160 31 S[80] 1380 -1160
4 S[53] -1860 -1160 32 S[81] 1500 -1160
5 S[54] -1740 -1160 33 S[82] 1620 -1160
6 S[55] -1620 -1160 34 S[83] 1740 -1160
7 S[56] -1500 -1160 35 S[84] 1860 -1160
8 S[57] -1380 -1160 36 S[85] 1980 -1160
9 S[58] -1260 -1160 37 S[86] 2110 -1160
10 S[59] -1140 -1160 38 S[87] 2240 -1160
11 S[60] -1020 -1160 39 S[88] 2240 -1030
12 S[61] -900 -1160 40 S[89] 2240 -900
13 S[62] -780 -1160 41 S[90] 2240 -780
14 S[63] -660 -1160 42 S[91] 2240 -660
15 S[64] -540 -1160 43 S[92] 2240 -540
16 S[65] -420 -1160 44 S[93] 2240 -420
17 S[66] -300 -1160 45 S[94] 2240 -300
18 S[67] -180 -1160 46 S[95] 2240 -180
19 S[68] -60 -1160 47 S[96] 2240 -60
20 S[69] 60 -1160 48 S[48] 2240 60
21 S[70] 180 -1160 49 S[47] 2240 180
22 S[71] 300 -1160 50 S[46] 2240 300
23 S[72] 420 -1160 51 S[45] 2240 420
24 S[73] 540 -1160 52 S[44] 2240 540
25 S[74] 660 -1160 53 S[43] 2240 660
26 S[75] 780 -1160 54 S[42] 2240 780
27 S[76] 900 -1160 55 S[41] 2240 900
28 S[77] 1020 -1160 56 S[40] 2240 1030
Ver 1.6 6/11 2005/05/24 Pad No. Pad Name X Y Pad No. Pad Name X Y
57 S[39] 2240 1160 85 S[11] -1140 1160
58 S[38] 2110 1160 86 S[10] -1260 1160
59 S[37] 1980 1160 87 S[9] -1380 1160
60 S[36] 1860 1160 88 S[8] -1500 1160
61 S[35] 1740 1160 89 S[7] -1620 1160
62 S[34] 1620 1160 90 S[6] -1740 1160
63 S[33] 1500 1160 91 S[5] -1860 1160
64 S[32] 1380 1160 92 S[4] -1980 1160
65 S[31] 1260 1160 93 S[3] -2110 1160
66 S[30] 1140 1160 94 S[2] -2240 1160
67 S[29] 1020 1160 95 S[1] -2240 1030
68 S[28] 900 1160 96 V0 -2240 890
69 S[27] 780 1160 97 V2 -2240 750
70 S[26] 660 1160 98 V3 -2240 610
71 S[25] 540 1160 99 VSS -2240 475
72 S[24] 420 1160 100 VDD -2240 340
73 S[23] 300 1160 101 CL1 -2240 210
74 S[22] 180 1160 102 SHL1 -2240 80
75 S[21] 60 1160 103 SHL2 -2240 -50
76 S[20] -60 1160 104 CL2 -2240 -180
77 S[19] -180 1160 105 DL1 -2240 -310
78 S[18] -300 1160 106 DR1 -2240 -440
79 S[17] -420 1160 107 DL2 -2240 -580
80 S[16] -540 1160 108 DR2 -2240 -720
81 S[15] -660 1160 109 M -2240 -860
82 S[14] -780 1160 110 S[49] -2240 -1010
83 S[13] -900 1160
84 S[12] -1020 1160
Ver 1.6 7/11 2005/05/24 /square6 Functional Description : Clock The CL1 is the clock to latch data on the falling edge. It latches the data input from the bi-directional shift register at the falling edge of CL1 and transfers its outputs to the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CL2 and transfers the output of each bit of the register to the latch circuit. Shift Registers And Data I/O The ST7921 supplies two sets of 48-bit shift register, which controls the shift direction by SHL1 & SHL2. The SHL1 controls the 1st 48-bit shift register, and SHL2 controls the 2nd 48-bit shift register. When SHL1 is connected to VDD, the 1st shift direction is from S48 to S1; when SHL1 is connected to VSS, the shift direction changes from S1 to S48. When SHL2 is connected to VDD, the 2nd shift direction is from S96 to S49; when SHL2 is connected to VSS, the shift direction changes from S49 to S96. The DL1, DR1, DL2, DR2 are data input or output option function. Shift Direction of Channel 1 SHL1 Shift Direction DL1 DR1
0 S1 /barb2right S48 IN OUT
1 S48 /barb2right S1 OUT IN
Shift Direction of Channel 2 SHL2 Shift Direction DL2 DR2
0 S49 /barb2right S96 IN OUT
1 S96 /barb2right S49 OUT IN
Ver 1.6 8/11 2005/05/24 /square6 LCD Output Waveforms : /square6 Timing Characteristics : Output of LATCH (DATA) M Output (S1 ~ S80) VSS VSS CL2 Data in (DL1, DL2) (DR1, DR2) Data out (DL1, DL2) (DR1, DR2) CL1 M VIH VIL TR TWCKH TF TWCKL TDH TSU TD VOH VOL TSL TLS TLS TWCKH TR TSU
Ver 1.6 9/11 2005/05/24 /square6 D.C Characteristics: Symbol Parameter Test Condition Min. Typ. Max. Unit Applicable pin V DD Operating Voltage - 2.7 - 5.5 V - V LCD Driver Supply Voltage V 0-VSS 3 - 7 V - V IH Input High Voltage - 0.7V DD - V DD V V IL Input Low Voltage - 0 - 0.3V DD V ILKG Input Leakage Current V IN = 0 ~ V DD -5 - 5 uA CL1,CL2,M,SHL1,SHL2 DL1,DL2,DR1,DR2 V OH Output High Voltage I OH = -0.4mA V DD -0.4 - - V V OL Output Low Voltage I OL = +0.4mA - - 0.4 V DL1,DL2,DR1,DR2 V1~V4, S1~S80 IDD Operating Current F CL2 = 400K HZ - 280 460 uA V DD ,V 0 IV Leakage Current V IN = V DD ~ V SS -10 - 10 uA V1 ~ V4 /square6 A.C Characteristics : Symbol Parameter Test Condition Min. Max. Unit Applicable pin FCL Data Shift Frequency - - 400 K HZ CL2 T WCKH Clock High Level Width - 800 - ns CL1,CL2 T WCKL Clock Low Level Width - 800 - ns CL2 T SL Clock Set-up Time CL2 /barb2right CL1 500 - ns CL1,CL2 T LS Clock Set-up Time CL1 /barb2right CL2 500 - ns CL1,CL2 T R /T F Clock Rise/Fall Time - - 200 ns CL1,CL2 T SU Data Set-up Time - 300 - ns DL1,DL2,DR1,DR2 T DH Data Hold Time - 300 - ns DL1,DL2,DR1,DR2 T D Data Delay Time CL = 15 PF - 500 ns DL1,DL2,DR1,DR2 /square6 Maximum Absolute Ratings : Symbol Parameters Min. Max. Unit V DD Supply Voltage -0.3 7 V TOPR Operating Temperature -20 85 0C TSTG Storage Temperature -55 125 0C
Ver 1.6 10/11 2005/05/24 ST7920 Dot Matrix LCD Panel VSS Vcc(+5V/+3V) DB0-DB7 To MPU M CL1 CL2 VSS VDD Seg 1-64 Com 1-32 Note: Regsister=2.2K~10K ohm VR=1K~30Kohm ST7921 V2 V3 V0 VSS SHL2 SHL1 VDD DL1 M CL2 CL1 DR1 DL2 DR2 Seg 1-96 ST7921 V2 V3 V0 VSS SHL2 SHL1 VDD DL1 M CL2 CL1 DR1 DL2 DR2 Seg 1-96 Regsister Regsister Regsister Regsister Regsister VR Dout /square6 Application Circuit : (2Line x 16 Chinese Word)
Ver 1.6 11/11 2005/05/24 ST7921 Specification Revision History Version Date Description C1.6 2005/05/24 1. Modify Operating Temperature=-20 0C ~85 0C