ST7533

ST7533 SITRONIX | Alldatasheet

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33 x 96 Dot Matrix LCD Controller/Driver Ver 1.0 1/60 2003/07/21 FFEEAATTUURREESS z Direct display of RAM data through the display data RAM. z RAM capacity : 33 x 96 = 3168 bits z Display duty selectable by select pin 1/33 duty : 33 common x 96 segment 1/17 duty : 17 common x 96 segment z High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported. z Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V 5 voltage regulation internal resistor ratio set. z Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) z Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of 2X/3X/4X , where the step-up voltage reference power supply can be input externally). High-accuracy voltage adjustment circuit (Thermal gradient –0.15%/°C ) V 5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. z CR oscillator circuit equipped internally (external clock can also be input) z Extremely low power consumption Operating power when the built-in power supply is used (an example) 70uA (V DD – VSS = VDD – VSS2 =3.0 V, Quad voltage, Conditions: When displays pattern OFF and the normal mode is selected. z Power supply operate on the low 1.8 voltage Logic power supply V DD – VSS = 1.8V to 3.3V (+10% Range) Boost reference voltage: VDD – VSS2 = 1.8V to 3.3V Booster maximum voltage limited VOUT= -13V (+10% Range) Liquid crystal drive power supply: V DD – V5 = 4.0V to 13.0 V z Wide range of operating temperatures: –40 to 85°C z CMOS process z These chips not designed for resistance to light or resistance to radiation. GGEENNEERRAALL DDEESSCCRRIIPPTTIIOONN The ST7533 is a single-chip dot matrix LCD drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a LCD drive signal independent of the microprocessor. Because the chips in the ST7533 contain 33x96 bits of display data RAM and there is a 1-to-1 correspondence between the LCD panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The ST7533 chips contain 33 common output circuits and 96 segment output circuits, so that a single chip can drive a 33x96 dot display (capable of displaying 8 columnsx4 rows of a 16x16 dot kanji font). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power LCD driver power supply, resistors for LCD driver power voltage adjustment and a display clock CR oscillator circuit, the ST7533 can be used to create the lowest power display system with the fewest components for high-performance portable devices. PART NO. V RS temperature gradient V RS range

Ver 1.0 2/60 2003/07/21 ST7533 Pad Arrangement Chip Size: 7240μm x 1,000 μm Origin: Chip Center Bump Pitch: 69.1μm(Min.) Bump Size: PAD No. 001〜005 49.1 μm x 70.5μm PAD No. 006 〜064 56 μm x 60μm PAD No. 065 〜070 51 μm x 60μm PAD No. 071〜083 56 μm x 60μm PAD No. 084 〜088 49.1 μm x 70.5μm PAD No. 089 〜100 70.5 μm x 49.1μm PAD No. 101 〜196 49.1 μm x 70.5μm PAD No. 197 〜208 70.5 μm x 49.1μm Bump Height: 18μm(Typ) Chip Thickness: 660μm 25um 30um 25um 30um 40um 30um 30um 30um 30um X Y (0,0) ST7533 PAD DIAGRAM

• •• 088 084 083 071 070 065 064 006 005 001 089 100 208 197 (-3405, 435) (3266, 162) 101 196 (3385,435) (-3312,-175) 15 um 15 um 15 um 15 um um um um um

Ver 1.0 3/60 2003/07/21 Pad Center Coordinates (1/33 Duty) PAD No. PIN Name X Y

1 COM[28] 3290 409

2 COM[29] 3221 409

3 COM[30] 3152 409

4 COM[31] 3083 409

5 COMS1 3014 409

6 FRS 2919 414

7 FR 2843 414

8 CL 2767 414

10 VSS 2614 414

12 CS2 2462 414

13 VDD 2386 414

15 A0 2234 414

16 VSS 2157 414

17 /WR(R/W) 2081 414 18 /RD(E) 2005 414

19 VDD 1929 414

20 D0 1853 414

21 D1 1777 414

22 D2 1701 414

23 D3 1624 414

24 D4 1548 414

25 D5 1472 414

26 D6 1396 414

27 D7 1320 414

28 VDD 1244 414

29 VDD 1168 414

30 VDD 1091 414

31 VSS 1015 414

32 VSS 939 414

33 VSS2 863 414

34 VSS2 787 414

35 VOUT 711 414

36 VOUT 634 414

37 CAP3- 558 414

38 CAP3- 482 414

39 CAP1+ 406 414

40 CAP1+ 330 414

41 CAP1- 254 414

42 CAP1- 178 414

43 CAP2- 101 414

44 CAP2- 25 414

45 CAP2+ -51 414

46 CAP2+ -127 414

47 VSS -203 414

48 VSS -279 414

49 VRS -355 414

50 VDD -432 414

51 VDD -508 414

52 V1 -584 414

No. PIN Name X Y

53 V1 -660 414

54 V2 -736 414

55 V2 -812 414

56 V3 -889 414

57 V3 -965 414

58 V4 -1041 414

59 V4 -1117 414

60 V5 -1193 414

61 V5 -1269 414

62 VR -1345 414

63 VDD -1422 414

64 VDD -1498 414

65 TEST0 -1571 414

66 TEST1 -1642 414

67 TEST2 -1713 414

68 TEST3 -1784 414

69 TEST4 -1855 414

70 TEST5 -1926 414

71 VDD -2000 414

72 M/S -2076 414

73 CLS -2152 414

74 VSS -2228 414

75 C86 -2305 414

76 P/S -2381 414

77 VDD -2457 414

79 VSS -2609 414

80 IRS -2685 414

81 VDD -2762 414

82 SEL1 -2838 414

83 VSS -2914 414

84 COM[15] -3011 409

85 COM[14] -3080 409

86 COM[13] -3150 409

87 COM[12] -3219 409

88 COM[11] -3288 409

89 COM[10] -3529 351

90 COM[9] -3529 282

91 COM[8] -3529 213

92 COM[7] -3529 144

93 COM[6] -3529 75

94 COM[5] -3529 6

95 COM[4] -3529 -64

96 COM[3] -3529 -133

97 COM[2] -3529 -202

98 COM[1] -3529 -271

99 COM[0] -3529 -340

100 COMS2 -3529 -409

101 SEG[0] -3280 -409

102 SEG[1] -3211 -409

103 SEG[2] -3142 -409

104 SEG[3] -3073 -409

Ver 1.0 4/60 2003/07/21 PAD No. PIN Name X Y

105 SEG[4] -3004 -409

106 SEG[5] -2935 -409

107 SEG[6] -2866 -409

108 SEG[7] -2797 -409

109 SEG[8] -2728 -409

110 SEG[9] -2658 -409

111 SEG[10] -2589 -409

112 SEG[11] -2520 -409

113 SEG[12] -2451 -409

114 SEG[13] -2382 -409

115 SEG[14] -2313 -409

116 SEG[15] -2244 -409

117 SEG[16] -2175 -409

118 SEG[17] -2106 -409

119 SEG[18] -2037 -409

120 SEG[19] -1967 -409

121 SEG[20] -1898 -409

122 SEG[21] -1829 -409

123 SEG[22] -1760 -409

124 SEG[23] -1691 -409

125 SEG[24] -1622 -409

126 SEG[25] -1553 -409

127 SEG[26] -1484 -409

128 SEG[27] -1415 -409

129 SEG[28] -1346 -409

130 SEG[29] -1276 -409

131 SEG[30] -1207 -409

132 SEG[31] -1138 -409

133 SEG[32] -1069 -409

134 SEG[33] -1000 -409

135 SEG[34] -931 -409

136 SEG[35] -862 -409

137 SEG[36] -793 -409

138 SEG[37] -724 -409

139 SEG[38] -655 -409

140 SEG[39] -585 -409

141 SEG[40] -516 -409

142 SEG[41] -447 -409

143 SEG[42] -378 -409

144 SEG[43] -309 -409

145 SEG[44] -240 -409

146 SEG[45] -171 -409

147 SEG[46] -102 -409

148 SEG[47] -33 -409

149 SEG[48] 36 -409

150 SEG[49] 106 -409

151 SEG[50] 175 -409

152 SEG[51] 244 -409

153 SEG[52] 313 -409

154 SEG[53] 382 -409

155 SEG[54] 451 -409

156 SEG[55] 520 -409

No. PIN Name X Y

157 SEG[56] 589 -409

158 SEG[57] 658 -409

159 SEG[58] 727 -409

160 SEG[59] 797 -409

161 SEG[60] 866 -409

162 SEG[61] 935 -409

163 SEG[62] 1004 -409

164 SEG[63] 1073 -409

165 SEG[64] 1142 -409

166 SEG[65] 1211 -409

167 SEG[66] 1280 -409

168 SEG[67] 1349 -409

169 SEG[68] 1418 -409

170 SEG[69] 1488 -409

171 SEG[70] 1557 -409

172 SEG[71] 1626 -409

173 SEG[72] 1695 -409

174 SEG[73] 1764 -409

175 SEG[74] 1833 -409

176 SEG[75] 1902 -409

177 SEG[76] 1971 -409

178 SEG[77] 2040 -409

179 SEG[78] 2109 -409

180 SEG[79] 2179 -409

181 SEG[80] 2248 -409

182 SEG[81] 2317 -409

183 SEG[82] 2386 -409

184 SEG[83] 2455 -409

185 SEG[84] 2524 -409

186 SEG[85] 2593 -409

187 SEG[86] 2662 -409

188 SEG[87] 2731 -409

189 SEG[88] 2800 -409

190 SEG[89] 2870 -409

191 SEG[90] 2939 -409

192 SEG[91] 3008 -409

193 SEG[92] 3077 -409

194 SEG[93] 3146 -409

195 SEG[94] 3215 -409

196 SEG[95] 3284 -409

197 COM[16] 3529 -409

198 COM[17] 3529 -340

199 COM[18] 3529 -271

200 COM[19] 3529 -202

201 COM[20] 3529 -133

202 COM[21] 3529 -64

203 COM[22] 3529 6

204 COM[23] 3529 75

205 COM[24] 3529 144

206 COM[25] 3529 213

207 COM[26] 3529 282

208 COM[27] 3529 351

Ver 1.0 5/60 2003/07/21 Pad Center Coordinates (1/17 Duty) PAD No. PIN Name X Y

1 COM[12] 3290 409

2 COM[13] 3221 409

3 COM[14] 3152 409

4 COM[15] 3083 409

17 /WR(R/W) 2081 414 18 /RD(E) 2005 414 No. PIN Name X Y

84 Reserve -3011 409

85 Reserve -3080 409

86 Reserve -3150 409

87 Reserve -3219 409

88 Reserve -3288 409

89 Reserve -3529 351

90 Reserve -3529 282

91 Reserve -3529 213

Ver 1.0 6/60 2003/07/21 PAD No. PIN Name X Y No. PIN Name X Y

197 Reserve 3529 -409

198 Reserve 3529 -340

199 Reserve 3529 -271

200 Reserve 3529 -202

201 Reserve 3529 -133

202 Reserve 3529 -64

203 Reserve 3529 6

204 Reserve 3529 75

205 COM[8] 3529 144

206 COM[9] 3529 213

207 COM[10] 3529 282

208 COM[11] 3529 351

Ver 1.0 7/60 2003/07/21 BBLLOOCCKK DDIIAAGGRRAAMM COMS COM31 COM0 SEG95 SEG0 DOF MPU INTERFACE ( Parallel and Serial ) Command decoder Voltage Regulator circuit Voltage follower circuit Voltage booster circuit Status Bus holder DISPLAY DATA RAM

33 X 96 = 3186 Bits

Display data latch circuit Oscillator circuit Display timing generator circuit

96 SEGMENT

33 COMMON

COM output control circuit COMS VDD HPM VR VRS VOUT IRS CS1 CS2 E(RD) RW(WR) P/S C86 /RES SEL1 D6(SCL) D7(SI) FRS M/S CL FR CLS Power Supply Circuit CAP1+ CAP1- CAP2- CAP2+ CAP3+ VSS VSS2

Ver 1.0 8/60 2003/07/21 PPIINN DDEESSCCRRIIPPTTIIOONNSS Power Supply Pins Pin Name I/O Function No. of Pins VDD Power Supply Shared with the MPU power supply terminal Vcc. 12 VSS Power Supply This is a 0V terminal connected to the system GND. 9 VSS2 Power Supply This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. 2 VRS Power Supply This is the internal-output VREG power supply for the LCD power supply voltage regulator. 1 V1, V2, V3, V4, Power Supply This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. VDD (= V0) ≧V1 ≧V2 ≧V3 ≧V4 ≧V5 When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. 1/33 DUTY 1/17 DUTY 1/6*V5,1/5*V5 2/6*V5,2/5*V5 4/6*V5,3/5*V5 5/6*V5,4/5*V5 1/6*V5,1/5*V5 2/6*V5,2/5*V5 4/6*V5,3/5*V5 5/6*V5,4/5*V5 LCD Power Supply Pins Pin Name I/O Function No. of Pins CAP1+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. 2 CAP1– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 CAP2+ O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. 2 CAP2– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. 2 CAP3– O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. 2 VOUT O DC/DC voltage converter. Connect a capacitor between this terminal and VSS. 2 VR I Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. IRS = “L” : the V5 voltage regulator internal resistors are not used . IRS = “H” : the V5 voltage regulator internal resistors are used .

Ver 1.0 9/60 2003/07/21 System Bus Connection Pins Pin Name I/O Function No. of Pins D5 to D0 D6 (SCL) D7 (SI) I/O This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = “L”) : D7 : serial data input (SI) ; D6 : the serial clock input (SCL). D0 to D5 are set to high impedance. When the chip select is not active, D0 to D7 are set to high impedance. A0 I This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = “H”: Indicates that D0 to D7 are display data. A0 = “L”: Indicates that D0 to D7 are control data. /RES I When /RES is set to “L,” the settings are initialized. The reset operation is performed by the /RES signal level. /CS1 CS2 I This is the chip select signal. When /CS1 = “L” and CS2 = “H,” then the chip select becomes active, and data/command I/O is enabled. /RD (E) I

• When connected to an 8080 MPU, this is active LOW. (E) This pin is connected to the /RD signal of the 8080 MPU, and the ST7533 series data bus is in an output status when this signal is “L”.
• When connected to a 6800 Series MPU, this is active HIGH. This is the 6800 Series MPU enable clock input terminal. /WR (R/W) I
• When connected to an 8080 MPU, this is active LOW. (R/W) This terminal connects to the 8080 MPU/WR signal. The signals on the data bus are latched at the rising edge of the /WR signal.
• When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = “H”: Read. When R/W = “L”: Write. C86 I This is the MPU interface switch terminal. C86 = “H”: 6800 Series MPU interface. C86 = “L”: 8080 MPU interface. P/S I This is the parallel data input/serial data input switch terminal. P/S = “H”: Parallel data input. P/S = “L”: Serial data input. The following applies depending on the P/S status: When P/S = “L”, D0 to D5 fixed to either “H”. /RD (E) and /WR (R/W) are fixed to either “H” or “L”. With serial data input, It is impossible read data from RAM . P/S Data/Command Data Read/Write Serial Clock “H” A0 D0 to D7 /RD, /WR X “L” A0 SI (D7) Write only SCL (D6)

Ver 1.0 10/60 2003/07/21 Pin Name I/O Function No. of Pins CLS I Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = “H” : used Internal oscillator circuit . CLS = “L” : used external clock input .(internal oscillator is disable) When CLS = “L”, input the display clock through the CL terminal. M/S I This terminal selects the master/slave operation for the ST7533 Series chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation input the timing signals required for the liquid crystal display, Synchronizing the liquid crystal display system. M/S = “H” Master operation M/S = “L” Slave operation M/S CLS Oscillator Circuit Power Supply Circuit CL FR FRS DOF “H” “H” “L” Enabled Disabled Enabled Enabled Output Input Output Output Output Output Output Output “L” “H” “L” Disabled Disabled Disabled Disabled Input Input Input Input Output Output Input Input CL I/O This is the display clock input terminal The following is true depending on the M/S and CLS status. M/S CLS CL “H” “H” “L” Output Input “L” “H” “L” Input Input FR O This is the liquid crystal alternating current signal terminal. 1 /DOF O This is the LCD blanking control terminal. 1 FRS O This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON and is used in conjunction with the FR terminal. IRS I This terminal selects the resistors for the V5 voltage level adjustment. IRS = “H”: Use the internal resistors IRS = “L”: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal /HPM I This is the power control terminal for the power supply circuit for liquid crystal drive. /HPM = “H”: Normal mode /HPM = “L”: High power mode SEL1 I These pins are DUTY selection. SEL 1 DUTY BIAS 0 1/33 1/5 or 1/6 1 1/17 1/5 or 1/6 TEST0 ~ 5 I These are terminals for IC testing . TEST0 (PAD No.65) must connect to VDD TEST1 ~ 5 must floating

Ver 1.0 11/60 2003/07/21 LCD Driver Pins Pin Name I/O Function No. of Pins SEG0 to SEG95 O These are the LCD segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from V DD, V2, V3, and V5. Output Voltage RAM DATA FR Normal Display Reverse Display H H V DD V 2 H L V 5 V 3 L H V 2 V DD L L V 3 V 5 Power save ---- V DD COM0 to COMn O These are the LCD common drive outputs. Through a combination of the contents of the scan data and with the FR signal, a single level is selected from V DD, V1, V4, and V5. Part No. COM TOTAL

33 DUTY COM0 ~ COM31 32

17 DUTY COM0 ~ COM15 16

Scan Data FR Output Voltage H H V 5 H L V DD L H V 1 L L V 4 Power save ---- V DD COMS O These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used.

Ver 1.0 12/60 2003/07/21 DDEESSCCRRIIPPTTIIOONN OOFF FFUUNNCCTTIIOONNSS The MPU Interface Selecting the Interface Type With the ST7533 chips, data transfers are done through an 8-bit parallel data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/ S terminal polarity to the “H” or “L” it is possible to select either parallel data input or serial data input as shown in Table 1. Table 1 P/S /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0 H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0 L: Serial Input /CS1 CS2 A0 — — — SI SCL (HZ) “—” indicates fixed to either “H” or to “L” The Parallel Interface When the parallel interface has been selected (P/S =“H”), then it is possible to connect directly to either an 8080-system MPU or a 6800 Series MPU (shown in Table 2) by selecting the C86 terminal to either “H” or to “L”. Table 2 C86 (P/S=H) /CS1 CS2 A0 /RD /WR D7~D0 H: 6800 Series /CS1 CS2 A0 E R/W D7~D0 L: 8080 Series /CS1 CS2 A0 /RD /WR D7~D0 Moreover, data bus signals are recognized by a combination of A0, /RD (E), /WR (R/W) signals, as shown in Table 3. Table 3 Shared 6800 Series 8080 Series A0 R/W /RD /WR Function 1 1 0 1 Reads the display data 1 0 1 0 Writes the display data 0 1 0 1 Status read 0 0 1 0 Write control data (command)

Ver 1.0 13/60 2003/07/21 The Serial Interface When the serial interface has been selected (P/S = “L”) then when the chip is in active state (/CS1 = “L” and CS2 = “H”) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth se rial clock for the processing. The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = “H”, the data is display data, and when A0 = “L” then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart. 1 2 3 4 5 6 7 8 9 1 01 11 21 31 4 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 CS1 CS2 SI SCL Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. The Chip Select The ST7533 have two chip select terminals: /CS1 and CS2. The MPU interface or the serial interface is enabled only when /CS1 = “L” and CS2 = “H”. When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, /RD, and /WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. The Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the ST7533. Wait time may not be considered. And, in the ST7533, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2.

Ver 1.0 14/60 2003/07/21 The Busy Flag When the busy flag is “1” it indicates that the ST7533 is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. N N+1 N+2 N+3 N+3N+2N+1N DATA BUS Holder Write Signal WR MPUInternal Timing Writing DATA WR MPU Reading N N n n+1 RD Preset N Increment N+1 N+2 n n+1N n+2 Address Preset Read Signal Column Address Bus Holder Internal Timing Address Set Dummy Read Data Read #n Data Read #n+1 Figure 2

Ver 1.0 15/60 2003/07/21 Display Data RAM The display data RAM stores the dot data for the LCD. It has a 33 (4 page x 8 bit +1) x 96 bit structure. as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the LCD display common direction, there are few constraints at the time of display data transfer when multiple ST7533 are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). Display data RAM COM0 COM1 COM2 COM3 COM4 Liquid crystal display Figure 3 The Page Address Circuit Page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special RAM for icons, and only display data D0 is used. (see Figure 4) The Column Addresses The display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementing of column addresses stops with 5FH. Because the column address is independent of the page address, when moving, for example, from page 0 column 5FH to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. As is shown in Figure 4, Table 4 SEG Output ADC SEG0 SEG 95 (D0) “0” (D0) “1” 0 (H) → Column Address → 5F(H) 5F(H) ← Column Address ← 0 (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM31 output for ST7533 , the detail is shown page.11 The display area is a 33 line area for the ST7533. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed.

Ver 1.0 16/60 2003/07/21 Page Address D3 D2 D1 D0 Data Line Address When the common output is normal COM Output D0 00H COM0 D1 01H COM1 D2 02H COM2 D3 03H COM3 D4 04H COM4 D5 05H COM5 D6 06H COM6 0 0 0 0 D 7 Page 0 07H COM7 D0 08H COM8 D1 09H COM9 D2 0AH COM10 D3 0BH COM11 D4 0CH COM12 D5 0DH COM13 D6 0EH COM14 0 0 0 1 D 7 Page 1 0FH COM15 D0 10H COM16 D1 11H COM17 D2 12H COM18 D3 13H COM19 D4 14H COM20 D5 15H COM21 D6 16H COM22 0 0 1 0 D 7 Page 2 17H COM23 D0 18H COM24 D1 19H COM25 D2 1AH COM26 D3 1BH COM27 D4 1CH COM28 D5 1DH COM29 D6 1EH COM30 0 0 1 1 D 7 Page 3

1 F H

s Regardless of the display start line address, 1/33duty => 32th line, 1/17duty =>16th line. S87 S88 S89 S90 S91 S92 S93 S94 S95 LCD Out Figure 4

Ver 1.0 17/60 2003/07/21 The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S= “H” and CLS = “H”. When CLS = “L” the oscillation stops, and the external clock is input through the CL terminal. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Two-frame alternating current drive waveform 32 33 1 2 3 4 5 6 28 29 30 31 32 33 1 2 3 4 5 6 VDD COM0 VDD COM1 VDD RAM Data SEGn FR CL Figure 5

Ver 1.0 18/60 2003/07/21 The Common Output Status Select Circuit In the ST7533 chips, the COM output scan direction can be selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized. Table 6 COM Scan Direction Status 1/33 DUTY 1/17 DUTY Normal Reverse COM0 → COM31 COM31 → COM0 COM0 → COM15 COM15 → COM0 com[0:15] Common output pins com[16:31] Duty Com dir 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 coms 0 com[0:7] com[8:15] com[16:23] com[23:31] coms 1/33 1 com[31:23] com[23:16] com[15:8] com[7:0] coms 0 com[0:7] reserve com[8:15] coms 1/17 1 com[15:8] reserve com[7:0] coms The LCD Driver Circuits These are a 129-channel, that generate four voltage levels for driving the LCD . The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure-6 shows examples of the SEG and COM output wave form.

Ver 1.0 19/60 2003/07/21 SEG 0 1 2 3 4 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 VDD VSS VDD VDD VDD VDD VDD VDD -V1 -V2 -V3 -V4 -V5 VDD -V1 -V2 -V3 -V4 -V5 FR COM0 COM1 COM2 SEG0 SEG1 COM0 to SET0 COM0 to SET1 Figure 6

Ver 1.0 20/60 2003/07/21 The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate t he voltage levels required for the LCD drivers. They are Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations. Table 7 bit function Status “1” “0” Booster circuit control bit Voltage regulator circuit control bit (V/R circuit) Voltage follower circuit control bit (V/F circuit) ON OFF ON OFF ON OFF The Control Details of Each Bit of the Power Control Set Command Table 8 Use Settings D2 D1 D0 Voltage booster Voltage regulator Voltage follower External voltage input Step-up voltage Only the internal power supply is used 1 1 1 ON ON ON VSS2 Used Only the voltage regulator circuit and the voltage follower circuit are used 0 1 1 OFF ON ON V OUT, VSS2 Open Only the V/F circuit is used 0 0 1 OFF OFF ON V5, V SS2 Open Only the external power supply is used 0 0 0 OFF OFF OFF V 1 to V5 Open Reference Combinations * The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–. * While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the ST7533 chips it is possible to product a 2X,3X or 4X step-up of the VDD – VSS2 voltage levels. 4X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, and between VSS2 and VOUT, to produce a voltage level in the negative direction at the VOUT terminal that is 4 times the voltage level between VDD and VSS2. 3X step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2– and between VSS2 and VOUT, and short and shor between CAP3– and VOUT to produce a voltage level in the negative direction at the VOUT terminal that is 3 times the voltage difference between VDD and VSS2. 2X step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between VSS2 and VOUT, leave CAP2+ open, and short between CAP2–, CAP3– and VOUT to produce a voltage in the negative direction at the VOUT terminal that Is twice the voltage between VDD and VSS2. The step-up voltage relationships are shown in Figure 7

Ver 1.0 21/60 2003/07/21 VSS2 VOUT CAP3- CAP1+ CAP1- CAP2- CAP2+ ST7533 VSS2 VOUT CAP3- CAP1+ CAP1- CAP2- CAP2+ ST7533 C1 C1 VSS2 VOUT CAP3- CAP1+ CAP1- CAP2- CAP2+ ST7533 OPEN 4x step-up voltage circuit 3x step-up voltage circuit 2x step-up voltage circuit VDD=0V VSS2=-3V VOUT=4xVSS2=-12V 4x step-up voltage relationships VDD=0V VSS2=-3V VOUT=3xVSS2=-9V 3x step-up voltage relationships VDD=0V VSS2=-3V VOUT=2xVSS2=-6V 2x step-up voltage relationships Figure 7 * The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the LCD driver voltage V5 through the voltage regulator circuit. Because the ST7533 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V 5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. (VREG thermal gradients approximate -0.15%/°C)

Ver 1.0 22/60 2003/07/21 The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the LCD driver voltage V5 through the voltage regulator circuit. Because the ST7533 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V 5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. VREG thermal gradients approximate -0.15%/°C) (A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V 5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V 5 voltage can be calculated using equation A-1 over the range where | V 5 | < | VOUT |. Figure 8 Rb Ra+1 VEVV5 = = () Rb Ra+1 (1- α 162 ) VREG [∵V EV = (1- α 162 ) VREG] Internal Ra Internal Rb VEV(constant voltage supply+electronic volume) VDD

Ver 1.0 23/60 2003/07/21 VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9. Table 9 Part no. Equipment Type Thermal Gradient VREG ST7533 Internal Power Supply –0.15 %/°C –2.1V α is set to 1 level of 64 possible levels by the electronic vo lume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for α depending on the electronic volume register settings. Rb/Ra is the V 5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V 5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V5 voltage regulator internal resistor ratio register. Table 10 D5 D4 D3 D2 D1 D0 α 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 V5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table 11 Register ST7533 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Figures 9, 10 show V5 voltage measured by values of the internal resistance ratio resistor for V5 voltage adjustment and electric volume resister for each temperature grade model.

Ver 1.0 24/60 2003/07/21 -10 -11 -12 -13 -14 -15 00H 1FH 3FH UNIT:V 000 001 010 011 100 101 110 111 V5 voltage regulator internal resistor ratio set D2,D1,D0 Electronic volume registered D5 ~ D0 Ta = 25 °C and booster off ,regulator,follower on VSS=-3V Figure 9 : (1) For ST7533 the Thermal Gradient = -0.15%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. Setup example: When selecting Ta = 25°C and V5 = –7V for an ST7533 on which Temperature gradient = –0.15%/°C. Using Figure 9 and the equation A-1, the following setup is enabled. At this time, the variable range and the notch width of the V5 voltage is, as shown Table 13, as dependent on the electronic volume. Table 12 Register Contents D5 D4 D3 D2 D1 D0 For V5 voltage regulator Electronic Volume — — — 0 1 0 1 0 0 1 0 1 Table 13 V5 Min Typ Max Units Variable Range Notch width –8.4 (63 levels) –7.0 (central value) –5.1 (0 level) [V] 51 [mV]

Ver 1.0 25/60 2003/07/21 (B) When an External Resistance is Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V 5 can also be set without using the V5 voltage regulator internal resistors (IRS terminal = “L”) by adding resistors Ra’ and Rb’ between VDD and VR, and between VR and V5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V through commands. In the range where | V 5 | < | V OUT |, the V 5 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’. Rb' Ra'+1 VEVV5 = = () Rb' Ra'+1 (1- α 162 ) VREG [∵V EV = (1- α 162 ) VREG] External resistor Ra' VEV(fixed voltage power supply+electronic volume) VDD External resistor Rb' Figure 11 Setup example: When selecting Ta = 25°C and V5 = –7 V for ST7533 the temperature gradient = –0.15%/°C. When the central value of the electron volume register is VREG = –2.1V so, according to equation B-1, = () Rb' Ra'+1 (1- 31 162 ) (-2.1)-7V = () Rb' Ra'+1 (1- α 162 ) VREGV5 Moreover, when the value of the current running through Ra’ and Rb’ is set to 5 uA, Consequently, by equations B-2 and B-3, =Rb' Ra' 3.12 Ra' = 340kΩ Rb' = 1060kΩ At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14. Table 14 V5 Min Typ Max Units Variable Range Notch width –8.6 (63 levels) –7.0 (central value) –5.3 (0 level) [V] 52 [mV]

Ver 1.0 26/60 2003/07/21 (C) When External Resistors are Used (The V5 Voltage Regulator Internal Resistors Are Not Used) (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V 5. In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V 5 by commands to adjust the liquid crystal display brightness. In the range where | V 5 | < | V OUT | the V 5 voltage can be calculated by equation C-1 below based on the R 1 and R2 (variable resistor) and R 3 settings, where R 2 can be subjected to fine adjustments (Δ R2). R3+R2-ΔR2 R1+ΔR2+1 VEVV5 = = ()+1 (1- α 162 ) VREG [∵V EV = (1- α 162 ) VREG] R3+R2-ΔR2 R1+ΔR2 External resistor R1 VEV(fixed voltage power supply+electronic volume) VDD External resistor R3 VR ΔR2 External resistor R2 Rb' Ra' Figure 12 Setup example: When selecting Ta = 25°C and V5 = –5 to –9 V (using R2) for an ST7533 the temperature gradient = –0.15%/°C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and V REG = –2.1 V so, according to equation C-1, when Δ R2 = 0 Ω, in order to make V5 = –9 V, R3+R2 R1+1-9V= ) (1- 31 162 ) (-2.1) When ΔR2 = R2, in order to make V = –5 V, 162 ) (-2.1) When the current flowing VDD and V5 is set to 5 uA, With this, according to equation C-2, C-3 and C-4, R1 = 264kΩ R2 = 211kΩ R3 = 925kΩ The V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15. Table 15 V5 Min Typ Max Units Variable Range Notch width –8.7 (63 levels) –7.0 (central value) –5.3 (0 level) [V] 53 [mV]

Ver 1.0 28/60 2003/07/21 Reference Circuit Examples Figure 15 shows reference circuit examples. 1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor is used. (Example where VSS2 = VSS, with 4x step-up) (2) When the voltage regulator internal resistor is not used. (Example where VSS2 = VSS, with 4x step-up) VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7533 IRS M/S V DD VDD VSS VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7533 IRS M/S V DD VSS VDD CAP4- CAP5- CAP4- CAP5- 2. When the voltage regulator circuit and V/F circuit alone are used (1) When the V 5 voltage regulator internal resistor is not used. (2) When the V 5 voltage regulator internal resistor is used. VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7533 IRS M/S V DD VSS VDD VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7533 IRS M/S V DD VDD VSS External power supply External power supply CAP4- CAP5- CAP4- CAP5-

Ver 1.0 29/60 2003/07/21 3. When the V/F circuit alone is used 4. When the built-in power is not used VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7533 IRS M/S V DD VDD VSS External power supply VSS2 VOUT CAP3- CAP1+ CAP1- CAP2+ CAP2- V VR VDD ST7533 IRS M/S VDD VDD VSS External power supply CAP4- CAP5- CAP4- CAP5- 5. When the built-in power circuit is used to drive a liquid crystal panel heavily loaded with AC or DC, it is recommended to connect an external resistor to stabilize potentials of V 1, V 2, V 3 and V 4 which are output from the built-in voltage follower. Examples of shared reference settings When V 5 can vary between –8 and 12 V ST7533 VDD,V0 R4 R4 R4 R4 Reference set value R4: 100KΩ ~ 1MΩ It is recommended to set an optimum resistance value R4 taking the liquid crystal display and the drive waveform. Figure 15 * 1. Because the VR terminal input impedance is high, use short leads and shielded lines. * 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings:

• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value.
• Next turn all the power supplies ON and determine C1. Item Set value units 1.0 to 4.7 0.1 to 4.7 uF uF C1 and C2 are determined by the size of the LCD being driven

Ver 1.0 30/60 2003/07/21 The Reset Circuit When the /RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = “L”) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: 1/33 DUTY = 1/6 bias 1/17 DUTY = 1/5 bias 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = “L”) 8. Power saving clear 9. V 5 voltage regulator internal resistors Ra and Rb separation 10. Output conditions of SEG and COM terminals SEG=VDD , COM=VDD 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) = (0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V 5 voltage regulator internal resistor ratio set mode clear 18. Electronic volume register set mode clear Electronic volume register : 19. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the /RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control sig nal from the MPU is in the high impedance, an over current may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on ST7533,it is necessary that /RES is “H” when the external liquid crystal power supply is turned on. This IC has the function to discharge V 5 when /RES is “L,” and the external power supply short-circuits to V DD when /RES is “L.” While /RES is “L,” the oscillator and the display timing generator stop, and the CL, FR, FRS and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected. The V DD level is output from the SEG and COM output terminals. This means that an internal resistor is connected between V DD and V5. When the internal liquid crystal power supply circuit is not used on other models of ST7533 series, it is necessary that /RES is “L” when the external liquid crystal power supply is turned on. While /RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR, FRS and /DOF terminals are fixed to “H.” The terminals D0 to D7 are not affected.

Ver 1.0 31/60 2003/07/21 CCOOMMMMAANNDDSS The ST7533 identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signal s. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the /RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H” signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. <Explanation of Commands> Display ON/OFF This command turns the display ON and OFF. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 1 1 1 1 Display ON Display OFF When the display OFF command is executed when in the disp lay all points ON mode, power saver mode is entered. See the section on the power saver for details. Display Start Line Set This command is used to specify the disp lay start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Line address 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Page address 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0

Ver 1.0 32/60 2003/07/21 Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 5FH. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 Column address High bits → Low bits → 0 1 0 0 0 0 1 A7 A6 A5 A4 0 0 0 0 0 0 0 0

0 A3 A2 A1 A0 0 0 0 0 0 0 0 1

0 0 1 BUSY ADC ON/OFF RESET 0 0 0 0 BUSY BUSY = 1: it indicates that either processing is occurring internally or a reset condition is in process. BUSY = 0: A new command can be accepted . if the cycle time can be satisfied, there is no need to check for BUSY conditions. ADC This shows the relationship between the column address and the segment driver. 0: Normal (column address n ↔ SEG n) 1: Reverse (column address 95-n ↔ SEG n) (The ADC command switches the polarity.) ON/OFF ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) RESET This indicates that the chip is in the process of initialization either because of a /RES signal or because of a reset command. 0: Operating state 1: Reset in progress Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write data

Ver 1.0 33/60 2003/07/21 Display Data Read This command reads 8-bit data from the specified display dat a RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read data ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (Figure 4) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 0 0 0 Normal Reverse Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 1 1 0 RAM Data “H” LCD ON voltage (normal) RAM Data “L” LCD ON voltage (reverse) Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority ov er the display normal/reverse command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Setting 0 1 0 1 0 1 0 0 1 0 0 Normal display mode Display all points ON When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the Power Save section.

Ver 1.0 34/60 2003/07/21 LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. Select Status E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1/33duty 1/17duty 1/6 bias 1/6 bias 0 1 0 1 0 1 0 0 0 1 0 1 1/5 bias 1/5 bias Read/Modify/Write This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. END Page address set Column address set Dummy read Data read Data write Changes Finished ? Read-modify-write cycle NO YES Figure 24 Command Sequence For read modify write

Ver 1.0 35/60 2003/07/21 Figure 25 End This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 Reset This command initializes the display start line, the column address, the page address, the common output mode, the V5 voltage regulator internal resistor ratio, the el ectronic volume, and the static indicator are reset, and the read/modify/write mode an d test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details. The reset operation is performed after the reset command is entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 0 The initialization when the power supply is applied must be done through applying a reset signal to the /RES terminal. The reset command must not be used instead. Common Output Mode Select This command can select the scan direction of the COM outp ut terminal. For details, see the function explanation in “Common Output Mode Select Circuit.” Selected Mode E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1/33duty 1/17duty 0 1 0 1 1 0 0 0 * * * Normal Reverse COM0→COM31 COM31→COM0 COM0→COM15 COM15→COM0 * Disabled bit Column address Read-modify-write mode set N N+1 N+2 N+3 N+m N End Return

Ver 1.0 36/60 2003/07/21 Power Controller Set This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode 0 0 1 0 1 0 Booster circuit: OFF Booster circuit: ON Voltage regulator circuit: OFF Voltage regulator circuit: ON 0 1 0 Voltage follower circuit: OFF Voltage follower circuit: ON V5 Voltage Regulator Internal Resistor Ratio Set This command sets the V 5 voltage regulator internal resistor ratio. For det ails, see the function explanation is “The Voltage Regulator circuit " and table 11 . E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Rb/Ra Ratio 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 Small Large The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V5 through the output from the voltage regulator circuits of the in ternal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1

Ver 1.0 37/60 2003/07/21 Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 | V5 | 0 1 0 * * 0 0 0 0 0 1 * * 0 0 0 0 1 0 * * 0 0 0 0 1 1 * * 1 1 1 1 1 0 * * 1 1 1 1 1 1 Small Large * Inactive bit (set “0”) When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) The Electronic Volume Register Set Sequence Figure 26 Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indica tor liquid crystal drive electrodes is con nected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paire d with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.) Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Static Indicator 0 1 0 1 0 1 0 1 1 0 0 OFF ON electronic volume mode set electronic volume register set Set complete ? YES NO Electronic volume mode clear

Ver 1.0 39/60 2003/07/21 Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1. The oscillator circuit and the LCD power supply circuit are halted. 2. All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level. Standby Mode The duty LCD display system operations are halted and only the st atic drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a V DD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the vari ous levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The ST7533 series chips have a liquid crystal display blanking control terminal /DOF. This terminal enters an “L” state when the power saver mode is launched. Using the output of /DOF, it is possible to stop the function of an external power supply circuit. NOP Non-OPeration Command E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 1 Test This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a “L” signal to the /RES input by the reset command or by using an NOP. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 1 1 * * * Inactive bit Note: The ST7533 maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the ST7533 . Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise.

Ver 1.0 40/60 2003/07/21 Table 16: Table of ST7533 Commands (Note) *: disabled data Command Code Command A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function (1) Display ON/OFF 0 1 0 1 0 1 0 1 1 1 0 LCD display ON/OFF 0: OFF, 1: ON (2) Display start line set 0 1 0 0 1 Display start address Sets the display RAM display start line address (3) Page address set 0 1 0 1 0 1 1 Page address Sets the display RAM page address (4) Column address set upper bit Column address set lower bit 0 1 0 0 1 0 0 0 0 1 Most significant column address 0 0 0 0 Least significant column address Sets the most significant 4 bits of the display RAM column address. Sets the least significant 4 bits of the display RAM column address. (5) Status read 0 0 1 Status 0 0 0 0 Reads the status data (6) Display data write 1 1 0 Write data Writes to the display RAM (7) Display data read 1 0 1 Read data Reads from the display RAM (8) ADC select 0 1 0 1 0 1 0 0 0 0 0 Sets the display RAM address SEG output correspondence 0: normal, 1: reverse (9) Display normal/ reverse 0 1 0 1 0 1 0 0 1 1 0 Sets the LCD display normal/ reverse 0: normal, 1: reverse (10) Display all points ON/OFF 0 1 0 1 0 1 0 0 1 0 0 Display all points 0: normal display 1: all points ON (11) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 Sets the LCD drive voltage bias ratio 0: 1/6 bias, 1: 1/5 bias (ST7533) (12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 Column address increment At write: +1 At read: 0 (13) End 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write (14) Reset 0 1 0 1 1 1 0 0 0 1 0 Internal reset (15) Common output mode select 0 1 0 1 1 0 0 0 * * * Select COM output scan direction 0: normal direction 1: reverse direction (16) Power control set 0 1 0 0 0 1 0 1 Operating mode Select internal power supply operating mode (17) V5 voltage regulator internal resistor ratio set 0 1 0 0 0 1 0 0 Resistor ratio Select internal resistor ratio(Rb/Ra) mode (18) Electronic volume mode set Electronic volume register set 0 1 0 1 0 0 0 0 0 0 1 0 0 Electronic volume value Set the V5 output voltage electronic volume register (19) Static indicator ON/OFF Static indicator register set 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 Mode 0: OFF, 1: ON Set the flashing mode (20) Power saver Display OFF and display all points ON compound command (21) NOP 0 1 0 1 1 1 0 0 0 1 1 Command for non-operation (22) Test 0 1 0 1 1 1 1 * * * * Command for IC test. Do not use this command

Ver 1.0 41/60 2003/07/21 CCOOMMMMAANNDD DDEESSCCRRIIPPTTIIOONN Instruction Setup: Reference (1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V 1 ~ V5) and the V DD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1. When the built-in power is being used immediately after turning on the power: Turn ON the power and keeping the /RES pin = “L” This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and t he capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V5 voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting When the power is stabilized Release the reset state. (/RES pin = “H”) Waiting reset circuit stabilized (<1ms) Function setup by command input (User setup) (16) Power control setting *7 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Initialized state (Default) *1 Arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms.

Ver 1.0 42/60 2003/07/21 2. When the built-in power is not being used immediately after turning on the power: * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: Description of functions; Resetting circuit *2: Command description; LCD bias setting *3: Command description; ADC selection *4: Command description; Common output state selection *5: Description of functions; Power circuit & Command description; Setting the built-in resistance radio for regulation of the V voltage *6: Description of functions; Power circuit & Command description; Electronic volume control *7: Description of functions; Power circuit & Command description; Power control setting *8: The power saver ON state can either be in sleep state or stand-by state. Command description; Power saver START (multiple commands) Turn ON the VDD-VSS power keeping the /RES pin = “L”. When the power is stabilized Release the reset state. (/RES pin = “H”) Waiting reset circuit stabilized (<1ms) Power saver OFF *8 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Power saver START (multiple commands) *8 Initialized state (Default) *1 Arrange to start the power saver within 5ms after releasing the reset state. (In case o f other models) execute the procedures from turning on the power to setting the power control in 5ms. Function setup by command input (User setup) (16) Power control setting *7 This concludes the initialization Arrange to start powe r control setting within 5ms after turning OFF the power saver.

Ver 1.0 43/60 2003/07/21 (2) Data Display Notes: Reference items *9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying all the data at the data display start (when the display is ON) in white. (3) Power OFF *14 Notes: Reference items *14: The logic circuit of this IC’s power supply V DD - VSS controls the driver of the LCD power supply VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures:

• After turning off the internal power supply, make sure that the potential V 5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS). 6. Description of Function, 6.7 Power Circuit *15: After inputting the power save command, be sure to reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save *16: After inputting the power save command, do not reset the function using the /RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save Function setup by command input (User setup) (2) Display start line set *9 (3) Page address set *10 (4) Column address set *11 Function setup by command input (User setup) (6) Display data write *12 End of data display Function setup by command input (User setup) (1) Display ON/OFF *13 End of initialization Function setup by command input (User setup) (20) Power save *15 VDD – VSS power OFF Reset active (RES pin = “L”) Optional status Set the time ( tL) from reset active to turning off the V DD - VSS power (VDD - V SS = 1.8V) longer than the time ( tH) when the potential of V 5 ~ V 1 becomes below the threshold voltage (approximately 1V) of the LCD panel. For tH, refer to the <Reference Data> of this event. When tH is too long, insert a resistor between V 5 and VDD to reduce it.

Ver 1.0 44/60 2003/07/21 Refresh It is recommended to turn on the refresh sequence regularly at a specified interval. Precautions on Turning off the power <Turning the power (V DD - VSS) off> 1) Power Save (The LCD powers (VDD - V5) are off.) → Reset input → Power (VDD - VSS) OFF

• Observe tL > tH.
• When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C2 (smoothing capacity of V5 ~ V1) and the driver’s discharging capacity. Reset Power save Power Off tL 1.8V VDD VDD tH COM SEG VDD RES About 1V:below Vth of the LCD Panel Since the power (VDD-VSS) is cut off,the output comes not to be fixed. Reset command or NOP command Refreshing of DRAM Set all commands to the ready state Refresh sequence

Ver 1.0 45/60 2003/07/21 <Turning the power (VDD - VSS) off : When command control is not possible.> 2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF

• Observe tL > tH.
• When tL < tH, an irregular display may occur. For tL, make the power (VDD - VSS) falling characteristics longer or consider any other method. tH is determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging capacity. Reset Power Off tL 1.8V VDD VDD tH COM SEG VDD RES About 1V:below Vth of the LCD Panel Since the power (VDD-VSS) is cut off,the output comes not be fixed. <Reference Data> V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset. V5 voltage falling (discharge) time (tH) after the process of operation → reset. 5.0 4.0 3.0 2.4 1.8 1.00.50 100 VDD-VSS(V) C2 : V1 to V5 capacity (uF) V5 voltage falling time (mSec) Figure 31

Ver 1.0 46/60 2003/07/21 AABBSSOOLLUUTTEE MMAAXXIIMMUUMM RRAATTIINNGGSS Unless otherwise noted, VSS = 0V Table 17 Parameter Symbol Conditions Unit Power Supply Voltage VDD –0.3 ~ +5.0 V Power supply voltage (VDD standard) V SS2 –4.0 ~ -1.8 V Power supply voltage (VDD standard) V 5, VOUT –16.0 ~ +0.3 V Power supply voltage (VDD standard) V 1, V2, V3, V4 V 5 to +0.3 V Input voltage V IN –0.3 to V DD + 0.3 V Output voltage V O –0.3 to V DD + 0.3 V Operating temperature T OPR –40 to +85 °C Storage temperature Bare chip T STR –55 to +125 °C VDD VSS2,V1 to V4 V5.,VOUT VDD VSS VCC GND System (MPU) side ST7533 chip side Figure 30 Notes and Cautions 1. The V SS2, V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VDD ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ V5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well.

Ver 1.0 47/60 2003/07/21 DDCC CCHHAARRAACCTTEERRIISSTTIICCSS Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = –40 to 85°C Table 18 Rating Item Symbol Condition Min. Typ. Max. Units Applicable Pin Operating Voltage (1) Vss -3.3 — -1.8 V Vss*1 Operating Voltage (2) V SS2 (Relative to V DD) –3.3 — –1.8 V V SS2 0.4 x V5 — V DD V 1, V2 Operating Voltage (3) V SS2 (Relative to V DD) V5 — 0.6 x V 5 V V3, V4 High-level Input Voltage V IHC 0.8 x V DD — V DD V *3 Low-level Input Voltage V ILC V SS — 0.2 x V DD V *3 High-level Output Voltage V OHC I OH = –0.5 Ma 0.8 x V DD — V DD V *4 Low-level Output Voltage V OLC I OL = 0.5 mA V SS — 0.2 x V DD V *4 Input leakage current I LI V IN = VDD or VSS –1.0 — 1.0 μA *5 Output leakage current I LO V IN = VDD or VSS –3.0 — 3.0 μA *6 Liquid Crystal Driver ON Resistance RON Ta = 25°C (Relative To V DD) KΩ SEGn COMn *7 Static Consumption Current I SSQ — 0.01 2 μA VSS, VSS2 Output Leakage Current I 5Q V5 = –13.0 V(Relative To VDD) — 0.01 10 μA V5 Input Terminal Capacitance C IN Ta = 25°C , f = 1 MHz — 5.0 8.0 pF Internal Oscillator fOSC 17 24 27 kHz *8 Oscillator Frequency External Input fCL 1/33 duty , Ta = 25°C 17 24 27 kHz CL

Ver 1.0 48/60 2003/07/21 Table 19 Rating Item Symbol Condition Min. Typ. Max. Units Applicable Pin Input voltage V SS2 (Relative To V DD) –3.3 — –1.8 V V SS2 Supply Step-up output voltage Circuit VOUT (Relative To V DD) –13.0 — — V V OUT Voltage regulator Circuit Operating Voltage VOUT (Relative To V DD) –13.0 — –6.0 V V OUT Voltage Follower Circuit Operating Voltage V5 (Relative To V DD) –13.0 — –4.0 V V 5 * 9 Internal Power Base Voltage V RS Ta = 25°C , (Relative To VDD)

• Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used . Table 20 Rating Test pattern Symbol Condition Min. Typ. Max. Units Notes Display Pattern OFF IDD VDD = 3.0 V, V5 – VDD = –11.0 V — 4 12 μA *11 Display Pattern Checker IDD VDD = 3.0 V, V5 – VDD = –11.0 V — 7 21 μA *11
• Dynamic Consumption Current : During Display, with the Internal Power Supply ON Table 21 Rating Test pattern Symbol Condition Min. Typ. Max. Units Notes Normal Mode — 70 110 Display Pattern OFF IDD VDD = 3.0 V, Quad step-up voltage. V5 – VDD = –11.0 V High-Power Mode — 90 150 μA *12 Normal Mode — 95 130 Display Pattern Checker IDD VDD = 3.0 V, Quad step-up voltage. V5 – VDD = –11.0 V High-Power Mode — 130 180 μA *12
• Consumption Current at Time of Power Saver Mode : VSS = -3.0 V ± 10% Table 22 Rating Item Symbol Condition Min. Typ. Max. Units Notes Sleep mode IDD Ta = 25°C — 0.1 4 Standby Mode IDD Ta = 25°C — 5 10 μA

Ver 1.0 49/60 2003/07/21

• The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate Frequency fFR Table 23 Item f CL fFR Used internal oscillator circuit fOSC / 8 fOSC / (8*33) 1/33 DUTY Used external display clock External input (fCL) fCL / 264 Used internal oscillator circuit fOSC / 16 fOSC / (16*17) 1/17 DUTY Used external display clock External input (fCL) fCL / 272 (fFR is the liquid crystal alternating current period, and not the FR signal period.) References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the VDD system and the V5 system is. This applies when the external power supply is being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, M/S and C86, P/S, /DOF, /RES, IRS, and /HPM terminals. *4 The D0 to D7, FR, FRS, /DOF, and CL terminals. *5 The A0, /RD (E), /WR (R/W), /CS1, CS2, CLS, M/S, C86, P/S, /RES, IRS, and /HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and /DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V 1, V 2, V 3, and V 4). These are specified for the operating voltage (3) range. RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.) *8 See Table 23 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V 5 voltage regulator circuit. In the ST7533 , the temperature range approximately –0.15%/°C. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. The ST7533 is 1/5 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. *12 It is the value on a ST7533 having the V REG temperature gradient is –0.15%/°C when the V 5 voltage regulator internal resistor is used.

Ver 1.0 50/60 2003/07/21 TTIIMMIINNGG CCHHAARRAACCTTEERRIISSTTIICCSS System Bus Read/Write Characteristics 1 (For the 8080 Series MPU) tAH8tAW8 tCYC8 tCCLR,tCCLW tCCHR,tCCHW tDS8 tACC8 tOH8 tDH8 CS1 (CS2="1") WR,RD D0 to D7 (Write) D0 to D7 (Read) Figure 37 Table 24 (VDD = 3.3V , Ta =25°C) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH8 0 — Address setup time tAW8 0 — System cycle time tCYC8 240 — Enable L pulse width (WRITE) tCCLW 80 — Enable H pulse width (WRITE) WR tCCHW 80 — Enable L pulse width (READ) tCCLR 140 — Enable H pulse width (READ) RD tCCHR 80 WRITE Data setup time tDS8 40 — WRITE Data hold time tDH8 10 — READ access time tACC8 CL = 100 pF — 70 READ Output disable time D0 to D7 tOH8 CL = 100 pF 5 50 ns

Ver 1.0 51/60 2003/07/21 Table 25 (V DD = 2.7 V , Ta = 25°C ) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH8 0 — Address setup time tAW8 0 — System cycle time tCYC8 400 — Enable L pulse width (WRITE) tCCLW 220 — Enable H pulse width (WRITE) WR tCCHW 180 — Enable L pulse width (READ) tCCLR 220 — Enable H pulse width (READ) RD tCCHR 180 — WRITE Data setup time tDS8 40 — WRITE Data hold time tDH8 15 — READ access time tACC8 CL = 100 pF — 140 READ Output disable time D0 to D7 tOH8 CL = 100 pF 10 100 ns Table 26 (V DD = 1.8V , Ta = 25°C ) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH8 0 — Address setup time tAW8 0 — System cycle time tCYC8 640 — Enable L pulse width (WRITE) tCCLW 360 — Enable H pulse width (WRITE) WR tCCHW 280 — Enable L pulse width (READ) tCCLR 360 — Enable H pulse width (READ) RD tCCHR 280 WRITE Data setup time tDS8 80 — WRITE Data hold time tDH8 30 — READ access time tACC8 CL = 100 pF — 240 READ Output disable time D0 to D7 tOH8 CL = 100 pF 10 200 ns *1 The input signal rise time and fall time ( tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and WR and RD being at the “L” level.

Ver 1.0 52/60 2003/07/21 tAH6tAW6 tCYC6 tCCLR,tCCLW tCCHR,tCCHW tDS6 tACC6 tOH6 tDH6 CS1 (CS2="1") E R/W D0 to D7 (Write) D0 to D7 (Read) System Bus Read/Write Characteristics 2 (For the 6800 Series MPU) Figure 38 Table 27 (V DD = 3.3 V , Ta = 25°C ) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH6 0 — Address setup time tAW6 0 — System cycle time tCYC6 240 — Enable L pulse width (WRITE) tEWLW 80 — Enable H pulse width (WRITE) WR tEWHW 80 — Enable L pulse width (READ) tEWLR 80 — Enable H pulse width (READ) RD tEWHR 140 WRITE Data setup time tDS6 40 — WRITE Data hold time tDH6 10 — READ access time tACC6 CL = 100 pF — 70 READ Output disable time D0 to D7 tOH6 CL = 100 pF 5 50 ns

Ver 1.0 53/60 2003/07/21 Table 28 (V DD = 2.7V , Ta =25°C ) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH6 0 — Address setup time tAW6 0 — System cycle time tCYC6 400 — Enable L pulse width (WRITE) tEWLW 220 — Enable H pulse width (WRITE) WR tEWHW 180 — Enable L pulse width (READ) tEWLR 220 — Enable H pulse width (READ) RD tEWHR 180 — WRITE Data setup time tDS6 40 — WRITE Data hold time tDH6 15 — READ access time tACC6 CL = 100 pF — 140 READ Output disable time D0 to D7 tOH6 CL = 100 pF 10 100 ns Table 29 (V DD =1.8V , Ta =25°C ) Rating Item Signal Symbol Condition Min. Max. Units Address hold time tAH6 0 — Address setup time tAW6 0 — System cycle time tCYC6 640 — Enable L pulse width (WRITE) tEWLW 360 — Enable H pulse width (WRITE) WR tEWHW 280 — Enable L pulse width (READ) tEWLR 360 — Enable H pulse width (READ) RD tEWHR 280 — WRITE Data setup time tDS6 80 — WRITE Data hold time tDH6 30 — READ access time tACC6 CL = 100 pF — 240 READ Output disable time D0 to D7 tOH6 CL = 100 pF 10 200 ns *1 The input signal rise time and fall time ( tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.

Ver 1.0 54/60 2003/07/21 The Serial Interface tCSH CS1 (CS2="1") SI SCL tCCSS tSAS tSAH tSCYC tSLW tSHW tSDHtSDS tf tr Figure 39 Table 30 (V DD = 3.3V, Ta =25°C ) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period tSCYC 50 — SCL “H” pulse width tSHW 25 — SCL “L” pulse width SCL tSLW 25 — Address setup time tSAS 20 — Address hold time tSAH 10 — Data setup time tSDS 20 — Data hold time SI tSDH 10 — CS-SCL time tCSS 20 — CS-SCL time CS tCSH 40 — ns Table 31 (V DD =2.7V , Ta =25°C ) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period tSCYC 100 — SCL “H” pulse width tSHW 50 — SCL “L” pulse width SCL tSLW 50 — Address setup time tSAS 30 — Address hold time tSAH 20 — Data setup time tSDS 30 — Data hold time SI tSDH 20 — CS-SCL time tCSS 30 — CS-SCL time CS tCSH 60 — ns

Ver 1.0 55/60 2003/07/21 Table 32 (V DD = 1.8V , Ta = 25°C ) Rating Item Signal Symbol Condition Min. Max. Units Serial Clock Period TSCYC 200 — SCL “H” pulse width TSHW 80 — SCL “L” pulse width SCL TSLW 80 — Address setup time TSAS 60 — Address hold time TSAH 30 — Data setup time TSDS 60 — Data hold time SI TSDH 30 — CS-SCL time TCSS 40 — CS-SCL time CS tCSH 100 — ns *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.

Ver 1.0 56/60 2003/07/21 Reset Timing Internal status tRW tR During reset Reset complete RES Figure 41 Table 36 (V DD = 3.3V , Ta = –40 to 85°C ) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tR — — 1.0 us Reset “L” pulse width RES tRW 1.0 — — us Table 37 (V DD = 2.7V , Ta = –40 to 85°C ) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tR — — 2.0 us Reset “L” pulse width RES tRW 2.0 — us Table 38 (V DD = 1.8V , Ta = –40 to 85°C ) Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time tR — — 3.0 us Reset “L” pulse width RES tRW 3.0 — — us *1 All timing is specified with 20% and 80% of VDD as the standard.

Ver 1.0 58/60 2003/07/21 CCOONNNNEECCTTIIOONNSS BBEETTWWEEEENN LLCCDD DDRRIIVVEERRSS ((RREEFFEERREENNCCEE EEXXAAMMPPLLEE)) The liquid crystal display area can be enlarged with ease through the use of multiple ST7533 Series chips. Use a same equipment type. (1) ST7533 (master) ↔ ST7533 (slave) Figure 43-1 ST7533 Slave ST7533 Master M/S FR CL DOF FR CL DOF Output Input VDD VSS CLS CLS M/S ST7533 Slave ST7533 Master M/S FR CL DOF FR CL DOF Output Input VDD VSS CLS CLS M/S

Ver 1.0 59/60 2003/07/21 (2) Single-chip Structure Figure 43-2 (3) Double-chip Structure Figure 43-3 192 x 33 Dots ST7533 Master ST7533 Slave COM SEG SEG COM ST7533 Master

96 X 33 Dots

Ver 1.0 60/60 2003/07/21 Revisions Version 0.1 - Preliminary. Version 0.2 - update Pad Center Coordinates page 2,3,4. Version 0.2a - update PIN DESCRIPTIONS M/S. Version 0.2b - update ABSOLUTE MAXIMUM RATINGS & DC CHARACTERISTICS. Version 0.2c - update Master and Slave reference example. Version 0.3 - update Pad Center Coordinates (1/33 , 1/17 Duty) page 3,4,5,6 and page-18. Version 0.3a - update Pad diagram page2 and v5 regulator voltage diagram page24 Version 0.3b - Logic power supply V DD – VSS = 1.8V to 3.3V (+10% Range) , VOUT= -13V (+10% Range) Version 0.3c - Modify page-27 The temperature grade of the Internal Power Supply for ST7533 (-0.05%/°C) Figure 14 Version 0.3d - Delete page-40 Figure 29 Version 0.4 - Modify V RS temperature gradient (-0.15%/°C) and Reset “L” pulse width Version 0.5 - Delete shipping forms include bare chip and TCP Version 0.6 - Modify page-10 The TEST0(PAD No.65) must connect VDD Version 1.0 - Modify Tdh (data hold time) and page41,42 initial flow , datasheet version change version 1.0