ST7522

ST7522 SITRONIX | Alldatasheet

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17 x 96 Dot Matrix LCD Controller/Driver Ver 1.0c 1/45 2002/07/10 OOVVEERRVVIIEEWW The ST7522 family of dot matrix LCD drivers are designed for the display of characters and graphics. The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM. The drivers are available in two configurations The ST7522 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages. These features give the designer a flexible means of implementing small to medium size LCD displays for compact, low power systems. The ST7522 which is able to drive 1 line of 6 Chinese characters or 2 lines of 12 Chinese characters each line with two ST7522. FFEEAATTUURREESS z Fast 8-bit MPU interface compatible with 80- and 68- family microcomputers and serial interface z Clock synchronous serial interface z Many command set Display data Read/Write, display ON/OFF, Normal/Reverse display mode, page address set , column address set , status read , display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, adjustable OSC frequency, booster input voltage select, follower input voltage and amplified ratio selectable z 4 static indicator and 96 icon available z Total 118 (segment + common + static) drive sets z Wide range of supply voltages V DD – VSS：2.7 to 5.5 V VDD – V5：3.5 to 7.0 V VDD – VCAP3 ：3.5 to 7.0 V z Low-power CMOS z 64 level digital contrast control Clock frequency Product name On-Chip External Number of COM Number of SEG Bias Duty ST7522D 1.2KHz,2.4KHz (When VDD=3.0V) 2.8KHz 17 96 1/5,1/6 1/17,1/33

Ver 1.0c 2/45 2002/07/10 ST7522 Serial Specification Revision History Version Date Description 1.0 2002/01/30 New specification version 1.0a 2002/02/20 Modify c over page’s product name 1.0b 2002/03/18 Adding FR frequenc y for “OSC frequency set” command 1.0c 2002/07/10 1. Adding “Slave chip notice” in application circuit 2. Adding “Software example” 3. Adding “Follower-contrast curve” 4. Adding “Master mode application circuit” 5. Adding “I/O pad configuration”

Ver 1.0c 3/45 2002/07/10 BBLLOOCCKK DDIIAAGGRRAAMM LCD driver circuit Common counter Display data latch circuit Display data RAM (96 X33 bits) Line address decoder I/O buffer Column address decoder Line counter Display start line register Column address counter Column address register Display timing generator circuit Low-address register Bus holder Command decoder Status MPU interface FR VDD VSS COM0~COM15 COMI SEG0~SEG95 V1,V2,V3,V4,V5 COMS S1~S4 Power circuit CAP1 CAP2 CAP3 /RES D0~D7 M/S /WR,/RD /CS1,CS2 P/S C86 CLS CL

Ver 1.0c 4/45 2002/07/10 PPAADD AARRRRAANNGGEEMMEENNTT Chip specifications of AL pad package Chip size : 3720 µm x 5040 µm Minimum pad pitch : 110µm Pad size : 90µm X 90µm ** SSuubbssttrraattee ccoonnnneecctt ttoo VVDDDD.. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148SEG12/ SEG11/ SEG10/ SEG9/ SEG8/ SEG7/ SEG6/ SEG5/ SEG4/ SEG3/ SEG2/ SEG1/ SEG0/ COMI/ COM15/ COM14/ COM13/ COM12/ COM11/ COM10/ COM9/ COM8/ COM7/ COM6/ COM5/ COM4/ COM3/ COM2/ COM1/ COM0/ SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COMS P/S CL VSS /CS1 CS2 E(RD) R/W VDD C86 RES CLS FR M/S CAP1 CAP2 CAP3 SEG95/ SEG94/ SEG93/ SEG92/ SEG91/ SEG90/ SEG89/ SEG88/ SEG87/ SEG86/ SEG85/ SEG84/ SEG83/ SEG82/ SEG81/ SEG80/ SEG79/ SEG78/ SEG77/ SEG76/ SEG75/ SEG74/ SEG73/ SEG72/ SEG71/ SEG70/ SEG69/ SEG68/ SEG67/ SEG66/ SEG65/ SEG64/ SEG63/ SEG62/ SEG61/ SEG60/ SEG59/ SEG58/ SEG57/ COM9 COM10 COM11 COM12 COM13 COM14 COM15 COMI SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 /SEG56 /SEG55 /SEG54 /SEG53 /SEG52 /SEG51 /SEG50 /SEG49 /SEG48 /SEG47 /SEG46 /SEG45 /SEG44 /SEG43 /SEG42 /SEG41 /SEG40 /SEG39 /SEG38 /SEG37 /SEG36 /SEG35 /SEG34 /SEG33 /SEG32 /SEG31 /SEG30 /SEG29 /SEG28 /SEG27 /SEG26 /SEG25 /SEG24 /SEG23 /SEG22 /SEG21 /SEG20 /SEG19 /SEG18 /SEG17 /SEG16 /SEG15 /SEG14 /SEG13

Ver 1.0c 5/45 2002/07/10 PPAADD CCEENNTTEERR CCOOOORRDDIINNAATTEESS (chip size : 3720 µm x 5040 µm) Pin Name Pin Name Pin Name Pad No. Master Slave X Y Pad No. Master Slave X Y Pad No. Master Slave X Y

1 SEG56 SEG73 -1745 2405 50 SEG7 SEG24 -1045 -2405 99 CLS 1745 275

2 SEG55 SEG72 -1745 2275 51 SEG6 SEG23 -935 -2405 100 FR 1745 385

3 SEG54 SEG71 -1745 2155 52 SEG5 SEG22 -825 -2405 101 V1 1745 495

4 SEG53 SEG70 -1745 2035 53 SEG4 SEG21 -715 -2405 102 V4 1745 605

5 SEG52 SEG69 -1745 1925 54 SEG3 SEG20 -605 -2405 103 V3 1745 715

6 SEG51 SEG68 -1745 1815 55 SEG2 SEG19 -495 -2405 104 M/S 1745 825

7 SEG50 SEG67 -1745 1705 56 SEG1 SEG18 -385 -2405 105 V5 1745 935

8 SEG49 SEG66 -1745 1595 57 SEG0 SEG17 -275 -2405 106 V2 1745 1045

9 SEG48 SEG65 -1745 1485 58 COMI SEG16 -165 -2405 107 CAP1 1745 1155

10 SEG47 SEG64 -1745 1375 59 COM15 SEG15 -55 -2405 108 CAP2 1745 1265

11 SEG46 SEG63 -1745 1265 60 COM14 SEG14 55 -2405 109 CAP3 1745 1375

12 SEG45 SEG62 -1745 1155 61 COM13 SEG13 165 -2405 110 SEG95 COM0 1745 1485

13 SEG44 SEG61 -1745 1045 62 COM12 SEG12 275 -2405 111 SEG94 COM1 1745 1595

14 SEG43 SEG60 -1745 935 63 COM11 SEG11 385 -2405 112 SEG93 COM2 1745 1705

15 SEG42 SEG59 -1745 825 64 COM10 SEG10 495 -2405 113 SEG92 COM3 1745 1815

16 SEG41 SEG58 -1745 715 65 COM9 SEG9 605 -2405 114 SEG91 COM4 1745 1925

17 SEG40 SEG57 -1745 605 66 COM8 SEG8 715 -2405 115 SEG90 COM5 1745 2035

18 SEG39 SEG56 -1745 495 67 COM7 SEG7 825 -2405 116 SEG89 COM6 1745 2155

19 SEG38 SEG55 -1745 385 68 COM6 SEG6 935 -2405 117 SEG88 COM7 1745 2275

20 SEG37 SEG54 -1745 275 69 COM5 SEG5 1045 -2405 118 SEG87 COM8 1745 2405

21 SEG36 SEG53 -1745 165 70 COM4 SEG4 1155 -2405 119 SEG86 COM9 1615 2405

22 SEG35 SEG52 -1745 55 71 COM3 SEG3 1265 -2405 120 SEG85 COM10 1495 2405

23 SEG34 SEG51 -1745 -55 72 COM2 SEG2 1375 -2405 121 SEG84 COM11 1375 2405

24 SEG33 SEG50 -1745 -165 73 COM1 SEG1 1495 -2405 122 SEG83 COM12 1265 2405

25 SEG32 SEG49 -1745 -275 74 COM0 SEG0 1615 -2405 123 SEG82 COM13 1155 2405

26 SEG31 SEG48 -1745 -385 75 COMS 1745 -2405 124 SEG81 COM14 1045 2405

27 SEG30 SEG47 -1745 -495 76 S1 1745 -2275 125 SEG80 COM15 935 2405

28 SEG29 SEG46 -1745 -605 77 S2 1745 -2155 126 SEG79 COMI 825 2405

29 SEG28 SEG45 -1745 -715 78 S3 1745 -2035 127 SEG78 SEG95 715 2405

30 SEG27 SEG44 -1745 -825 79 S4 1745 -1925 128 SEG77 SEG94 605 2405

31 SEG26 SEG43 -1745 -935 80 P/S 1745 -1815 129 SEG76 SEG93 495 2405

32 SEG25 SEG42 -1745 -1045 81 CL 1745 -1705 130 SEG75 SEG92 385 2405

33 SEG24 SEG41 -1745 -1155 82 VSS 1745 -1595 131 SEG74 SEG91 275 2405

34 SEG23 SEG40 -1745 -1265 83 D0 1745 -1485 132 SEG73 SEG90 165 2405

35 SEG22 SEG39 -1745 -1375 84 D1 1745 -1375 133 SEG72 SEG89 55 2405

36 SEG21 SEG38 -1745 -1485 85 D2 1745 -1265 134 SEG71 SEG88 -55 2405

37 SEG20 SEG37 -1745 -1595 86 D3 1745 -1155 135 SEG70 SEG87 -165 2405

38 SEG19 SEG36 -1745 -1705 87 D4 1745 -1045 136 SEG69 SEG86 -275 2405

39 SEG18 SEG35 -1745 -1815 88 D5 1745 -935 137 SEG68 SEG85 -385 2405

40 SEG17 SEG34 -1745 -1925 89 D6 1745 -825 138 SEG67 SEG84 -495 2405

41 SEG16 SEG33 -1745 -2035 90 D7 1745 -715 139 SEG66 SEG83 -605 2405

42 SEG15 SEG32 -1745 -2155 91 /CS1 1745 -605 140 SEG65 SEG82 -715 2405

43 SEG14 SEG31 -1745 -2275 92 CS2 1745 -495 141 SEG64 SEG81 -825 2405

44 SEG13 SEG30 -1745 -2405 93 E(RD) 1745 -385 142 SEG63 SEG80 -935 2405

45 SEG12 SEG29 -1615 -2405 94 A0 1745 -275 143 SEG62 SEG79 -1045 2405

46 SEG11 SEG28 -1495 -2405 95 R/W 1745 -165 144 SEG61 SEG78 -1155 2405

47 SEG10 SEG27 -1375 -2405 96 VDD 1745 -55 145 SEG60 SEG77 -1265 2405

48 SEG9 SEG26 -1265 -2405 97 C86 1745 55 146 SEG59 SEG76 -1375 2405

49 SEG8 SEG25 -1155 -2405 98 RES 1745 165 147 SEG58 SEG75 -1495 2405

148 SEG57 SEG74 -1615 2405

Ver 1.0c 6/45 2002/07/10 PPIINN DDEESSCCRRIIPPTTIIOONN (1) Power Pins Name I/O Description VDD - Connected to the +5V 0r +3V dc power. Common to the Vcc MPU power pin. VSS - 0V dc pin connected to the system ground. CAP1~3 - Capacitor connector pin for voltage booster V1~V5 - Multi-level power supplies for LCD driving. The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied. These voltages must satisfy the following: VDD≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧V5 (2) System Bus Connection Pins Name I/O Description D7 to D0 SI (D7) SCL (D6) I/O The 8-bit bidirectional data buses to be connected to the 8- or 16- bit standard MCU Data busses. When the serial interface is selected then D7 act as serial data input terminal and D6 act as serial clock input terminal. D5 ~ D0 become high impedance. A0 I Usually connected to the low-order bit of the MPU address bus and used to identify the data or a command. A0=0 : DO to D7 are display control data. A0=1 : DO to D7 are display data. CLS I CLS=1 : internal oscillator enable CLS=0 : external clock operation mode RES I Input low active. System reset. C86 I High level: 68-series MPU interface Low level : 80-series MPU interface P/S I This pin select the parallel / serial data input method. P/S = 1 : parallel, P/S = 0 : serial. CS1 , CS2 I Input. When CS1 = 0 and CS2 = 1 the chip select become active E(RD — ) I z If the 68-series MPU is connected: Input. Active high. Used as an enable clock input of the 68-series MPU. z If the 80-series MPU is connected: Input. Active low. The RD signal of the 80-series MPU is entered in this pin. When this signal is kept low, the ST7522 data bus is in the output status. R/W (WR — ) I z If the 68-series MPU is connected: Input. Used as an input pin of read control signals (if R/W is high) or write control signals (if low). z If the 80-series MPU is connected: Input. Active low. The WR signal of the 80-series MPU is entered in this pin. A signal on the data bus is fetched at the rising edge of WR signal.

Ver 1.0c 7/45 2002/07/10 (3) LCD Driver Circuit Signals Name I/O Description CL I/O Input/output. I/O selection z M/S = “H” & CLS = “H” ：Output z M/S = “L” & CLS = “H” ：Input z M/S = “X” & CLS = “L” ：Input This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. SEGn O Output. A single level of VDD, V2, V3 and V5 is selected by the combination of display RAM contents and FR signal. COMn O Output. The output pin for LCD common (row) driving. A single level of VDD, V1, V4 and V5 is selected by the combination of common counter output and FR signal. The slave LSI has the reverse common output scan sequence than the master LSI. COMI O Output. ICON common signals(only use with SEGn) FR I/O Input/output. This is the liquid crystal alternating current signal I/O terminal l/O selection z M/S = “H”：Output z M/S = “L”：Input COMS O Output. Static scan line(only use with S1~S4) S1~S4 O Output. Static data (only use with COMS) M/S I Input. The master or slave LSI operation select pin for the ST7522 . Connected to VDD (to select the master LSI operation mode) or Vss (to select the slave LSI operation mode). The slave driver has the reverse common/ segment output scan sequence than the master driver for the convenience of PCB and LCD layout. M/S Operating Mode FR CL V1~V5 Power Supply Internal oscillator High Master Output See CLS On On See CLS Low Slave Input Input Off Off Off M/S COM0~COM15 SEG0~SEG95 COMI COMS S1~S4 High Pad 74~59 Pad 57~110 Pad 58 Low Pad 110~125 Pad 74~127 Pad 126 Pad 75 Pad 76~79

Ver 1.0c 8/45 2002/07/10 DDEESSCCRRIIPPTTIIOONN OOFF FFUUNNCCTTIIOONNSS The MPU Interface Selecting the Interface Type With the ST7522 Series chips, data transfers are done through an 8-bit bi-directional data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/S terminal polarity to the “H” or “L” it is possible to select either parallel data input or serial data input as shown in Table 1. Table 1 P/S CS1 CS2 A0 RD WR C86 D7 D6 D5~D0 H: Parallel Input CS1 CS2 A0 RD ― WR ― C86 D7 D6 D5~D0 L: Serial Input CS1 CS2 A0 High level High level High level SI SCL High level The Parallel Interface When the parallel interface has been selected (P/S =“H”), then it is possible to connect directly to either an 8080-system MPU or a 6800 Series MPU (as shown in Table 2) by selecting the C86 terminal to either “H” or to “L”. Table 2 C86 CS1 ― CS2 A0 RD ― WR ― D7~D0 H: 6800 Series MPU Bus CS1 ― CS2 A0 E R/W D7~D0 L: 8080 MPU Bus CS1 CS2 A0 RD ― WR ― D7~D0 Moreover, data bus signals are recognized by a combination of A0, RD (E), WR (R/W) signals, as show in Table 3. Table 3 Shared 6800 Series 8080 Series A0 R/W RD WR Function 1 1 0 1 Reads the display data 1 0 1 0 Writes the display data 0 1 0 1 Status read 0 0 1 0 Write control data (command)

Ver 1.0c 10/45 2002/07/10 The Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the ST7522 Series. Wait time may not be considered. And, in the ST7522 Series chips, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. Internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2. N N+1 N+2 N+3 N+3N+2N+1N Data Bus Holder Write Signal WR MPUInternal Timing Writing Data WR MPU Reading N N n n+1 RD Preset N Increment N+1 N+2 n n+1N n+2 Address Preset Read Signal Column Address Bus Holder Internal Timing Address Set #n Dummy Read Data Read Data Read #n+1 Figure 2

Ver 1.0c 11/45 2002/07/10 Display Data RAM The display data RAM is a RAM that stores the dot data for the display. It has a 33 (4 page x 8 bit +1) x 96 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are fe w constraints at the time of display data transfer when multiple ST7522 series chips are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). Display data RAM Liquid crystal display COM0 COM1 COM2 COM3 COM4 Figure 3 The Page Address Circuit As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page for the RAM region used only by the indicators, and only display data D0 is used. The Column Addresses As is shown in Table 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the increment of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. Table 4 SEG Output ADC set SEG0 SEG 95 ADC(D0)=0 0 → Column Address → 95 ADC(D0)=1 95 ← Column Address ← 0

Ver 1.0c 12/45 2002/07/10 Figure 4 Page Address D3 D2 D1 D0 Data SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 ………… SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG COM D0 c C O M 0 D1 C O M 1 D2 C O M 2 D3 C O M 3 D4 C O M 4 D5 C O M 5 D6 C O M 6 0 0 0 0 Page 0 C O M 7 D0 C O M 8 D1 C O M 9 D2 COM10 D3 COM11 D4 COM12 D5 COM13 D6 COM14 0 0 0 1 Page 1 COM15 D0 COM16 D1 COM17 D2 COM18 D3 COM19 D4 COM20 D5 COM21 D6 COM22 0 0 1 0 Page 2 COM23 D0 COM24 D1 COM25 D2 COM26 D3 COM27 D4 COM28 D5 COM29 D6 COM30 0 0 1 1 Page 3 COM31 1 0 0 0 D0 Page 8 COMI ADC=0 08 ………… COLUMN ADC=1 87 …………

Ver 1.0c 13/45 2002/07/10 Common Timing Generator Circuit Generates common timing signals and FR frame signals from the CL basic clock. The 1/17 or l/33 duty (for ST7522)can be selected by the Duty Select command. If the l/33 duty is selected for the ST7522 , the l/33 and l/ 17 duties are provided by two chips consisting of the master and slave chips in the common multi-chip mode. Display Data Latch Circuit This latch stores one line of display data for use by the LCD driver interface circuitry. The output of this latch is controlled by the Display ON/OFF. FR SIGNAL (Master output) Master Common Slaver Common 0 1 2 3 14 15 16 17 18 31 32

Ver 1.0c 14/45 2002/07/10 Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Two-frame alternating current drive waveform Figure 5 When multiple ST7522 Series chips are used, the slave chip must be supplied the display timing signals (FR, CL) from the master chip. Table 5 shows the status of the FR and CL signals. Table 5 Operating Mode FR CL Master (M/S = “H”) The internal oscillator circuit is enabled (CLS = “H”) The internal oscillator circuit is disabled (CLS = “L”) Output Output Output Input Slave (M/S = “L”) The internal oscillator circuit is enabled (CLS = “H”) The internal oscillator circuit is disabled (CLS = “L”) Input Input Input Input VDD VDD VDD COM0 COM1 RAM Data SEGn FR CL 3 2 3 3 123456 2 8 2 9 3 0 3 1 3 2 3 3 123456

Ver 1.0c 16/45 2002/07/10 The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 6 shows the Power Control Set Command 2-bit data control function,.(if Booster is off, than the external LCD power supply CAP3 must connect to Vss or external power). Table 6 Status Item “1” “0” D2 Booster circuit control bit D0 Voltage follower circuit control bit ON ON OFF OFF The Control Details of Each Bit of the Power Control Set Command The Liquid Crystal Voltage Generator Circuit The V5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit. 1/6 bias or 1/5 bias for ST7522, can be selected. VDD-V5 maximum voltage is 7V, VDD-Vcap3 maximum voltage is 7V too. If VDD < 3.5V , it can use the Booster circuit 2x, The booster voltage can follow the spec. condition (VDD-V5 ≦ 7V max. voltage.) if VDD >3.5V only use the 1X booster circuit, that can ensure the VDD-V5 voltage ≦ 7V. If use the VDD voltage 5V and 2X booster , it’s over the spec. operation condition, although adjust the contrast control can make the V5 voltage small than 7V , but the Vcap3 booster voltage already over spec 7V. IC can not guarantee normally work in this condition. To turn on built-in power(booster/follower) must waiting 200mS to display on for booster/follower stable. Therefore, power off must follow “power off sequence” too. Power on Power control Booster on Display off Display all point on Static indicator off Hardware reset Power off Power off sequence Set Duty/Bias Electronic contrast set Wait time >200mS Display on Power on sequence Power control Follower on

Ver 1.0c 17/45 2002/07/10 The Reset Circuit When the RES input comes to the “L” level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Static drive is turned OFF. 3. ADC select: Normal (ADC command D0 = 0) 4. Display all point on is select to normal 5. Display normal/reverse is select to normal 6. Power control register: (D2, D0) = (0, 0) 7. Serial interface inter nal register data clear 8. 1/6 bias is selected 9. 1/17 duty is selected. 10. Read modify write OFF 11. Column address set to Address 0 12. Page address set to Page 0 13. Start line set to first line 14. Electronic contrast register = 35H(max:3FH) 15. OSC frequency set = 08H 16. Follower input voltage set =02H 17. Follower amplified ratio = 06H 18. Booster input voltage set = 00H When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RES terminal. After the initialization, each input terminal should be controlled normally. While RES is “L,” the oscillator works but the display timing generator stops, and the CL, FR, terminals are fixed to “H.” The terminals D0 to D7 are not affected.

Ver 1.0c 18/45 2002/07/10 TTAABBLLEE OOFF SSTT77552222 IINNSSTTRRUUCCTTIIOONNSS Instruction code Instructions A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function Display on/off 0 1 0 1010111D D=1:Display on D=0:Display off Page address set 0 1 0 1 0 1 1 Page address Set display page Column address set upper bits 0 1 0 0 0 0 1 MSB 4 bits Set MSB 4 bits of column address Column address set lower bits 0 1 0 0 0 0 0 LSB 4 bits Set LSB 4 bits of column address Status read 0 0 1 0 Status 0 0 0 0 Read status Display data write 1 1 0 Write data Write display data Display data read 1 0 1 Read data Read display data Start line set 0 1 0 0 1 0 Display start address Determines the RAM display line for COM 0 ADC select 0 1 0 1010000A Display RAM and Segment output correspondence A=1:Reverse A=0:Normal Display normal/reverse 0 1 0 1010011R Set LCD display reverse R=1:Reverse R=0:Normal Display all point on/off 0 1 0 1010010L Set display all point on L=1:All on L=0:Normal Read/modify/write 0 1 0 11100000 Column address increment Wr:+1 Rd:+0 End 0 1 0 1 1 1 0 1 1 1 0 Clear read/modify/write Duty select 0 1 0 1010100U Select LCD duty U=1:1/33 duty U=0:1/17 duty LCD bias set 0 1 0 1010001 I Select LCD bias voltage I=1:1/5 bias I=0:1/6 bias Reset 0 1 0 11100010 I n t e r n a l r e s e t Power control 0 1 0 00101B0F B=1:Booster on B=0:Booster off F=1:Follower on F=0:Follower off

Ver 1.0c 19/45 2002/07/10 TTAABBLLEE OOFF SSTT77552222 IINNSSTTRRUUCCTTIIOONNSS((ccoonnttiinnuueedd)) Instruction codeInstructions A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Function 1 0 0 0 0 0 0 1 Electronic contrast set 0 1 0 0 0 Electronic volume Set contrast by 64 level (V5 fine adjust) 1 1 1 1 0 0 0 1 OSC Frequency set 0 1 0 0000 josc josc josc josc Internal OSC frequency adjust 1 1 1 1 1 0 0 0 Follower input voltage set 0 1 0 000000 jvref jvref V5 follower input voltage select(V5 coarse adjust) Follower amplified ratio 0 1 0 00100 rarb rarb rarb

0 V5 follower amplified ratio

Booster input voltage set 0 1 0 jbst jbst 0 000000 Booster input voltage select 1 0 1 0 1 1 0 S Static indicator on/off static indicator register set 0 1 0 0 0 0 0 S4 S3 S2 S1 S=1:Indicator on S=0:Indicator off Set the individual indicator on/off Sleep Display off + Display all point on + Static indicator off compound command Sleep mode Stand by Display off + Display all point on + Static indicator on compound command Stand by mode

Ver 1.0c 20/45 2002/07/10 CCoommmmaanndd DDeessccrriippttiioonn See the Table of ST7522 instructions. The ST7522 series identifies a data bus using a combination of A0 and R/W (RD or WR signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed is very high. The busy check is usually not required. ¾ Display ON/FF A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 1 D This command turns the display on and off. D=1: Display ON D=0: Display OFF(default) ¾ Set Page Address This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified. The display status is not changed even when the page address is changed. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 1 A3 A2 A1 A0 This command loads the page address register. A3 A2 A1 A0 Page 0 0 0 0 0(default) 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 1 0 0 0 8(Icon) Page mapping see Figure 4.

Ver 1.0c 21/45 2002/07/10 ¾ Set Column Address This command specifies a column address of the display dat a RAM. When the display data RAM is accessed by the MPU continuously, the column address is incremented by I each time it is accessed from the se t address. Therefore, the MPU can access to data continuously. The column address stops to be incremented at address 95, and the page address is not changed continuously. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 A3 A2 A1 A0 A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 1 A7 A6 A5 A4 This command loads the column address register. A7 A6 A5 A4 A3 A2 A1 A0 Column Address 0 0 0 0 0 0 0 0 0(default) 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 95 ¾ Read Status A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 ADC ON/OFF RESET 0 0 0 0 Reading the command I/O register (A0=0) yields system status information. The ADC bit indicates the way column addresses are assigned to segment drivers. ADC=1 : Normal. Column address n = segment driver n. ADC=0: Inverted. Column address 95-n = segment driver n. The ON/OFF bit indicates the current status of the display. It is the inverse of the polarity of the display ON/OFF command. ON/OFF=1: Display OFF ON/OFF=0: Display ON The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode, RESET=1: Currently executing reset command. RESET=0: Normal operation Low column set High column set

Ver 1.0c 22/45 2002/07/10 ¾ Write Display Data A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write data Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page, address registers and then increments the column address register by one. ¾ Read Display Data A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read data Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data RAM location specified by the contents of the column address and page address registers and then increments the column address register. After loading a new address into the column address register one dummy read is required before valid data is obtained. ¾ Start line set A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 0 Display start address Loads the RAM line address of the initial display line, COM 0,into the initial display line register. The RAM display data becomes the top line of the LCD screen. It is followed by the higher number lines in ascending order, corresponding to the duty cycle. The screen can be scrolled using this command by incrementing the line address.(default value=”00H”) ¾ Select ADC A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 0 0 A The command selects the relationship between display data RAM column addresses and segment drivers. A=1: SEG0 ← column address 5FH, … inverted A=0: SEG0 ← column address 00H, … normal (default) This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit Board design. See Figure 4 for a table of segments and column addresses for the two values of D.

Ver 1.0c 23/45 2002/07/10 ¾ Display Normal/Reverse A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 1 R This command can reverse the lit and unlit display without overwriting the contents of the display data RAM(with ICON). When this is done. the display data RAM contents are maintained R=1: Reverse R=0: Normal(default) ¾ Display All Points ON/OFF A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 0 L This command makes it possible to force all display points ON regardless of the content of the display data RAM(with ICON). The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. L=1: All display points ON. L=0: Normal(default) Compound command priority follow below table Display all point on Display reverse Display on Display on All point black Display reverse Display on Display reverse All point white Display reverse Display reverse Display all point on Display all point on All point white All point black

Ver 1.0c 24/45 2002/07/10 ¾ Read-Modify-Write A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 This command defeats column address register auto-increment after data reads. The current contents of the column Address register are saved. The mode remains active until an End command is received. When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write Command. This function can reduce the load of MPU when data change is repeated as a specific display area. *Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column Address Set command cannot be used. ¾ End A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 This command cancels read-modify-write mode and restores the contents of the column address register to their value prior to the receipt of the Read-Modify-Write command. Set page address Set column address Read-modify-write Dummy read Read data Write data End Completed? No Yes N N+1 N+2 N+3 N+m N Read -modify-write mode set End Returm Column address

Ver 1.0c 25/45 2002/07/10 ¾ Select Duty A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 0 U U=1: 1/33 duty cycle (When double chip was be used, then both chip must set duty together ) U=0: 1/17 duty cycle (default) ¾ LCD bias set A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 0 1 I I=1:1/5 bias I=0:1/6 bias (default) ¾ Reset A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 0 This command initializes the column address, the page address, the start line, the electric volume, and the static indicator are reset, and the read/modify/write mode are released. There is no impact on the display data RAM. The reset operation is performed after the reset command is entered. Their default states are as follows: 1. Column address set to Address 0 2. Page address set to Page0 3. Start line set to first line 4. Electronic contrast re gister = 35H(max=3FH) 5. Static drive is turned OFF 6. Read modify write OFF

Ver 1.0c 26/45 2002/07/10 ¾ Power control A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 B x F B=1: set booster circuit on, which makes Vcap3 has 2 time voltage B=0: set booster circuit off, which make Vcap3 have 1 time voltage only. (default) F=1: set follower circuit on, the V5 electric volume can adjust by internal follower circuit with command set. F=0: set follower circuit off, the V1~V5 must connect to external voltage divider and adjust V5 level by external divider. (default) B F Step- up circuit Follower circuit External input voltage 0 0 Open Open Vcap3 connect to V5 V1~V5 connect to external resistor 0 1 Open Used Vcap3 connect to external power supply 1 0 Used Open V1~V5 connect to external resistor 1 1 Used used - Booster and follower on/off condition table Note: ensure V5 level stable, that must let |Vcap3-V5| over 0.5V(if panel size over 4.5”,the |Vcap3-V5| propose over 0.8V). VDD Vcap3 VDD VSS VCC GND |Vcap3-V5|>0.5V(minimum) (System side) (ST7522 Side)

Ver 1.0c 27/45 2002/07/10 ¾ The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V5. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. That command can operate in master chip for master + slave mode. The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1 Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 Electronic volume Default value=“35H” D7 D6 D5 D4 D3 D2 D1 D0 V5 level 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 Small Large The Electronic Volume Register Set Sequence Electronic volumn mode set Electronic volumn register set YES NO Change complete

Ver 1.0c 28/45 2002/07/10 ¾ OSC frequency set(Double Byte Command) This command is designed for frame frequency adjustment, which can provide about 50% variation of frame frequency to avoid the interference with the frequency of daylight lamp in different countries. This command is a two byte command used as a pair with the OSC frequency mode set command and the OSC frequency register set command, and both commands must be issued one after the other. The OSC frequency mode set A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 0 0 0 1 OSC frequency register set A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 Josc3 Josc2 Josc1 Josc0 Default value=“08H” Josc3 Josc2 Josc1 Josc0 CL Frequency 0 0 0 0 Slow 0 0 0 1 1 1 1 1 Fast Frequency for “OSC frequency set” command Conditions: 1. VDD=3.0V 2. Use internal OSC circuit 500 1000 1500 2000 2500 3000 3500 Josc[3,0] CL frequency[Hz] CL-1/17 CL-1/33 100 Josc[3,0] FR frequency[Hz] FR-1/17 FR-1/33

Ver 1.0c 29/45 2002/07/10 ¾ Follower input voltage set(Double Byte Command) V5 amplifier input voltage can be set by this command, which provide coarse adjustment only. This command needs to be used with the electric volume control command in order to get correct V5 output. This command is a two byte command used as a pair with the follower input voltage mode set command and the follower input voltage register set command, and both commands must be issued one after the other. See the power control explanation for details. The follower input voltage mode set A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 1 0 0 0 Follower input voltage register set A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 0 0 Jvref1 Jvref0 Default value=“02H” Jvref1 Jvref0 V5 input voltage 0 0 4/6*V SS 0 1 3/6*V SS 1 0 2/6*V SS(default) 1 1 1/6*V SS Follower input voltage parameter ¾ Follower amplified ratio This command sets the V5 voltage internal resistor ratio. that can control V5 level with follower input voltage set command and electric volume command. See the power control explanation for details. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 0 RaRb2 RaRb1 RaRb0 Default value=“06H” Rarb2 Rarb1 Rarb0 V5 amplified ratio 0 0 0 2 0 0 1 2.5 0 1 0 3 0 1 1 3.5 1 0 0 4 1 0 1 4.5 1 1 0 5(default) 1 1 1 5.5 Follower amplified ratio parameter

Ver 1.0c 30/45 2002/07/10 The V5 level be generate by OPAmp with VDD-Vcap3 power supply, so that V5 level must to be smaller than Vcap3 over –0.5V. Fine adjustment must to used EC[5:0] adjust of Electronic contrast set command. Coarse adjustment must to used jvref[1:0] adjust of Follower input voltage set command. For V5 voltage level setup formula: (follower must on of power control command) (used follower input voltage set and amplified ratio command) Rvref 200K 400K (default) 600K 800K Rarb2 Rarb1 Rarb0 V5 amplified ratio 0 0 0 2 0 0 1 2.5 0 1 0 3 0 1 1 3.5 1 0 0 4 1 0 1 4.5 1 1 0 5(default) 1 1 1 5.5 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 Contrast[5,0] Bias voltage[V] Test condition: 1. VDD=3.0V 2. Booster/Follower=Default set 3. Bias=1/6 4. Only master chip RaRb[2:0] VDD Vcap3 VDD VSS Electric volumn EC[5:0] Reference voltage jvref[1:0] VDD F (power control command) Vref [3FH-EC volume] x 20KΩ=REC The value of Vref is not allowed to be lower than 1.2V within the contrast adjustment range. Rvref 1M+REC [] x V5 amp ratio x (VSS-VDD)= V 5 (±5% range) Rvref 1M+REC [] x (VSS-VDD) =Vref

Ver 1.0c 31/45 2002/07/10 3571 Operating range Operating voltage range of Vss and Vcap3 system VDD VDD-Vcap3 ¾ Booster input voltage set (Double Byte Command) This command is designed to select different level of the input voltage to booster. In 5V application system, it’s better to reduce the input voltage of booster to make sure that the output voltage of booster will not be over the specification range of VDD-Vcap3. This command is a two byte command used as a pair with the booster input voltage mode set command and the booster input voltage register set command, and both commands must be issued one after the other. See the power control explanation for details. The booster input voltage mode set A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 0 0 0 0 Booster input voltage register set. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 Jbst1 Jbst0 0 0 0 0 0 0 Default value=“00H” Jbst1 Jbst0 VSS2 0 0 1*VSS(default) 0 1 4/5*VSS 1 0 3/5*VSS 1 1 2/5*VSS Booster input voltage parameter For Vcap3 voltage level setup formula: (booster must on of power control command) (used booster input voltage set command) Vcap3=VSS2 x 2 (booster must on of power control command) VDD VSS input voltage jbst[1:0] Vcap3=VSS2 x 2 Booster VSS2 Vcap3 B (power control command)

Ver 1.0c 32/45 2002/07/10 Reference circuit examples: When used 2x step-up voltage circuit, the “Power control” command must set to 2DH and adjust “Booster input voltage set” command of Vcap3’s full range. When used 1x step-up voltage circuit, the “Power control” command must set to 29H; the “Booster input voltage set” command is not action at this operation. CAP1 CAP2 CAP3 VDD M/S VSSVDD Cb Cb VDD CAP1 CAP2 CAP3 VDD M/S VSSVDD VDD Open Open 2x step-up voltage circuit (Power control=2DH) 1x step-up voltage circuit (Power control=29H) VDD=0V VSS=-3V Vcap3=Jbst[1,0] x (VSS-VDD) x 2 VDD=0V VSS=-3V Vcap3=(VSS-VDD) x 1

Ver 1.0c 33/45 2002/07/10 ¾ Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the COMS terminal, and the other is connected to the S1~S4 terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paire d with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.) Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 0 S S=1: Indicator on S=0: Indicator off (default) Static Indicator Register Set This command sets four bits of data into the static indicator register, and is used to set the static indicator into a on/off mode A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 S1 S2 S3 S4 the command selection the S1-S4 static indicator on or off. Sn=1: Sn -> on Sn=0: Sn -> Off(default) Static Indicator Register Set Sequence Static indicator mode set Static indicator register set No On Off Yes Change complete?

Ver 1.0c 34/45 2002/07/10 ¾ Power Save (Compound Command) When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When all static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was ineffect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1. The oscillator circuit and the LCD power supply circuit are halted. 2. All liquid crystal drive circuits are halted, and the segment and common drive outputs output a V DD level. Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1. The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2. The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. * When the master is turned on, the oscillator circuit is operable immediately after the powering on. * When the master/slave mode, into Sleep or Standby mode have to at same time. Static indicator off (Static off only) Display off Display all point on Sleep mode Display on or Display all point off Sleep cancel Static indicator on (Static on + Static register set) Display off Display all point on Stand by mode Display on or Display all point off Stand by cancel

Ver 1.0c 35/45 2002/07/10 SSooffttwwaarree EExxaammppllee Condition: 1. VDD=5.0V 2. Use Winbond W78E52-40 at 16MHz crystal(compatible intel 8051 MPU) 3. Use Mater and Slave mode(ST7522D x 2) 4. |VCAP3|=(5x2)x3/5=6V 5. |V5|=[600K Ω/(1MΩ+200KΩ)]x2x5=5V ;Reset CLR RES ;Reset ST7522D(Master & Slave) CALL DELAY ; SETB RES CALL DELAY ; ;Initial LCD CLR CS1 ;Enable chip 1(low active) CLR CS2 ;Enable chip 2(low active) MOV A,#11110001B ;OSC frequency set CALL WRINS ; MOV A,#10001000B ; Frame about 80.6Hz/OSC frequency about 2.6KHz CALL WRINS ; MOV A,#11111000B ;Follower input voltage set CALL WRINS ; MOV A,#00000001B ; V5 input voltage=3/6*VSS CALL WRINS ; MOV A,#00100000B ;Follower amplified ratio CALL WRINS ; Ratio=2 MOV A,#11110000B ;Booster input voltage set CALL WRINS ; MOV A,#10000000B ; VSS2=3/5 *VSS CALL WRINS ; MOV A,#00101111B ;Power control CALL WRINS ; MOV A,#10101001B ;Duty select CALL WRINS ; MOV A,#10100010B ;LCD bias set CALL WRINS ; MOV A,#10000001B ;Electronic contrast set CALL WRINS ; MOV A,#00110101B ; Contrast register=35H CALL WRINS ; CALL DELAY200mS ; Delay 200mS for booster & follower stable MOV A,#10101111B ;Display on CALL WRINS ;

Ver 1.0c 36/45 2002/07/10 AABBSSOOLLUUTTEE MMAAXXIIMMUUMM RRAATTIINNGGSS Characteristics Symbol Value Unit Power supply voltage V DD -0.3 to +7.0 V LCD driver voltage Vcap3 -7.0 to +0.3 V Input voltage V IN -0.3 to V DD+0.3 V Operating temperature T A -40 to +85 ℃ Storage temperature T STO -55 to +125 ℃ DDCC CCHHAARRAACCTTEERRIISSTTIICCSS Unless otherwise specified, VSS = 0 V, VDD = 3.0 V Rating Item Symbol Condition Min. Typ. Max. Unit Applicable Pin Operating Voltage VDD - 2.7 3.0 5.5 V V DD*1 Step up output voltage Vcap3 (Relative to V DD) -7 - -3.5 V CAP3 Voltage follower circuit operating Voltage V5 (Relative to V DD) -7 - -3.5 V V5 V5 accuracy V5 - -7 - 7 % V5 High-level Input Voltage Low-level Input Voltage VIHC VILC - 0.7 VDD Vss - VDD

0.9 V *2

IOH = –0.5 mA IOL = 0.5 mA 0.8VDD Vss - VDD

0.2 VDD V *3

Input leakage current I LI V IN = VDD or VSS -1 - 2 uA *4 Output leakage current I LO - -1 1 uA *5 Liquid Crystal Driver ON Resistance RON Ta = 25°C (Relative To V DD) V5 = –6.0 V - 1.6 2.0 KΩ SEGn COMn *6 Internal Oscillator f OSC 2 - 3 Oscillator Frequency External Input RECOMMAND fCL Ta = 25°C 1/33Duty 2 - 3.5 kHz CL

Ver 1.0c 37/45 2002/07/10

• Dynamic Consumption Current, During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used. Display Pattern OFF Ta = 25°C Vcap3=-6V Rating Item Symbol Condition Min. Typ. Max. Unit Notes VDD=3.0 V, VDD-V5=-5.0V - 10 15 ST7522 I DD VDD=5.0 V, VDD-V5=-5.0V - 35 45 μA *7 Display Pattern Checker Ta = 25°C Vcap3=-6V Rating Item Symbol Condition Min. Typ. Max. Unit Notes VDD=3.0 V, VDD-V5=-5.0V - 15 20 ST7522 I DD VDD=5.0 V, VDD-V5=-5.0V - 40 50 μA *7
• Dynamic Consumption Current, During Display, with the Internal Power Supply ON Display Pattern OFF Ta = 25°C Vcap3=-6V Rating Item Symbol Condition Min. Typ. Max. Unit Notes VDD=3.0 V, VDD-V5=-5.0V - 60 70 ST7522 I DD VDD=5.0 V, VDD-V5=-5.0V - 120 130 μA *7 Display Pattern Checker Ta = 25°C Vcap3=-6V Rating Item Symbol Condition Min. Typ. Max. Unit Notes VDD=3.0 V, VDD-V5=-5.0V - 65 80 ST7522 I DD VDD=5.0 V, VDD-V5=-5.0V - 130 150 μA *7
• Consumption Current at Time of Power Saver Mode, VSS = 0 V, VDD = 3.0 V ± 10% Ta = 25°C Rating Item Symbol Condition Min. Typ. Max. Unit Notes Sleep mode I DD - - 5 10 Standby Mode I DD - - 10 15 μA - References for items market with * *1 While a broad range of operating voltages is guarantee d, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1 , CS2, CLS, CL, FR, M/S, C86, P/S , and RES terminals. *3 The D0 to D7, FR and CL terminals. *4 The A0, RD (E), WR (R/W), CS1 , CS2, CLS, M/S, C86, P/S, and RES terminals. *5 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, and FR terminals are in a high impedance state. *6 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V 1, V 2, V 3, and V 4). These are specified for the operating voltage (3) range. RON = 0.1 V /ΔI (Where ΔI is the current that flows when 0.1 V is applied while the power supply is ON.) *7 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU.

Ver 1.0c 38/45 2002/07/10 TTIIMMIINNGG CCHHAARRAACCTTEERRIISSTTIICCSS

68 Interface

(Ta = –40 to 85°C ) VDD=2.7 to 4.5V Rating VDD=4.5 to 5.5V Rating Item Signal Symbol Condition Min. Max. Min. Max. Units Address hold time A0 tAH6 10 — 10 — Address setup time A0 tAW6 25 — 10 — ns System cycle time A0 tCYC6 — 4400 — 3500 — ns Data setup time D0 to D7 tDS6 25 — 25 — Data hold time D0 to D7 tDH6 10 — 10 — ns Access time D0 to D7 tACC6 — 90 — 60 Output disable time D0 to D7 tOH6 CL = 100 pF — 1100 — 1100 ns Read tEWHR 260 — 160 — Enable H pulse time Write E tEWHW 260 — 160 — ns Read tEWLR 200 — 140 — Enable L pulse time Write E tEWLW 2300 — 1200 — ns *1 All timing is specified using 20% and 80% of VDD as the reference. *2 tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E. tAW6 tAH6 tDS6 tDH6 tACC6 tOH6 tEWHR,tEWHW tCYC6 tEWLR,tEWLW R/W E D0 to D7 (Write) D0 to D7 (Read) CS1 CS2

Ver 1.0c 39/45 2002/07/10

80 Interface

(Ta = –40 to 85°C ) VDD=2.7 to 4.5V Rating VDD=4.5 to 5.5V Rating Item Signal Symbol Condition Min. Max. Min. Max. Units Address hold time tAH8 10 — 10 — Address setup time A0 tAW8 — 10 — 10 — ns System cycle time A0 tCYC8 — 3400 — 1300 — ns Control L pulse width (WR ) WR tCCLW 350 — 160 — Control L pulse width (RD ) RD tCCLR 530 — 200 — Control H pulse width (WR ) WR tCCHW 1100 — 1100 — Control H pulse width (RD ) RD tCCHR 730 — 530 — ns Data setup time tDS8 25 — 10 — Address hold time D0 to D7 tDH8 — 10 — 10 — ns RD access time tACC8 — 70 — 70 Output disable time D0 to D7 tOH8 CL = 100 pF — 1200 — 1100 ns *1 All timing is specified using 20% and 80% of VDD as the reference. *2 tCCLW and tCCLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and WR and RD being at the “L” level. tAW8 tAH8 tDS8 tDH8 tACC8 tOH8 tCCLR,tCCLW tCYC8 tCCHR,tCCHW D0 to D7 (Write) D0 to D7 (Read) CS1 CS2 WR,RD

Ver 1.0c 40/45 2002/07/10 Serial Interface (Ta = –40 to 85°C ) VDD=2.7 to 4.5V Rating VDD=4.5 to 5.5V Rating Item Signal Symbol Condition Min. Max. Min. Max. Units Serial Clock Period tSCYC 500 — 400 — SCL “H” pulse width tSHW 100 — 300 — SCL “L” pulse width SCL tSLW 200 — 120 — ns Address setup time tSAS 0 — 0 — Address hold time tSAH 100 — 100 — ns Data setup time tSDS 0 — 0 — Data hold time SI tSDH 120 — 100 — ns tCSS 60 — 40 — CS-SCL time CS tCSH 2200 — 1000 — ns *1 All timing is specified using 20% and 80% of VDD as the standard. tCSS tCSH tSDS tSDH tSLW tSCYC tSHW SCL SI tSAS tSAH CS1 CS2

Ver 1.0c 41/45 2002/07/10 Reset Timing Internal status tR During reset Reset complete RES tRW Figure 41 Table 36 Rating Item Signal Symbol Condition Min. Typ. Max. Units Reset time — tR — — 1 100 μs Reset “L” pulse width RES tRW — 0.2 1 — μs *1 When double chip was be used, then the duty set command must be set between the tR

Ver 1.0c 42/45 2002/07/10 II//OO PPAADD CCOONNFFIIGGUURRAATTIIOONN Input PAD VSS VDD VDD VSS I/O PAD VDD VSS VSS VDD VDD VSS VDD P MOS N MOS I/O PAD:D0,D1,D2,D3,D4,D5 Pull up control I/O PAD VDD VSS VSS VDD VSS VDD P MOS N MOS I/O PAD:D6,D7,FR,CL Input PAD: RES,P/S,/CS1,CS2,CLS, E(/RD),R/W(/WR),A0,C86,M/S D0~D5 into pull up mode when P/S set to VSS(Serial interface), but P/S set to VDD(Parallel interface), D0~D5 will be without pull up MOS connected.

Ver 1.0c 43/45 2002/07/10 TTHHEE MMPPUU IINNTTEERRFFAACCEE ((RREEFFEERREENNCCEE EEXXAAMMPPLLEESS)) The ST7522 Series can be connected to either 80x86 Series MP Us or to 68000 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7522 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7522 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs GND VCC DECODER VSS VDD VDD ST7522 P/S C86 MPU CS1 CS2 D0 to D7 RD WR RES RESET A1 to A7 IORQ D0 to D7 RD WR RES (2) 6800 Series MPUs GND VCC DECODER VSS VDD VDD ST7522 P/S C86 MPU CS1 CS2 D0 to D7 E R/W RES RESET A1 to A15 VMA D0 to D7 E R/W RES (3) Using the Serial Interface GND VCC DECODER VSS VDD VDD ST7522 P/S MPU CS1 CS2 D0 to D5 SI SCL RES RESET A1 to A7 PORTA PORTB RES C86

Ver 1.0c 44/45 2002/07/10 AAPPPPLLIICCAATTIIOONN ((MMaasstteerr && SSllaavvee MMooddee)) Condition: 1. 2 time booster 2. internal follower 3. internal OSC frequency 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COMI COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 COMS P/S CL VSS /CS1 CS2 E R/W VDD C86 RES CLS FR M/S CAP1 CAP2 CAP3 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 ST7522 Master 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 COMS P/S CL VSS /CS1 CS2 E R/W VDD C86 RES CLS FR M/S CAP1 CAP2 CAP3 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 COMI COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 ST7522 Slave 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 LCD 33 x 160 dots P/S C86 CLS VDD VSS VSS VDD Vout R/W E CS1 CS2 RES CL VDD VDD VDD 2.2uF 4.7uF 2.2uF 4.7uF 1uF 2.2uF 2.2uF 4.7uF 2.2uF 4.7uF 2.2uF 2.2u~4.7uF 2.2uF 2.2u~4.7uF Viewing area=3.0" Viewing area=4.5" Panel size Capacitor Notice: Slave chip's common & segment pin had changed follow "PIN DESCRIPTION" table

Ver 1.0c 45/45 2002/07/10 APPLICATION(Only use master mode) Resemble ST7066U+ST7065C (2 line x 16 word with 14 pin assign application) condition: 1. 68 interface 2. 2 time booster 3. internal follower 4. internal OSC frequency LCD 17 x 96 dots 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COMI COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 COMS P/S CL VSS /CS1 CS2 E R/W VDD C86 RES CLS FR M/S CAP1 CAP2 CAP3 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 ST7522 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 VDD 2.2uF 4.7uF 2.2uF 4.7uF 1uF 2.2uF 2.2uF 4.7uF 2.2uF 4.7uF 2.2uF 2.2u~4.7uF 2.2uF 2.2u~4.7uF Viewing area=3.0" Viewing area=4.5" Panel size Capacitor VSS VDD RES R/W E