DPAD1 CALOGIC | Alldatasheet
Document overview
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Technical content
DPAD1 / DPAD2 / DPAD5 / DPAD10 / DPAD20 / DPAD50 / DPAD100 SSTDPAD5 / SSTDPAD10 / SSTDPAD20 / SSTDPAD50 / SSTDPAD100
FEATURES
- • Matched Capacitance
APPLICATIONS
- • Op Amp Protection Devices
- • Diode Switching
- • High Impedance Protection
DESCRIPTION
Calogic’s ultra low leakage dual pico amp diodes out perform conventional diodes for applications where reverse current (leakage) is critical and must be kept at a minimum. The devices have very low capacitance and are also fast switching. Housed in a compact dual hermetic package and a plastic surface mount SO-8 this product is also available in chip form for hybrid uses.
ORDERING INFORMATION
Part Package Temperature Range DPAD1 Hermetic TO-78 -55 to +150 oC DPAD2/50 Hermetic TO-71 -55 to +150 oC SSTDPAD5/100 Plastic SO-8 -55 to +150 oC XDPAD5/100 Sorted Chips in Carriers -55 to +150oC CORPORATION SCHEMATIC DIAGRAM TO-71 (MODIFIED) (PINS 2 AND
6 REMOVED)
(MODIFIED) (DPAD1 ONLY) A C A C BOTTOM VIEW (ALTERNATE) A 1 C 1 A 2 C 2 A 1 C 1 A 2 C 2 C BOTTOM VIEW CASE PIN CONFIGURATION SO-8 N/C N/C CJ1, CJ2, CJ4
DPAD1 / DPAD2 / DPAD5 / DPAD10 / DPAD20 / DPAD50 / DPAD100 SSTDPAD5 / SSTDPAD10 / SSTDPAD20 / SSTDPAD50 / SSTDPAD100 CORPORATION ABSOLUTE MAXIMUM RATINGS (25 oC) T otal Device Dissipation @ TA = 25oC ELECTRICAL CHARACTERISTICS (25oC unless otherwise noted) SYMBOL CHARACTERISTICS MIN TYP MAX UNIT TEST CONDITIONS STATIC IR Reverse Current pA VR = -20 V DPAD1 -2 DPAD2 -5 DPAD5 -10 DPAD10 -20 DPAD20 -50 DPAD50 -100 DPAD100 BV R Breakdown Voltage (Reverse) -45 -120 V IR = -1µA DPAD1, 2, 5 -35 DPAD10, 20, 50, 100 VF Forward Voltage Drop 0.8 1.5 I F = 5 mA DPAD1, 2, 5, 10, 20, 50, 100 DYNAMIC C R Capacitance 0.8 pF V R = -5 V, f = 1 MHz DPAD1, 2, 5
2.0 DPAD10, 20, 50, 100
| CR1 - CR2 | Differential Capacitance 0.1 0.2 pF V R1 = VR2 = -5 V, f = 1 MHz DPAD1, 2, 5, 10, 20, 50, 100 APPLICATION Operational Amplifier Protection. Input Differential Voltage limited to 0.8 V (typ) by DPADS D1 and D2 Common mode input voltage limited by DPADS D3 and D4 to ±15V. T ypical sample and hold circuit with clipping, DPAD diodes reduce offset voltages fed capacitively from the FET switch gate. DPAD10 -15V+15V D 3 I < 1 pAR +V -V DPAD1 VOUT C CONTROL SIGNAL ein DPAD1 J110 J210