SSP1601 SAMSUNG | Alldatasheet

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Samsung is a pioneer in the DSP core approach, which is a high performing and flexible family of DSP core based ASDSP(Application Specifics Digital Signal Processor). The DSP core architecture and instruction set are designed simplicity and flexibility. The DSP core contains only the most essential DSP function blocks. Because all intemal buses are accessible extemally. The ASDSP is an application specifics integrated circuit that incorporates a programmable digital signal processor core. The ASDSP approach allows the system designer to integrate a programmable dsp core, interface logic, peripheral, extra memory into a single integrated circuit. Typically, the custom circuitry on a ASDSP is implemented either in standard cell or gate array. All methods used samsung process by 0.8um double metal CMOS technology. The SSP1601 uses 0.8um CMOS technology(CSP4H) and can perform up to 25 MHz at 5V. The SSP1601 DSP cores have the following on-chip functions: two independent high-speed RAM bants, a 16 x 16 multiply unit, an 32-bit ALU , RAM address pointers, a status register, a program control unit, and an extemal bus control unit. The DSP core can address up to 64K-word of extemal ROM over an extemal data bus. The actual size of the extemal ROM area used depends upon the requirements of the individual application. The SSP1601 has five 16-bit buses and one 32-bit bus; program address (PA) bus, program data (PD) bus, multiplier (M) bus, extemal (EXT) bus, subsidiary (S) bus, data (0) bus, mpya_ instructions (add, load, multiply, and modify RAM address pointer) are executed efficiently within one machine cycle.The condition flags in the status register (ST) are set or cleared by the corresponding ALU operations. Values for the status register control bits are loaded by application software or through the /O pins USRO, USR1, ST5, and ST6. The system stack has six hardware levels and operates using Push and Pop operations. The pins EA[2:0], ESB, and R/WB are used to contro! the EXT bus, and the RESB, INTO, INT1, INT2, and SS pins are used to control system functions. Key Features Design Tools ™ 16-bit fixed point arithmetic As part of its total support commitment, ™ ACC + Ax B > ACC; MAC operation in 40 SASUNG backs up the SSP1601 with a set of ns using pipelined muttiplier high level software and hardware tools. . aenattanuies multiply with 32-bit output = Software Tools : running on PC eration > Macro-assembler (MASM1601) = 512-word data RAM ; RAMO, RAM1 is = Eight 8-bit RAM point ist ted > Linker (LNK1601) ig! point register are existed, > ROM Spitter (RSP1601) RO ~ R3 are for RAMO, > Simulator (SIM1601) R4 ~ R7 are for RAM1. = RAM pointer registers for easy circular buffer = Hardware Tools : running on PC . ceente struct ' > Realtime Emulator (SDE1601) P lon sel > Algorithm Development Board = User defined I/Os (SDAP1601) ™ Up to 64K word Program Memory which can be readable and writable . i : fl ™ SSP1601 EVA Chip has two 256.word pesian Teele = running on SUN (Unix) erilog model SRAM for each RAM banks , > Macrocells dedicated to the DSP core = 25 MIPS @ 5.0 Volt i sts = 68 - pin PLCC (evaluation version) to build user's applications. = 08 doubl tal CMOS (CSP. >» Standard cell library, /O library and -Sum double metal (CSP4H) Data path generator = Excepted core size (except PAD, Data RAM): > Memory Generator (ROM, RAM) 3600um x 2400um a CD-ROM(Edition 3.0) This Data Sheet is subject to change without notice. (C) 1996 Samsung Electronics. Printed in Korea. Page : 1 (SSP1601 ) M@@ 7964142 0031915 344 mm

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status: is Rau” Ret TACK) eT | ass x ws) (Ee! [ass x 6 Multiplier | ; | Z 3oM-bus ! i | D-bus 8 | | RESB EA(20) Program Control Program ROM nos On-chip [ESB i , ripheral] "RWB unt (External) usRo-1=4" 'l=sTs, ST6 Pin Layout IURUBUBUBUBU! PEEEEEELE PELE EEED See 2 22559590959 59955 AEPWNACOBNDDTA WN Pn vss C] set 4 ste6 Pbo C4 /) sT5 Pp1 CJ 1) INT2 PD2 i iNT1 Pb3 CI |] INTO pp4 —<e [1 usR pps C4 | >< 1] USRO Pps C] — — ss Po7 C] r] PHi0 Pps CI 1] CK1 ppo CI SSP1601 P ox Polo = 16-bit Fixed Point 5 voo Pp12 C DSP Core |] ESB Pbd13 C4 i] EA2 PD14 CJ 1] EA1 pp15 C4 |] EAO UUUUUUUUUUUUUUUU uv BERSESELE SES SEES

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CD-ROM(Edition 3.0) This Data Sheet is subject to change without notice. (C) 1996 Samsung Electronics Printed in Korea. Page :2 (SSP1601 ) Mi 7964142 O0O31L91b 280

Name Number vo Description Intemal clock output | PH10B | Inverted output of PH1 generated from CK1 | Asynchronous step Effective when CK1 is rising 53 | \\ Asynchronous single step { Effective when CK1 of a cycle is rising ~ as ees | INTO 56 Interrupt request 0 | INT1 57 1 Interupt request 1 | INT2 58 Interrupt request 2 PAO-PA15S 2735 & | og ip dd rogram address 37-43 9 PADO-PD15 11-26 | VO | Program data | EXTO-EXT15 198 VO | Extemal data bi ia bus 61-68 EAO-EA2 44-46 Extemal register address oo — T RWB 48 ae) Read/write timing signal for EXT bus usRO 54 | | User input 0 uUSRI1 55 | User input 1 STs 59 | User output 0 ST6é 60 | User output 1 SS CD-ROM(Edition 3.0) This Data Sheet is subject to change without notice. (C) 1996 Samsung Electronics Printed in Korea. Page :3 (SSP1601) MH 7964142 0031917 117 a

Voo to Vss Voo 0.7 Vv Input voltage v | Voo + 0.5 to - 0.5 Vv | | Output voltage Vo | Voo + 0.5 to - 0.5 vo | | storage temperature Ts 65 to + 150 c Lead temperature(Soldering) an Less than 300 Cc DC Characteristics Characteristics | Symbol Condition | Min | tye | max | unit | Operating current loo. CK = 25 MHz | mA | Input voltage high Vin 0.9Vo0 Vv Input Leakage current iN 1 | ft | Output voltage high | Vow low = -100 pA Voo=0.2 | || vo} Output voltage low Vou ln = 0.5 mA | | os | v | Output current in high \\ ! impedance state oe uA Sa, CD-ROM(Edition 3.0) This Data Sheet is subject to change without notice. (C) 1996 Samsung Electronics Printed in Korea. Page : 4 (SSP1601 ) @m@ 7964142 0031918 O53

i AC Characteristics Symbol Min | Typ Max Unit | Clock cycle time Toy mi 1000 | 40 : oo Clock pulse width Pow | | EA.RMB delay from CK1 En js | | “ext peatnae deny ton okt | te || | EXT floating delay from CK1 Tre | o | | | | EXT data output delay from CK1 ow || | | EXT data output hold from CK1 | om | .« | | | : EXT data input setup time ns | EXT data input hold time f | ESB delay time Tewan 16 | | ‘omen | tm | | PD input hold time Tron 6 CD-ROM(Edition 3.0) This Data Sheet is subject to change without notice. (C) 1996 Samsung Electronics Printed in Korea. Page :5 (SSP1601 ) Mm 7964142 0031919 TIT