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Technical content

-9.0 A, -40 V , RDS(ON) 35 m P-Ch Enhancement Mode Power MOSFET 31-Dec-2010 Rev. B Page 1 of 2 http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. A H B M D C J K F L E N G RoHS Compliant Product A suffix of “-C” specifies halogen & lead-free

DESCRIPTION

These miniature surface mount MOSFETs utilize a high cell density trench process to provide low RDS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters and power management In portable and battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones.

FEATURES

 Low RDS(on) provides higher efficiency and extends battery life.  Low thermal impedance copper leadframe SOIC-8 saves board space.  Fast switching speed.  High performance trench technology.

PACKAGE INFORMATION

SOP-8 2.5K 13’ inch MAXIMUM RATINGS (TA = 25°C unless otherwise specified) Parameter Symbol Ratings Unit Drain-Source Voltage V DS -40 V Gate-Source Voltage V GS ±20 V ID @ TA = 25°C -9.0 A Continuous Drain Current 1 ID @ TA = 70°C -7.3 A Pulsed Drain Current 2 I DM ±50 A Continuous Source Current (Diode Conduction) 1 I S -2.1 A PD @ TA = 25°C 3.1 W Total Power Dissipation 1 PD @ TA = 70°C 2.6 W Operating Junction & Storage Temperature Range T J, TSTG -55 ~ 150 °C Thermal Resistance Ratings t≦10 sec 50 °C / W Thermal Resistance Junction-ambient (Max.) 1 Steady State RθJA 92 °C / W Notes: 1. Surface Mounted on 1” x 1” FR4 Board. 2. Pulse width limited by maximum junction temperature. SOP-8 A 5.80 6.20 H 0.35 0.49 B 4.80 5.00 J 0.375 REF. C 3.80 4.00 K 45 ° D0 ° 8 ° L 1.35 1.75 E 0.40 0.90 M 0.10 0.25 F 0.19 0.25 N 0.25 REF. G 1.27 TYP. S S S GD D D D

-9.0 A, -40 V , RDS(ON) 35 m P-Ch Enhancement Mode Power MOSFET 31-Dec-2010 Rev. B Page 2 of 2 http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Symbol Min. Typ. Max. Unit Teat Conditions Static Gate Threshold Voltage V GS(th) -1 - - V V DS= VGS, ID= -250μA Gate-Body Leakage Current I GSS - - ±100 nA V DS= 0V, VGS= ±25V - - -1 μA V DS= -24V, VGS= 0V Zero Gate Voltage Drain Current I DSS - - -5 μA V DS= -24V, VGS= 0V, TJ=55°C On-State Drain Current 1 I D(on) -50 - - A V DS= -5V, VGS= -10V - - 35 VGS= -10V, ID= -9.0A Drain-Source On-Resistance 1 R DS(ON) - - 45 mΩ VGS= -4.5V, ID= -7.2A Forward Transconductance 1 g fs - 31 - S V DS= -15V, ID= -9.0A Diode Forward Voltage V SD - -0.7 - V I S= -2.1A, VGS= 0V Dynamic 2 Total Gate Charge Q g - 15.3 - Gate-Source Charge Q gs - 5.2 - Gate-Drain(“Miller”) Charge Q gd - 5.8 - nC ID= -9.0A VDS= -15V VGS= -4.5V Turn-On Delay Time T d(on) - 15 - Rise Time T r - 12 - Turn-Off Delay Time T d(off) - 62 - Fall Time T f - 46 - nS VDD= -15V, ID= -1A VGEN= -10V, RL= 15Ω RG= 6Ω Notes: 1. Pulse test :PW ≦ 300 μs duty cycle ≦ 2%. 2. Guaranteed by design, not su bject to production testing.