SS2412

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CMOS High Sensitivity Micropower Hall Latch 1 V3.10 Nov 1, 2013 Features and Benefits – Micropower consumption for battery pow- ered applications – Latching output – Operation down to 2.5V – High sensitivity for direct reed switch re- placement applications – Chopper stabilized amplifier stage Application Examples – Solid state switch – Handheld Wireless Handset Awake Switch – Lid close sensor for battery powered devices 3 pin SOT23 (suffix SO) 3 pin SIP (suffix UA) Functional Block Diagram VDD OUT Sleep/Awake Li Chopper Hall GND

CMOS High Sensitivity Micropower Hall Latch 2 V3.10 Nov 1, 2013 General Description The SS2412 latching Hall effect sensor IC is fabr i- cated from mixed signal CMOS technology . It incor- porates advanced chopper -stabilization techniques to provide accurate and stable magnetic switch points. The circuit design provides an internally controlled clocking mechanism to cycle power to the Hall el e- ment and analog signal processing circuits. This serves to place the high current -consuming portions of the circuit int o a “Sleep” mode. Periodically the device is “Awakened” by this internal logic and the magnetic flux from the Hall element is evaluated against the predefined thresholds. This device r e- quires the presence of both south and north polarity magnetic fields for operation. In the presence of a south polarity field of sufficient strength, the device output latches on, and only switches off when a north polarity field of sufficient strength is present. While in the “Sleep” cycle t he output transistor is latched in its previous state. The design has been o p- timized for service in applications requiring extended operating lifetime in battery powered systems. Glossary of Terms MilliTesla (mT), Gauss Units of magnetic flux density: 1mT = 10 Gauss RoHS Restriction of Hazardous Substances Operating Point (BOP) Magnetic flux density applied on the branded side of the package which turns the output driver ON (VOUT = VDSon) Release Point (BRP) Magnetic flux density applied on the branded side of the package which turns the output driver OFF (VOUT = high)

CMOS High Sensitivity Micropower Hall Latch 3 V3.10 Nov 1, 2013 Pin Definitions and Descriptions SOT Pin № SIP Pin № Name Type Function 1 1 VDD Supply Supply Voltage Pin 2 3 OUT Output Open Drain Output Pin 3 2 GND Ground Ground Pin Internal Timing Circuit Absolute Maximum Ratings Parameter Symbol V alue Units Supply Voltage VDD 6 V Supply Current IDD 50 mA Output Voltage VOUT 28 V Output Current IOUT 50 mA Operating Temperature Range TA -40 to 150 °C Storage Temperature Range TS -50 to 160 °C ESD Sensitivity 4000 V Awake Taw:120 μs Sleep Tsl:70ms Time Current Isp Iaw Iavg Sample & Out- put Latched Period

CMOS High Sensitivity Micropower Hall Latch 4 V3.10 Nov 1, 2013 Operating Temperature Range Symbol Value Units Temperature Suffix “E” TA -40 to 85 °C Temperature Suffix “K” TA -40 to 125 °C Temperature Suffix “L” TA -40 to 150 °C Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute-maximum- rated conditions for ex- tended periods may affect device reliability. General Electrical Specifications DC Operating Parameters TA = 25°C, VDD= 2.75V Parameter Symbol Test Conditions Min Typ Max Units Supply Voltage VDD Operating 2.5 3 5.5 V Supply Current IDD Average 5 μA Output Current IOUT 1.0 mA Saturation Voltage VSAT IOUT=1mA 0.4 V Awake mode time TAW Operating 175 μS Sleep mode time TSL Operating 70 mS Magnetic Specifications DC Operating Parameters VDD = 2.5 to 5.5V (unless otherwise specified) Package Parameter Symbol Test Conditions Min Typ Max Units UA Operating Point BOP Ta=25°C Vdd=2.75V DC 5 30 60 G Release Point BRP -60 -30 -5 G Hysteresis BHYST 60 G SO Operating Point BOP Ta=25°C Vdd=2.75V DC -60 -30 -5 G Release Point BRP 5 30 60 G Hysteresis BHYST 60 G

CMOS High Sensitivity Micropower Hall Latch 5 V3.10 Nov 1, 2013 Output Behavior versus Magnetic Pole DC Operating Parameters TA = -40°C to 150°C, VDD = 2.5 to 5.5V (unless otherwise specified) Test Conditions (UA) Test Conditions (SO) OUT B < BRP B > BRP High B > BOP B < BOP Low The SOT-23 device is reversed from the UA package. The SOT-23 output transistor will be turned on(drops low) in the presence of a sufficiently strong North pole magnetic field applied to the marked face and turned off(hoists high) in the presence of a sufficiently strong South pole magnetic field. Unique Features CMOS Hall IC Technology The chopper stabilized amplifier uses switched capacitor techniques to eliminate the amplifier offset voltage, which, in bipolar devices, is a major source of temperature sensitive drift. CMOS makes this advanced technique possible. The CMOS chip is also much smaller than a bipolar chip, allowing very sophisticated circuitry to be placed in less space. The small chip size also contributes to lower physical stress and less power consumption. ESD Protection Human Body Model (HBM) tests according to: Mil. Std. 883F method 3015.7 Parameter Symbol Limit Values Unit Notes Min Max ESD Voltage VESD ±4 kV ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products.

CMOS High Sensitivity Micropower Hall Latch 6 V3.10 Nov 1, 2013

Package Information

4.0 ± 0.01 1.27 2.13 1.87 1.00 1.20 45° ± 1° 1.52 ± 0.1 3° ± 1° 0.75 ± 0.05 3.0 ± 0.01 0.44± 0.01 0.05 ± 0.01 1.6.± 0.1 0.84(Nom) 3° ± 1° 6° ± 1° 6° ± 1° 3° ± 1° 14 .5 ± 1 Active Area Depth: Sensor Location Notes: 1). Controlling dimension : mm ; 2). Leads must be free of flash and plating voids ; 3). Do not bend leads within 1 mm of lead to package interface ; 4). PINOUT: Pin 1 V DD Pin 2 GND Pin 3 Output 0.39± 0.01 0.38 ± 0.01 2.54

CMOS High Sensitivity Micropower Hall Latch 7 V3.10 Nov 1, 2013 Package 3-Pin SOT-23： 0.56 0.66 0.95 1.50 Chip Bottom View of SOT-23 Package 2.70 3.10 1.00 1.30 0.70 0.90 0.00 0.10 0.35 0.50 0.10 0.25 0.20 MIN 2.60 3.00 1.50 1.80 1.70 2.10 2 1 Top View Side View End View Notes: 1. PINOUT: Pin 1 V DD Pin 2 Output Pin 3 GND 2. All dimensions are in millimeters ;

CMOS High Sensitivity Micropower Hall Latch 8 V3.10 Nov 1, 2013 Package 3-Pin TSOT-23： 0.36 0.46 0.95 1.50 Chip Bottom View of TSOT-23 Package 2.82 3.02 0.70 0.90 0.70 0.80 0.00 0.10 0.35 0.50 0.08 0.20 0.20 Min 2.65 2.95 1.60 1.70 1.70 2.10 2 1 Top Side Vie End Notes 1). PINOUT: Pin 1 VDD Pin 2 Output Pin 3 GND 2). All dimensions are in millimeters;

CMOS High Sensitivity Micropower Hall Latch 9 V3.10 Nov 1, 2013

Ordering Information

Part No. Pb-free Temperature Code Package Code Packing SS2412ESOT YES -40°C to 85°C SOT-23 7-in. reel, 3000 pieces/ reel SS2412ESTT YES -40°C to 85°C TSOT-23 7-in. reel, 3000 pieces/ reel SS2412EUA YES -40°C to 85°C TO-92 Bulk, 1000 pieces/ bag SS2412KSOT YES -40°C to 125°C SOT-23 7-in. reel, 3000 pieces/ reel SS2412KSTT YES -40°C to 125°C TSOT-23 7-in. reel, 3000 pieces/ reel SS2412KUA YES -40°C to 125°C TO-92 Bulk, 1000 pieces/ bag SS2412LSOT YES -40°C to 150°C SOT-23 7-in. reel, 3000 pieces/ reel SS2412LSTT YES -40°C to 150°C TSOT-23 7-in. reel, 3000 pieces/ reel SS2412LUA YES -40°C to 150°C TO-92 Bulk, 1000 pieces/ bag