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CMOS High Se nsitivity Micropower Hall Latch 1 V3.10 Nov 1, 201 3 Packages Features and Benefits 3 pin SIP (suffix UA) 1. Operation down to 4.5V 2. Wide operating voltage range 3. High sensitivity for direct reed switch re- placement applications 4. Output switches with absolute value of North or South pole from magnet 5. Temperature compensation 6. Open-Collector pre-driver 7. 60V maximum withstand voltage 8. Reverse polarity protection 9. Package: TO-92S(SIP) Functional Block Diagram Application Examples 1. Brush-less DC Motor 2. Brush-less DC Fan 3. Revolution counting 4. Speed measurement General Description: The SS2015 Hall effect latch sensor IC is fabricated fr om mixed signal CMOS technology. It incorporates a d- vanced chopper-stabilization techniques to provide accurate and stable magnetic switch points. The circuit design provides an internally controlled clocking mechanism to cycle power to the Hall element and analog signal processing circuits. This serves to place the high current -consuming portions of the circuit into a “Sleep” mode. Periodically the device is “Awakened” by this internal logic and the magnetic flux from the Hall element is evaluated against the predefined thresholds. If the flux density is above or below the B OP/BRP thresh- olds then the output transistor is driven to change states accordingly. While in the “Sleep” cycle the output tran- sistor is latched in its previous state. The design has been optimized for service in applications requiring extended operating lifetime in battery powered systems. An internal bandgap regulator is used to provide temperature co m- pensated supply voltage for internal circuits and allows a wide operating supply range. The output tra nsistor of the SS2015 will be latched on (BOP) in the presence of a sufficiently strong South or North magnetic field facing the marked side of the package. The output will be latched off (BRP) in the absence of a magnetic field. 3 pin SOT23W (suffix SO)

CMOS High Se nsitivity Micropower Hall Latch 2 V3.10 Nov 1, 201 3 Typical Application Circuit SEC's pole-independent sensing technique allows for operation with either a north pole or south pole magnet orientation, enhancing the manufacturability of the device. The state -of-the-art technology provides the same output polarity for either pole face. It is strongly recommended that an external bypass be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chop- per-stabilization technique. This is especially true due to the relatively high impedance of battery supplies. Functional Block Diagrams Voltage Hall Plate Amp VDD GND Output

CMOS High Se nsitivity Micropower Hall Latch 3 V3.10 Nov 1, 201 3 Pin Definitions and Descriptions SIP Pin № Name Type Function

1 VDD Supply Supply Voltage pin

3 OUT Output Open Drain Output pin

2 GND Ground Ground pin

Parameter Symbol Value Units Supply Voltage (operating) VDD 24 V Reverse Voltage, -VDD -24 V Output Voltage VOUT 30 V Output Current IOUT 50 mA Operating Temperature Range TA -20 to 85 °C Storage Temperature Range TS -55 to 150 °C ESD Sensitivity - 4000 V Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DC Operating Parameters: TA = 25°C, VDD= 12V. Parameter Symbol Test Conditions Min Typ Max Units Operating Voltage VDD Operating 4.5 5 24 V Supply Current IDD Average 5 10 mA Saturation Voltage VSAT IOUT = 20mA, B>BOP 0.4 0.5 V Output Leakage IOFF B<BRP, VOUT = 20V 0.01 5 µA Output Rise Time tr RL = 1.1K O, CL = 20pf 0.3 1.5 µS Output Fall Time tf RL = 1.1K O, CL = 20pf 0.3 1.5 µS

CMOS High Se nsitivity Micropower Hall Latch 4 V3.10 Nov 1, 201 3 Magnetic Characteristics Operating Parameters: TA = 25°C, VDD =12V Parameter Symbol Min Type Max Units Operating Point BOP 5 70 Gs Release Point BRP -70 -5 Gs Hysteresis BHYST 80 Gs ESD Protection Human Body Model (HBM) tests according to: Mil. Std. 883F method 3015.7 Parameter Symbol Limit Values Unit Notes Min Max ESD Voltage VESD ±4 kV Performance Characteristics Unique Features CMOS Hall IC Technology The chopper stabilized amplifier uses switched capacitor techniques to eliminate the amplifier offset voltage, which, in bipolar devices, is a major source of temperature sensitive drift. CMOS makes this advanced technique possible. The CMOS chip is also much smaller than a bipolar chip, allowing very sophisticated circuitry to be placed in less space. The small chip size also contributes to lower physical stress and less power consumption. Installation Comments Consider temperature coefficients of Hall IC and magnetic, as well as air gap and life time variations. Observe temperature limits during wave soldering. Typical IR solder-reflow profile: – No Rapid Heating and Cooling. – Recommended Preheating for max. 2minutes at 150°C – Recommended Reflowing for max. 5seconds at 240°C

CMOS High Se nsitivity Micropower Hall Latch 5 V3.10 Nov 1, 201 3 ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products.

CMOS High Se nsitivity Micropower Hall Latch 6 V3.10 Nov 1, 201 3

Package Information

Package UA, 3-Pin IP:

Ordering Information

Part No. Pb-free Temperature Code Package Code Packing SS2015EUA YES -40°C to 85°C TO-92 Bulk, 1000 pieces/bag SS2015KUA YES -40°C to 125°C TO-92 Bulk, 1000 pieces/bag SS2015LUA YES -40°C to 150°C TO-92 Bulk, 1000 pieces/bag 4.0 ± 0.01 1.27 2.13 1.87 1.00 1.20 45° ± 1° 1.52 ± 0.1 3° ± 1° 0.75 ± 0.05 3.0 ± 0.01 0.44± 0.01 0.05 ± 0.05 1.6.± 0.1 0.84(Nom) 3° ± 1° 6° ± 1° 6° ± 1° 3° ± 1° 14 .5 ± 1 Active Area Depth: Sensor Location Notes: 1). Controlling dimension : mm ; 2). Leads must be free of flash and plating voids ; 3). Do not bend leads within 1 mm of lead to package interface ; 4). PINOUT: Pin 1 V DD Pin 2 GND Pin 3 Output 0.39± 0.01 0.38 ± 0.01 2.54