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Siemens Power Hybrid for SMPS SPH 4690 Preliminary Data Bipolar IC Features or @ Fold-back characteristics provides overload protection for ° external components Gee @ Burst operation under secondary short-circuit condition & implemented iS @ Protection against open or a short of the control loop v © Switch-offif line voltage is too low (undervoltage switch-off) @ Line voltage depending compensation of foldback point veo osoas © Soft-start for quit start-up without noise generated by the | P-DIP-18 transformer er © Chip-over temperature protection implemented (thermal shutdown) © On-chip ringing suppression circuit against parasitic oscillations of the transformer Power MOSFET @ Vos = 600 V @ Rosen = 2.02 © Repetitive Avalanche Type [Ordering Code | Package SPH 4690 Q67000-A5068_P-DIP-18-1 (11-P) The Siemens Power Hybrid SPH 4690 contains the SMPS IC TDA 4605-3 as well as the SIEMENS. POWER MOSFET in a P-DIP-18 package. The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and protection functions in free running flyback converters. Because of the fact that a wide load range is achieved, this IC is applicable for consumer as well as industrial power supplies. 91 10.92

The serial circuit and primary winding of the flyback transformer are connected in series to the input voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the switch-off period the energy is fed to the load via the secondary winding. By varying the switch-on time of the power transistor, the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent of load variations. The required control information is taken from the input voltage during the switch-on period of the transistor and from a regulation winding during the switch off period. A new cycle will start if the transformer has transferred the stored energy completely into the load. In the different load ranges the switched-mode power supply (SMPS) behaves as follows: No-load operation: The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be a little bit higher or lower than the nominal value depending of the design of the transformer and the resistor of the control voltage divider. Nominal operation: The switching frequency is reduced with increasing load and decreasing AC-voltage. The output voltage is only dependent on the load Overload point: Maximal output power is available at this point of the output characteristic. Overload: The energy transferred per operation cycle is limited at the top. Therefore the output voltages declines by secondary overloading, Pin Configuration Control IC — — Pint | Regulating voltage Pin2 Primary current simulation Pin3 Primary voltage detector Pin4 Ground Pin 15 Push-pull output Pin 16 Supply voltage Pin 17 Soft-Start Pin 18 Zero detector Pin Configuration Power MOSFET 7 Pin 5, 12 N.C. Pin 6-11 MOSFET Drain Pin 13 MOSFET Source Pin 14 MOSFET Gate Semiconductor Group 92

Pin Definitions and Functions Pin No. Function 1 Information Input Concerning Secondary Voltage. By comparing the regulating voltage - obtained from the regulating winding of the transformer - with the internal reference voltage, the output impulse width on pin 5 is adapted to the load of the secondary side (normal, overload, short circuit, no load). 2 Information Input Regarding the Primary Current. The primary current rise in the primary winding is simulated at pin 2 as a voltage rise by means of external RC-element. When a value is reached that's derived from the regulating voltage at pin 1, the output impulse at pin 5 is terminated. The RC-element serves to set the maximum power at the overload point set. 3 Input for Primary Voltage Monitor. When the line voltage is too low the IC is switched off by comparing V, with an internal reference. Voltage at pin 3 is used for overload point compensation. Overload point compensation will work 7 times the under voltage limit set.

4 Ground

5 Not connected

12 Not connected

13 MOSFET Source

14 MOSFET Gate

15 Output: Push-pull output provides + 1 A for rapid charge and discharge of the

gate capacitance of the power MOS transistor. 16 ‘Supply Voltage Input. From it a stable internal reference voltage Vac and the switching thresholds Vex, Vee. Vemax 2Nd Ve ma for the supply voltage detector is formed. If Vs > Voe then Vaer is switched on and switched off when V5 < Vea. In addition the logic is only enabled for Vg min > Ve 7 Input for Soft-Start. Start up will begin with short pulses by connecting a capacitor from pin 7 to ground. 18 Input for the Oscillation Feedback. After starting oscillation, every zero transit of the feedback voltage (falling edge) triggers an output impulse at pin 5. The trigger threshold is at + 50 mV typical. Semiconductor Group 93

Reference Supply Bo! Primary output Voltage jotage Current stoge and typ. 3V fonitor Reproducer Current 6-11 Limit ? © Starting

4 Pulse

The application circuit shows a flyback converter for video recorders with an output power rating of 70 W. The circuit is designed as a wide-range power supply for AC-line voltage of 180 to 264 V. The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C;. The NTC limits the rush-in current. In the period before the switch-on threshold is reached the IC is supplied via resistor R, ; during the start-up phase it uses the energy stored in C2, under steady state conditions the IC receives its supply voltage from transformer winding , via diode D1. The switching transistor T1 is a BUZ 90. The parallel connected capacitor C; and the inductance of primary winding n, determine the system resonance frequency. The R-C,-D2 circuitry limits overshoot peaks, and R,; protects the gate of T1 against static charges. During the conductive phase of the power transistor T1 the current rise in the primary winding depends on the winding inductance and the mains voltage. The network consisting of R4-C; is used to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage is fed into pin 2 of the IC. The RC-time constant given by R,-C; must be designed that way that driving the transistor core into saturation is avoided. The ratio of the voltage divider Rio/R,, is fixing a voltage level threshold. Below this threshold the switching power supply shall stop operation because of the low mains voltage. The control voltage present at pin 3 also determines the correction current for the foldback point. This current added to the current flowing through RX, and represents an additional charge to C; in order to reduce the turn- ‘on phase of T1. This is done to stabilize the fold-back point even under higher main voltages. Regulation of the switched-mode power supply is via pin 1.The control voltage of winding n1 during the off period of T1 is rectified by D3, smoothed by C; and stepped down at an adjustable ratio by R;, Re and R;. The R,-C; network suppresses parasitic overshoots (transformer oscillation). The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage applied across the control winding, and hence the output voltages, are at the desired level. When the transformer has supplied its energy to the load, the control voltage passes through zero. The IC detects the zero crossing via series resistors Re connected to pin 18. But zero crossings are also produced by transformer oscillation after T1 has turned off if outputs is short circuited. Therefore the IC ignores zero crossings occurring within a specified period of time after T1 turn-off. The capacitor Csconnected to pin 17 causes the power supply to be started with shorter pulses to keep the operating frequency outside the audible range during start-up. On the secondary side, three output voltages are produced across winding nto ns rectified by D4 to D6 and smoothed by C,to C;;. Resistor R;2 is used as a bleeder resistor. Fusable resistors Ry, and Ry, protect the rectifiers against short circuits in the output circuits, which are designed to supply only small loads. Semiconductor Group 95

Page 4 shows the block diagram of the IC, page 18 shows the most important waveforms of the SMPS in operation. Pint The regulating voltage forwarded to this pin is compared with a stable internal reference voltage Va . in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If the control voltage is rather small at pin 1 an additional current is added by means of current source which is controlled according the level at pin 7. This additional current is virtually reducing the control voltage present at pin 1. Pin2 A voltage proportional to the drain current of the switching transistor is generated there by the external RC-combination in conjunction with the primary current transducer. The output on this transducer is controlled by the logic and referenced to the internal stable voltage Vas. If the voltage V, exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator and consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage are the output for the start impulse generator with the stable reference potential Vs; and the supply voltage motor. Pin3 The down divide primary voltage applied there stabilized the overload point. In addition the logic is disabled in the event of low voltage by comparison with the internal stable voltage V, in the primary voltage monitor block. Pin4 Ground Pin 15 In the output stage the output signals produced by the logic are shifted to a level suitable for MOS- power transistors. Pin 16 From the supply voltage V, are derived a stable internal references Vrer and the switching threshold Vea» Vee Vemax Nd Vs min for the Supply voltage monitor. All references values (Va, oa. Vex) are derived from Vacr. If Vs > Vve, the Vaer is switched on and switched off when Vs < Ve, . In addition, the logic is released only for Vo min < V6 < Ve max + Pint7 The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is connected to ground by a capacitor. Semiconductor Group 96

The zero detector controlling the logic block recognizes the transformer being discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an internal circuit inhibits the zero detector for a finite time 1. after the end of each pulse. Start-Up Behaviour The start-up behaviour of the application circuit per page 16 is represented on page 18 for a line voltage barely above the lower acceptable limit time fa the following voltages built up: = Vs corresponding to the half-wave charge current over R, = Vo tO Vo max (typically 6.6 V) - Vs to the value determined by the divider Ryo/Ry1 - The current drawn by the IC in this case is less than 1.6 mA. If Vs reaches the threshold Vs < (time point t1), the IC switches on the internal reference voltage. The current draw max. rises to 12 mA. The primary current-voltage reproducer regulates V, down to Veg and the starting impulse generator generates the starting impulses from time point fs to 16. The feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short- circuit event, i.e. V; = 0. Hence the IC starts up with “short circuit impulses" to assume a width depending on the regulating voltage feedback (the IC operates in the overload range). The IC operates at the overload point. Thereafter the peak values of V, decrease rapidly, as the starting attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V further decreases to Vs. The IC switches off; Vs can rise again (time point 1.) and a new start-up attempt begins at time point t1. If the rectified alternating line voltage (primary voltage) collapses during load, V, can fall below V3 ,, as is happening at time point r, (switch-on attempt when voltage is too low). The primary voltage monitor then clamps V3 to V3 until the IC switches off (Vs < Vs 4). Then a new start-up attempt begins at time point r, Semiconductor Group 97

Regulation, Overload and No-Load Behaviour When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V; = H). The peak voltage value at pin 2 increases up to Vos max. If the secondary load is further increased, the overload amplifier begins to regulate the pulse width downward. This point is referred to as the overload point of the power supply. As the IC supply voltage V;is directly proportional to the secondary voltage, it goes down in accordance with the overload regulation behaviour. If Vs falls below the value Vo mo. the IC goes into burst operation. As the time constant of the half-wave charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back to the pulse width f,... This pulse width must remain possible, in order to permit the IC to start-up without problems from the virtual short circuit, which every switching on with V, = 0 represents. If the secondary side is unloaded, the loading impulses (V; = H) become shorter. The frequency increases up to the resonance frequency of the system. If the load is further reduced, the secondary voltages and Vg increase. When V5 = Vs max. the logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe under no-load conditions. Behaviour when Temperature Exceeds Limit An integrated temperature protection disables the logic when the chip temperature becomes too high. The IC automatically interrogates the temperature and starts as soon as the temperature decreases to permissible values. Semiconductor Group 98

Ty =-20 to 85°C Parameter | Symbol Remarks _ iin. typ. | TDA 4605-3 Voltage pint Vv, |-03 3 iV pin2 V, |-03 Vv pin3 Vs (-03 v | pin 15 Vis (-03 Ve V pin 16 Ve ‘03 20. |V__| Supply voltage pin 17 Vay (-03 | v Current pint I 3. [mA pin2 lb H 3 (mA | pin3 L, { 3 mA pina I (15 i A tS 50 ys; vs 0.1 pin 15 hs (-05 418 A ‘gs 50us;vs0.4 pin 16 he | 105 A (4<50us;v<0.1 pin 17 Ip 13 mA pin 18 Ie -5 3 mA Junction temperature 1, 125°C Storage temperature Tag -40 | 125 °C | Power MOSFET Pulsed drain current Mose | |44 [A |T,=25°C Gate source voltage | Ves +20 Vv - Power dissipation Pp 1 wo | T,=25'C Single pulse | Eas 320 mo | ip=4.4A; Avalanche Energy i Voo= 50 V ' Rog = 25.5 \\ | L=30mH Repetitive avalanche Energy | Ean [a |__| limited by 7, Avalanche current lan | "A | limited by T,nax repet. or non-repet. | i ‘Semiconductor Group 99

Absolute Maximum Ratings (cont'd) Operating Range Parameter Limit Values | Unit | Remarks TDA 4605-3 Supply voltage 155 |V_ [IC "on" Ambient temperature T, 85 C Heat resistance Junction to environment | Rove 100 | KW Junction to package Rss 70 KW _ measured at pin 4 Semiconductor Group 400

Ty= 25°C; Ve= 10V Parameter Symbol Limit Values | Unit |Test Condition | Test min. | typ. | max. Circuit TDA 4605-3 Start -Up Hysteresis Start-up current Ieee 06 [08 |mA | Vie= Ver it Voltage Clamp (V_= 10 V, IC switch-off) Atpin2 (Ve<Viee) [Vana [56 [66 [8 |V |h=1mA 1 Control Range Voltage gain of the Vp Va = (Vas—Van)/dV, | 2 control circuit in the f= 1 kHz control range Primary Current Simulation Voltage Overload Range and Short Circuit Operation Peak value in the range | V2.5 29 3.0 {3.1 Vv H YsVa-10mv (2 of secondary overload { | | Peak value in the range | Vax V1Y=0 l2 of secondary short | | circuit operation | | Foldback Point Correction Foldback point -h 300 |s500 [650 [pA |W=37V 1 correction current Semiconductor Group 401

Characteristics (cont'd) Tn = 25°C; Ve=10V Parameter | Symbol Limit Values Unit Test Condition Test | min. [typ. max. | _Cireuit Generally Valid Data (V,, = 10 V) Voltage of the Zero Transition Detector Positive clamping | Vee | [o7s Vv lig=tmA [2 Negative clamping | Vian 1-02 Vv |hg=1mA 2 Ne | { — h : Threshold value Vas [40 50 mV 2 Suppression of an 30 |34 38 [us | 2 transformer ringing i Input current -hs 0 4 WA | Vig=0 | Push-Pull Output Stage Saturation voltages: \\ Pin 15 sourcing Veato 45 (20 |V | fg=-0.1A 4 Pin 15 sinking Vesat v | 1.0 1.2 Voi hs=+01A 4 Pin 15 sinking Veary 1418 |V hg=40.5A 1 Output Slew Rate Rising edge + dVisar "70 ‘Vins |— 12 Falling edge = ddr | | 100 | Vins | - 2 Reduction of Control Voltage Current reduce the -h [ 50 [WA |Vy=t4V control voltage : " Semiconductor Group 102

Characteristics (cont'd) T, = 25°C; Ve=10V Parameter ~ [Symbol | Limit Values | Unit |Test Condition | Test min. |typ. | max. Circuit Power MOSFET Static Ratings Drain source breakdown | Vaross | 600 Vi | Veg = 0V; voltage Jy = 0.25 MA Gate threshold voltage |Vosmn 21 (3.0 [40 |V | Ves=Vosi controlled by | I= 1mA TDA 4605-3 Zero gate voltage drain | Joss 0.4 10 | WA | 1=25°C | current Vos = 600 V | Ves = 0V | Zero gate voltage drain | Iss. HA | T= 125°C current Vos = 600 V Vos = 0V — = 9S} Drain source on state | Rosen Q | i resistance ; | _ Dynamic Ratings Forward Bs 25 |38 | S |Vos= j transconductance | 2X bX Rosionmax | b=28A Input capacitance Cus | 780 PF Vos = 0V | Vos = 25 V f= 1MHz Output capacitance Coss 170 |pF | Ves=0V | Vos = 25 V f=1MHz Reverse transfer Gs 70 pF | Vos =0V capacitance Vos = 25 V f=1 MHz Turn-on delay time faon 30 [ns | Vic = 300 i Vos = 10 V b=25A Ros = 50.2 Semiconductor Group 104

Characteristics (cont'd) Th = 25°C; Va=10V Parameter Symbol Limit Values [Unit [Test Condition | Test min. |typ. | max. i { { Circuit Rise time & 50 75 ins | Voc = 300 V ] Veg = 10 V | b=25A ' ! Res = 502 Turn-off delay time bow 120/150 |ns | Voc=300V Vos = 10 V | b=25A 1 Ros = 50.2 Fall time 4 70 90 ns Voc = 300 V Veg = 10V | b=25A ! } Ros = 50. Reverse Diode Continuous reverse k 0.55 | A drain current i Pulsed reverse drain | ky : 44 A | current { Diode forward Veo 12 |V | Ves=0V k=2.8A Reverse recovery time | ty 350 | ns | Va=100V | \\ k= 28A ' i it di/dt = 100 A/us Reverse recovery "0, 25 uC | Va=100V charge | j h=28A | | | dk/dr=100 Aus | Semiconductor Group 105

1 18, @) ® Yo (f) 2 7 SPH 4690 “oO 3 is GK 2) 4 15. 2) LG se=hen Ms ov Yoorw = Yas ucsosasa Test Circuit 1 Yeo [Jor00 [eo [is 1 wi oy Tre pete | | 7 chur SPH 4690 is 10nF 3.3nF []5u0 4 15 Test Circuit 2 Semiconductor Group 106

= Fe = 2 3 s 5 Fa 2 § + + + coy s es cS | je 7 ete > [EF eLE ons ee Coe € es o¢ . © ® os sy i Fs 2 Fa ave sag 24 > ‘5 4 7 388 oe S “fe SS 3 UE ene o| — ~[]s z of = es eG “J es i ee rt a8 4 as ll = de ( lls ee {—} =[E So KS Bee 33 2 $354 6 =8 4 = TasscEs Application Circuit Semiconductor Group 107

—-t Yew ¥, Stort Voy = ‘ \\ XN XN Vag Stop Mise Mes fain mee | 1 1 { to to4 ‘ — ° 4~ Foldback Point ! 4 tT 1 a it i ot veoosses Semiconductor Group 108

yj AA. / ’ \\/ / f ! Yaeenin Yew 0 Yon { || fj Vi tl ll | (hed | I Yep ST tty] t [lh t hh h —e=f hh Isto — Ly { t | =—_- ——— = —_) is , —~ —-! vueze3e70 Semiconductor Group 109

Start-Up Hysteresis, Semiconductor Group 110

y Ie | | 9 10 «20 | 30 40 Sts ty rs | Vien et faz ta —— Foldback Point Vax Vag toy —-! Ys * 4 ths - Mismoe~ “ismin Nsmex. —— a i NN hs Msmax~ Mismin Vuod t Yismin t —~t epose7i Operation in Test Circuit 2 Semiconductor Group m1

Start-Up Current as a Function of the Overload Point Correction as a Function of Ambient Temperature the Voltage at Pin 3 1.0 peer 750 ye003873 uA mA Neco h t 0.75 t 562.3 05 375 0.25 187.5 0 0 “2 0 2 50 75 C100 0 2 4 6 Vv 8 — —% Semiconductor Group 112

Product Information

SPH4690 specifications and overview.

Summary

SIEMENS POWER HYBRID FOR SMPS

Description

SIEMENS POWER HYBRID FOR SMPS

Source title SPH4690 Datasheet(PDF) - Siemens Semiconductor Group

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