SPD50P03LG_12 INFINEON | Alldatasheet
Document overview
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- PDF pages: 9
Technical content
Features
- P-Channel
- Enhancement mode
- Logic level
- 175°C operating temperature
- Avalanche rated
- d v t rated
- High current rating
- Pb-free lead-plating, RoHS compliant Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Unit Continuous drain current I D T C=25 °C1) A T C=100 °C1) Pulsed drain current I D,pulse T C=25 °C Avalanche energy, single pulse E AS I D=-50 A, R GS=25 Ω mJ Reverse diode d v t d v t I D=-50 A, V DS=24 V, d i t =-200 A/µs, T j,max=175 °C kV/µs Gate source voltage V GS V Power dissipation P tot T C=25 °C W Operating and storage temperature T j, T stg °C ESD class HBM Soldering temperature IEC climatic category; DIN IEC 68-1 Value 256 -200 -50 -50 150 55/175/56 -55…+175 ±20 260 V DS -30 V R DS(on),max 7 m Ω I D -50 A Product Summary PG-TO252-5 Type Package Marking Lead Free PG-TO252-5 50P03L YesSPD50P03L G Rev. 1.9 page 1 2012-09-13 Packing Non dry Tape and reel information 1000 pcs / reel
Parameter Symbol Conditions Unit min. typ. max. Thermal characteristics Thermal resistance, junction - case R thJC - - 1 K/W R thJA minimal footprint - - 75 6 cm2 cooling area2) -- 5 0 Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=-250 µA -30 - - V Gate threshold voltage V GS(th) V DS= V GS, Zero gate voltage drain current I DSS V DS=-30 V, V GS=0 V, V DS=-30 V, V GS=0 V, T j=175 °C - -10 -100 Gate-source leakage current I GSS V GS=-20 V, V DS=0 V - -10 -100 nA Drain-source on-state resistance R DS(on) V GS=-4.5 V, I D=-30 A - 8.5 12.5 m Ω Drain-source on-state resistance R DS(on) V GS=-10 V, I D=-50 A - 5.7 7.0 Transconductance g fs | V DS|>2| I D| R DS(on)max, I D=-50 A 47 94 - S 1) Current is limited by bondwire; with an R thJC=1 K/W the chip is able to carry 123 A. Values 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Thermal resistance, junction - ambient Rev. 1.9 page 2 2012-09-13
Parameter Symbol Conditions Unit min. typ. max. Dynamic characteristics Input capacitance C iss - 4590 6880 pF Output capacitance C oss - 1220 1830 Reverse transfer capacitance C rss - 1000 1500 Turn-on delay time t d(on) - 14.8 22 ns Rise time t r - 21.7 32 Turn-off delay time t d(off) - 139 208 Fall time t f - 104 156 Gate Charge Characteristics3) Gate to source charge Q gs - -14 -19 nC Gate to drain charge Q gd - -35 -53 Gate charge total Q g VDD=-24 V, ID=-50 A, VGS=0 to -10 V - -95 -126 Gate plateau voltage V plateau VDD=-24 V, ID=-50 A - -3.0 - V Reverse Diode Diode continous forward current I S - - -50 A Diode pulse current I S,pulse - - -200 Diode forward voltage V SD V GS=0 V, I F=50 A, Reverse recovery time t rr V R=-15 V, I F=| I S|, d i F/d t =100 A/µs -3 8 4 7 n s Reverse recovery charge Q rr -4 6 5 7 n C 3) See figure 16 for gate charge parameter definition T C=25 °C Values V GS=0 V, V DS=-25 V, f =1 MHz V DD=-15 V, V GS=-10 V, I D=-1 A, R G=6 Ω V DD=-24 V, I D=-50 A Rev. 1.9 page 3 2012-09-13
1 Power dissipation 2 Drain current
P tot=f( T C) I D=f( T C); | V GS| ≥ 10 V 3 Safe operating area 4 Max. transient thermal impedance I D=f( V DS); T C=25 °C; D =0 Z thJC=f( t p) parameter: t p parameter: D = t p/ T 1 µs 10 µs 100 µs 1 ms 10 ms DC 10-1 100 101 102 100 101 102 103 -V DS [V] -I D [A] limited by on-state resistance single pulse 0.01 0.02 0.05 0.1 0.2 0.5 10-110-210-310-410-5 101 100 10-1 10-2 t p [s] Z thJC [K/W] 100 120 140 160 0 40 80 120 160 200 T C [°C] P tot [W] 0 40 80 120 160 200 T C [°C] -I D [A] Rev. 1.9 page 4 2012-09-13
5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f( V DS); T j=25 °C R DS(on)=f( I D); T j=25 °C parameter: V GS parameter: V GS 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f( V GS); | V DS|>2| I D| R DS(on)max g fs=f( I D); T j=25 °C parameter: T j -4.5 V -5.5 V V 6- -6.5 V -7 V -10 V 0 40 80 120 160 200 -I D [A] R DS(on) [m Ω ] C °25 C °175 01234 -V GS [V] -I D [A] 100 02 0 4 0 6 0 -I D [A] g fs [S] -3 V -5 V -4 V -2.5 V -4.5 V -3.5 V -10 V 100 120 140 160 180 200 02468 1 0 -V DS [V] -I D [A] Rev. 1.9 page 5 2012-09-13
9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f( T j); I D=-50 A; V GS=-10 V V GS(th)=f( T j); V GS= V DS; I D=-250 µ A 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f( V DS); V GS=0 V; f =1 MHz I F=f( V SD) parameter: T j typ. 98 % -60 -20 20 60 100 140 180 T j [°C] R DS(on) [m Ω ] Ciss Coss Crss 104 103 102 100 1000 10000 0 5 10 15 20 25 -V DS [V] C [pF] typ. 98%. 0.5 1.5 2.5 -60 -20 20 60 100 140 180 T j [°C] -V GS(th) [V] 25 °C, typ 175 °C, typ 25 °C, 98% 175 °C, 98% 100 1000 0 0.5 1 1.5 2 2.5 -V SD [V] I F [A] Rev. 1.9 page 6 2012-09-13
13 Avalanche characteristics 14 Typ. gate charge I AS=f( t AV); R GS=25 Ω V GS=f( Q gate); I D=-50 A pulsed parameter: T j(start) parameter: V DD
15 Drain-source breakdown voltage 16 Gate charge waveforms
V BR(DSS)=f( T j); I D=-250 µ A V 6- V 15- V 24- 0 2 04 06 08 0 1 0 0 1 2 0 -Q gate [nC] -V GS [V] -60 -20 20 60 100 140 180 T j [°C] -V BR(DSS) [V] V GS Q gate V gs(t h ) Q g(th) Q gs Q gd Q sw Q g C °25 C °100 C °150 100 1 10 100 1000 t AV [µs] -I AV [A] Rev. 1.9 page 7 2012-09-13
-TO252-5: Outline Footprint Packaging Tape Dimensions in mm Rev. 1.9 page 8 2012-09-13
Rev. 1.9 page 9 2012-09-13 SPD50P03LSPD50P03L G Published by Infineon Technologies AG
81726 Munich, Germany
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