SP9841 SIPEX | Alldatasheet
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I Replaces 8 Potentiometers and 8 Op Amps I Operates from Single +5V Supply I 6.3 MHz 2-Quadrant Multiplying Gain Band- width I No Signal Inversion I Eight Reference Inputs, Eight Voltage Outputs (SP9841) I Four Reference Inputs, Eight Voltage Outputs (SP9842) I 3-Wire Serial Input I 0.8MHz Data Update Rate I +3.25 Volt Output Swing I Midscale Preset I Low 65 mW Power Dissipation (8mW/DAC) DESCRIPTION… The SP9841 and SP9842 are general purpose octal DACs in a single package. The SP9841 features eight individual reference inputs, while the SP9842 provides four pair of voltage reference inputs. Both parts feature 6.3MHz bandwidth, two–quadrant multiplication, and a three–wire serial interface. Other features include midscale preset, no signal inversion and low power dissipation from a single +5V supply. Devices are available in commercial and industrial temperature ranges. DAC A 8 x 8 DAC REGISTER SERIAL REGISTER LOGIC Decoded Address Data Clock Serial Data Input Serial Data Output Preset Load VREF Low SP9842 DAC B VINA/B VOUTB VOUTA DAC G DAC H VING/H VOUTH VOUTG SP9842 Block Diagram DAC A DAC H 8 x 8 DAC REGISTER SERIAL REGISTER LOGIC Decoded Address Data Clock Serial Data Input Serial Data Output Preset Load VINA VOUTA VINH VOUTH VREF Low SP9841 SP9841 Block Diagram SP9841/42 8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC
These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Operating Temperature Range Thermal Resistance ∅JA SPECIFICATIONS (VDD = +5V, All VINX= +1.625V, VREFL = 0V, TA = 25° C for commercial–grade parts; TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to all DAC's unless noted otherwise.) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS SIGNAL INPUTS Input Voltage Range 1.625 V VREFL = GND, VDD = 4.75V Input Resistance D = 55H; Code Dependent SP9841 kΩ SP9842 2.5 kΩ Input Capacitance Code Dependent SP9841 pF SP9842 pF VREFL Resistance 0.375 0.75 kΩ All D = ABH; Code Dependent VREFL Capacitance 190 250 pF Code Dependent DIGITAL INPUTS Logic High 2.4 V Logic Low 0.8 V Input Current ±10 µA Input Capacitance pF Input Coding Binary STATIC ACCURACY Resolution Bits Integral Nonlinearity ±0.25 ±1.0 LSB Note 1 Differential Nonlinearity ±0.2 ±1.0 LSB Note 1 Half-Scale Output Voltage 1.600 1.625 1.650 V PR = LOW, Sets D = 80H Zero-Scale Output Voltage 100 mV D = 00H Output Voltage Drift µV/°C PR = LOW, Sets D = 80H DYNAMIC PERFORMANCE Multiplying Gain Bandwidth 6.3 MHz VINX = 100 mV p-p+ 1.0V dc Slew Rate Measured 10% to 90% Positive 3.0 7.9 V/µs VOUTX = 100mV to +3.1V Negative –3.0 –8.3 V/µs VOUTX = +3.1V to 100mV Total Harmonic Distortion 0.005 VINX = 0.8VDC + 1.4V p-p D= FFH; 1kHz, fLP = 80 kHz Output Settling Time 0.7 µs ±1 LSB Error Band, 8H to 255H Crosstalk dB Note 2 Digital Feedthrough nVs VREFL = +1.625V, D = 0 to FFH Wideband Noise 42.5 µV rms VOUT = 3.25V; 400Hz to 80kHz CAUTION: While all input and output pins have inter- nal protection networks, these parts should be considered ESD (ElectroStatic Dis- charge) sensitive devices. Permanent dam- age may occur on unconnected devices sub- ject to high energy electrostatic fields. Un- used devices must be stored in conductive foam or shunts. Personnel should be prop- erly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are re- moved.
SPECIFICATIONS (continued) (VDD = +5V, All VINX= +1.625V, VREFL = 0V, TA = 25° C for commercial–grade parts; TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to all DAC's unless noted otherwise.) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS DYNAMIC PERFORMANCE SINAD dB VINX = 0.8VDC + 1.4V p-p D= FFH; 1kHz, fLP = 80 kHz Digital Crosstalk nVs SP9842 only; measured between adjacent channels of same pair; D = 7FH to 80H DAC OUTPUTS Voltage Range VDD–1.5 V RL = 5kΩ; VDD = 4.75V Output Current ±10 ±15 mA ∆VOUT < 10mV, VINX=1.625V, PR = LOW Capacitive Load 47,000 pF No Oscillation DIGITAL OUTPUT Logic High 3.5 V IOH = -0.4mA Logic Low 0.4 V IOL = 1.6mA POWER REQUIREMENTS Power Supply Range 4.75 5.00 5.25 V To rated specifications Positive Supply Current mA PR = LOW Power Dissipation mW ENVIRONMENTAL AND MECHANICAL Operating Temperature Range Commercial +70 Industrial –40 +85 Storage Temperature Range –65 +150 Package SP9841N 24–pin Plastic DIP SP9841S 24–pin SOIC SP9842S 20–pin SOIC Note 3 Notes: The op amp limits the linearity for VOUT ≤ 100mV. When VREFL is driven above ground such that the output voltage remains above 100mV, then the linearity specifications apply to all codes. For VREFL = GND, VIN = 1.5V, codes 0 through 7 are not included in differential or integral linearity tests. Integral and differential linearity are computed with respect to the best fit straight line through codes 8 through 255. SP9841 is measured between adjacent channels, f = 100kHz; SP9842 is measured between adjacent pairs, f = 100kHz. For plastic DIP packaging of SP9842, please consult factory.
Plot 1. Integral Linearity Error versus Code. Plot 2. Differential Non–linearity Error versus Code. Plot 3. Integral Linearity Matching; VOUT A through VOUT D.
Plot 4. Integral Linearity Matching; VOUT E through VOUT H. Plot 5. THD versus Frequency. Plot 6. PSRR versus Frequency.
Plot 8. Full Scale Pulse Response. Plot 7. Small Signal Gain versus Frequency. VDD = 5V VIN = 0.05V to 1.55V VOUT = 0.1V to 3.1V Plot 9. Positive Full Scale Settling. VDD = 5V VIN = 0.05V to 1.55V VOUT = 0.1V to 3.1V
Plot 10. Negative Full Scale Settling. Plot 11. VIN(X) Current versus Code. VDD = 5V VIN = 0.05V to 1.55V VOUT = 0.1V to 3.1V Plot 12. IREFL Current Input Current versus Code.
Plot 13. Typical Midscale Output versus Temperature. Plot 14. Supply Current versus Temperature. Plot 15. Output Short Circuit Current versus VOUT(X).
Plot 16. Sink Current at Zero Scale. Plot 17. Typical VOUTmax versus VDD. Plot 18. Typical VOUT min versus VDD versus ISINK.
Plot 20. Integral Error versus Code versus VDD; VIN(X) = 0.6V. Plot 19. Integral Error versus Code versus VDD; VIN(X) = 0.5V.
Plot 21. Pulse Response — a) CLOAD = 470pF, RLOAD = 10MOhm; b) CLOAD = 470pF, RLOAD = 1kOhm; c) 50Ohms in series with CLOAD = 470pF; d) RLOAD = 1kOhm, 50Ohms in series with CLOAD = 470pF.
Plot 22. Pulse Response — a) CLOAD = 4,700pF; b) CLOAD = 4,700pF, RLOAD = 1kOhm; c) 30 Ohms in series with CLOAD = 4,700pF; d) RLOAD = 1kOhm, 30Ohms in series with CLOAD = 4,700pF.
Plot 23. Pulse Response — a) CLOAD = 47,000pF; b) CLOAD = 47,000pF, RLOAD = 1kOhm; c) 15 Ohms in series with CLOAD = 47,000pF; d) RLOAD = 1kOhm, 15 Ohms in series with CLOAD = 47,000pF.
Plot 24. Pulse Response — a) CLOAD = 0.47µF; b) CLOAD = 0.47µF, RLOAD = 1kOhm; c) 8.2 Ohms in series with CLOAD = 0.47µF; d) RLOAD = 1kOhm, 8.2 Ohms in series with CLOAD = 0.47µF.
24 VOUTD
23 VINC
22 VIND
21 VDD
20 SDI
19 GND
18 SDO
17 CLOCK
16 LOADH
15 VINH
14 VING
13 VOUTH
20 VOUTD
19 VINC/D
18 VDD
17 SDI
16 GND
15 SDO
14 CLOCK
13 LOADH
12 VING/H
11 VOUTH
Pin 18 — SDO — Serial Data Output; active totem– pole output. Pin 19 — GND — Ground. Pin 20 — SDI — Serial Data Input. Pin 21 — VDD — Positive 5V Power Supply. Pin 22 — VIND — DAC D Reference Voltage Input. Pin 23 — VINC — DAC C Reference Voltage Input. Pin 24 — VOUTD — DAC D Voltage Output. SP9842 PINOUT Pin 1 — VOUTC — DAC C Voltage Output. Pin 2 — VOUTB — DAC B Voltage Output. Pin 3 — VOUTA — DAC A Voltage Output. Pin 4 — VINA/B — DAC A and B Reference Voltage Input. Pin 5 — VREFL — DAC Reference Voltage Input Low, common to all DACs. Pin 6 — PRESETL — Preset Input; active low; all DAC registers forced to 80H. Pin 7 — VINE/F — DAC E and F Reference Voltage Input. Pin 8 — VOUTE — DAC E Voltage Output. Pin 9 — VOUTF — DAC F Voltage Output. SP9841 PINOUT Pin 1 — VOUTC — DAC C Voltage Output. Pin 2 — VOUTB — DAC B Voltage Output. Pin 3 — VOUTA — DAC A Voltage Output. Pin 4 — VINB — DAC B Reference Voltage Input. Pin 5 — VINA — DAC A Reference Voltage Input. Pin 6 — VREFL — DAC Reference Voltage Input Low, common to all DACs. Pin 7 — PRESETL — Preset Input; active low; all DAC registers forced to 80H. Pin 8 — VINE — DAC E Reference Voltage Input. Pin 9 — VINF — DAC F Reference Voltage Input. Pin 10 — VOUTE — DAC E Voltage Output. Pin 11 — VOUTF — DAC F Voltage Output. Pin 12 — VOUTG — DAC G Voltage Output. Pin 13 — VOUTH — DAC H Voltage Output. Pin 14 — VING — DAC G Reference Voltage Input. Pin 15 — VINH — DAC H Reference Voltage Input. Pin 16 — LOADH — Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin 17 — CLOCK — Serial Clock Input; positive– edge triggered.
Pin 10 — VOUTG — DACG Voltage Output. Pin 11 — VOUTH — DACH Voltage Output. Serial Input Register into the decoded DAC Register. Pin 17 — SDI — Serial Data Input. Pin 18 — VDD — Positive 5V Power Supply. Pin 20 — VOUTD — DACD Voltage Output. from a standard 3-wire serial input digital interface. Table 1. Serial Input Decoded Truth Table
SP9843 4–quadrant multiplying DACs. some op amp internal nodes toward the supply rails. to function in the same manner as a 50 ohm resistor. Figure 3. Reference Voltages a) Normal Operation; b) Maximum Linearity Near Code 1
is requested, feedback within the op amp circuit will force internal nodes to the rails, while the output will remain saturated near this minimum value. Non–saturated monotonic behavior returns between 25mV and 100mV at the output, but full open loop gain and linearity are not apparent until the output voltage is nearly 100mV above the negative supply. Applications which require good linearity for codes near zero should drive the VREFL input at least 100mV above the ground pin, as this insures that the output voltage will not go below 100mV for any legal input voltage. Two–quadrant applications (programmable gain/attenuator) usually bias VREFL up at system pseudoground, well above this saturation region, and therefore maintain linearity even at high attenuations (i.e. at code 1). The allowable, useful values of VIN(X) and VREFL are limited if a legal output value is to be expected for all input codes. At maximum gain (DAC code 255) VOUT is approximately equal to 2VIN(X) – VREFL. By solving this equation twice, once with VOUT set to 0V, and then again with Vout set to VDD–1.5V, the chart of Figure 3a results. This chart can be used to find the maximal VIN(X) voltage excursions for any given voltage driven into VREFL. The upper line plots the maximum voltage at VIN(X) and the lower line plots the mini- mum voltage at VIN(X) at each value of VREFL drive. Normal operation would be for VIN(X) anywhere between the two lines. For example, assume a 4.75V supply voltage, and that the DAC code is set to 255. If VREFL is driven to 1.6V, VIN(X) below 0.8V would require the output amplifier to swing below ground. VIN(X) above 2.425V would require output voltages greater than VDD – 1.5V, or 3.25V. Figure 3b shows the limits on VIN when the mini- mum VOUT is constrained to be greater than 100mV, for extremely linear operation, even at DAC code 1. In this case, the lower line is 50mV above its position in Figure 3a, except that below VREFL = 100mV, the minimum input voltage stays at 100mV. It should be noted that VIN(X) can always be driven to or slightly beyond the supply rails without harm. Under such circumstances, the DAC code can always be set to provide sufficient attenu- ation to get an undistorted output. Driving the Reference Inputs The VIN inputs exhibit a code–dependent input resis- tance, as shown in the specifications. In general, these inputs should be driven by an amplifier capable of handling the specified load resistance and capaci- tance. The reference inputs are useful for both ac and dc input sources. However, series resistance into these pins will degrade the linearity of the DAC. A series resistance of 50 Ohms can cause up to 0.5LSB of additional integral linearity degradation for codes near full scale, due to the code–dependent input current dropping across this error resistance. AC– coupled applications should use the largest capacitor value (lowest series resistance) which is practical, or, use an external buffer to drive the inputs. The DAC switches function in a break–before–make manner in order to minimize current spikes at the reference inputs. As previously noted, the reference inputs can withstand driving voltages slightly beyond the power supply rails without harm. The gain of 2 at the op amps limits the choice of VIN/VREFL combina- tions if clipping is to be avoided at the higher codes. Output Considerations Each DAC output amplifier can easily drive 1Kohm loads in parallel with 15pF at its rated slew rate. The unique BiCMOS amplifier design also ensures stabil- ity into heavily capacitive loads — up to 47,000pF. Under these conditions, the slew rate will be limited by the instantaneous current available for charging the capacitance — the slew rate will be severely degraded, and some damped ringing will occur. Especially under heavy capacitive loading, a large, low imped- ance local bypass capacitor will be required. A 0.047µF ceramic in parallel with a low–ESR 2.2 to 10µF tantalum are recommended for worst–case loads. The amplifier outputs can withstand momentary shorts to VDD or ground. Continuous short circuit operation can result in thermally induced damage, and should be avoided. If the input reference voltage is reduced to 0.6V, then both the amplifier and DAC are functional at room temperature at supply voltages as low as 2.5V. At VDD = 2.7V, power dissipation is 9.3mW typical, with the serial clock at 4MHz, or 7.0mW typical with the serial clock gated off. Interfacing to the SP9841/SP9842 A simple serial interface, similar to that used in a 74HC594 shift–register with output latch, has been implemented in these products. A serial clock is used
Figure 4. Timing. Table 2. Logic Control Input Truth Table. Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high.
to strobe serial data into a 12–stage shift–register at each rising clock edge. The first four serial bits contain the address of the DAC to be updated, MSB first. The next 8 bits contain the binary value to be loaded into the desired DAC, again MSB first. After the 12th serial bit is clocked in, the LOADH line can be strobed to latch the 8 bits of data into the data holding register for the desired DAC. The address bits feed a decoding network which steers the LOADH pulse to the clock input of the desired DAC data holding register. The output of the 12th shift–register is also buffered and brought out as the SERIAL DATA OUT (SDO), which can be used to cascade multiple devices, or for data verification purposes. The address field is set up such that DAC A is addressed at 0001 (binary). Address 0000(binary) will not affect the operation of any channel, as this combination is easily generated inadvertently at power–up. Other no–operation addresses exist at 1001(binary) through 1111(binary). Another use for no–operation addresses is to mask off updates of any DAC channel in a multiple–part system with cas- caded serial inputs and outputs. By sending a valid address and data only to the desired channel, it is possible to simplify the system hardware by driving the LOADH pin at each part in parallel from a single source. Table 1 shows a register–level diagram of the addresses, data, and the resulting operation. A fourth control pin, PRESETL, can be used to simultaneously preset all DAC data holding registers to their mid–scale (80H) values. This will asynchro- nously force all DAC outputs to buffer the voltages at their respective inputs to their outputs with unity gain. This feature is useful at power–up, as a simple resistor to the supply and capacitor to ground can insure that all DAC outputs start at a known voltage. It can also be used to implement stand-alone (non–programmed) applications, such as a unity gain octal cable driver. Table 2 summarizes the operation of the four digital control inputs. The four digital control input pins have been designed to accept TTL (0.8V to 2.0V minimum) or full 5V CMOS input levels. Timing information is shown in Figure 4. Serial data is fully clocked into the shift–register after 12 clock rising edges, subject to the described setup and hold times. After the shift–register data is valid, the LOADH line can be pulsed high to load data into the desired DAC data register, which switches the DAC to the new input code. The serial clock input should not see a rising edge while the LOADH pulse is high in order to prevent shift–register data from corrup- tion during data register loading. The serial clock and data input pins are designed to be compatible as slaves under National Semiconductor's Microwire™ and MicrowirePlus™ protocols and under Motorola's SPI™ and QSPI™ protocols. In some micro–controllers, the interface is completed by programming a bit in a general–purpose I/O port as a level, used to strobe the LOADH line at the DACs. This is done in a manner similar to that used for generating a CS signal, which is necessary when driving some other Microwire™ peripherals. Low Voltage Operation At nominal VDD, the CMOS switches used in the DAC obtain sufficient drive to maintain an ON- resistance much lower than the thin–film resistors. This keeps the non–linear voltage–dependent portion of their ON-resistances low, and guarantees both excellent DAC linearity versus code, and low–distor- tion multiplication of large–swinging AC inputs. The devices in the op amp also receive sufficient drive to guarantee the specified bandwidth and output drive current. However, all circuits within the DACs are quite "functional" at very low values of VDD. By reducing the reference voltages such that the maxi- mum VOUT is near the target of VDD-1.5V, the DACs will provide better than 0.5LSB typical integral per- formance for DC output voltages between 100mV and VDD-1.5V. Reducing the reference voltage actu- ally aids the linearity of the DACs, even at nominal VDD. This occurs because the NMOS half of the CMOS switches are more fully utilized at reference voltages closer to ground, thus further reducing the ON–resistance of the switches. Reference input cur- rents are proportional to the reference voltages and will also decrease with the reference voltages. Plot 19 shows typical DC output linearity for VIN(X) set to 0.5V, with VDD at 2.5, and then 3.5V. Note that at 3.5V, the linearity is actually much better than the ±0.25LSB typical performance at VIN(X) = 1.625V and VDD = 5V. Similarly, Plot 20 shows that this performance level persists for VDD = 4.5V and 5.5V, with VIN(X) set to 0.6V. The price paid for low voltage operation is in op amp gain, bandwidth and es– pecially current sinking at the DAC output. Plots 17
50 Ohm resistor to ground, and the VREFL output
Figure 12. AC–Coupled, Programmable Gain/Attenuator with Bootstrapped Programmable Output DC Offset (VREFL Drive). Load DACA with code 90; sets VREFL =1.7V.
Figure 14. Two–Channel Multiplexed Window Comparator with Programmable Gain and Limits.
input DACs to the proper code. The LM339 does not really drive the LED to full illumina- tion, due to limited output current, but a pull–up resistor alone will yield a functional TTL error signal. External op amps could use the VREFL voltage as pseudoground. The outputs of the two signal DACs must be isolated with resistors if the two signals are to be multiplexed. This will reduce the signal gain to 255/256 maximum, due to the resistive divider created at the com- parator input. If only a single channel was to be window–compared, then the maximum gain to the comparator would be the usual 255/128. Figure 15 shows the schematic of an evaluation board, which can be used with an IBM–compat- ible (XT or AT) computer and the simple QuickBasic routine of Figure 16 to load each DAC channel with its desired code. A straight– through 25-pin cable can be used, or the board can be plugged directly into the back of the PC. Data is first latched into each 'HC165 parallel– to–serial converter. Then a small state machine is initiated by strobing INI. It clocks the latched data into the serial data input and strobes the LOADH input at the DAC. A pair of banana jacks is used for applying VDD from an external supply. A trimpot–adjustable voltage reference is tied to all eight DAC inputs. On the evaluation board, jumpers will allow this reference to drive any VIN(X) input or the VREFL pin. The other three op amps in the quad OP–491 are available for breadboarding circuits, such as in Figures 1 through 14. If the reference voltage is adjusted down to 0.5V, the DAC and the board should function with VDD as low as 2.5V. Driving Capacitive Loads Unlike many other products, the SP9841/9842 will not oscillate under purely capacitive load- ing. However, fullscale step outputs will show overshoot and ringing of up to 40% at worst– case purely capacitive loading (between 1,000 and 10,000pF). Figures 17 through 20 show near fullscale steps under capacitive loads of between 470pF and 0.47µF. For capacitance up to 10,000pF, the addition of a resistive load to ground at the op amp output will decrease set- tling times without adversely affecting the posi- tive–going slew rate. For higher capacitances, this settling time enhancement comes at the expense of positive slew rate, as not all instan- taneous current can be used to charge the capaci- tor. For all values of capacitive load, settling time can be dramatically reduced by adding a small resistor in series with the DAC outputs. Such series resistors will degrade the current sinking ability at the DAC outputs for voltages near ground; while the DACs typically sink 2mA at VDD =5V at VOUT = 110mV, the addition of a 50Ohm resistor would require 210mV after the resistor to sink 2mA. Large capacitances require lower values of series resistance in order to obtain critical damping.
Figure 15. Evaluation Board — Loads SP9841/9842 from IBM PC Parallel Port
- ALL DIGITAL IC'S BYPASSED WITH 0.1µF TO GROUND
- THREE UNCOMMITTED OP AMPS IN THE OP–491 PACKAGE
ARE AVAILABLE FOR USER APPLICATIONS.
Figure 16. Microsoft qbasic Program to Load Evaluation Board with Desired Codes. 'output will be: Vout-(data/128)*VREF volts. 'LPT1 port address was 3BCH (Data Register #BCH and control register 3BEH).