SP9840 SIPEX | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
I Replaces 8 Potentiometers and 8 Op amps I Operates from Single +5V Supply I 5 MHz 4-Quadrant Multiplying Band- width I Eight Inputs/Eight Outputs (SP9840) Four Inputs/Eight Outputs (SP9843) I 3-Wire Serial Input I 0.8MHz Data Update Rate I +3.25V Output Swing I Midscale Preset I Programmable Signal Inversion I Low 70mW Power Dissipation (9mW/DAC) DAC 1 DAC 8 8 x 8 DAC REGISTER SERIAL REGISTER LOGIC Decoded Address Data Clock Serial Data Input Serial Data Output Preset Load VIN1 VOUT1 VIN8 VOUT8 VREF Low SP9840 shown DESCRIPTION… The SP9840 and SP9843 are general purpose octal DACs in a single package. The SP9840 features eight individual reference inputs, while the SP9843 provides four pair of voltage reference inputs. Both parts feature 5MHz bandwidth, four–quadrant multiplication, and a three– wire serial interface. Other features include midscale preset, programmable signal inversion and low power dissipation from a single +5V supply. Devices are available in commercial and industrial temperature ranges. SP9840/43 8-Bit Octal, 4-Quadrant Multiplying, BiCMOS DAC
These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Operating Temperature Range Thermal Resistance 8JA CAUTION: While all input and output pins have internal protection networks, these parts should be considered ESD (ElectroStatic Discharge) sensitive de- vices. Permanent damage may occur on unconnected devices subject to high en- ergy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed. SPECIFICATIONS (VDD = +5V, All VINX= 0V, VREFL = 1.625V, TA = 25° C for commercial–grade parts; TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to all DAC's unless noted otherwise.) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS SIGNAL INPUTS Input Voltage Range 3.25 V VDD = 4.75V, VREFL = 1.625V Input Resistance D = 2BH, Code Dependent SP9840 3.1 6.2 kΩ SP9843 1.55 3.1 kΩ Input Capacitance Note 1 SP9840 pF SP9843 pF VREFL Resistance 0.68 1.3 kΩ Note 1 and 2 VREFL Capacitance 190 250 pF Note 1 DIGITAL INPUTS Logic High 2.4 V Logic Low 0.8 V Input Current ±10 µA Input Capacitance pF Input Coding Offset Binary Note 3 STATIC ACCURACY Resolution Bits Integral Nonlinearity ±0.75 ±1.5 LSB Note 4 Differential Nonlinearity ±0.3 LSB Note 4 Half-Scale Output Voltage 1.600 1.625 1.650 V PR = LOW, VREFL = 1.625V Minimum Output Voltage 100 mV D=FFH; ISINK = 0.1mA Output Voltage Drift µV/°C PR = LOW DYNAMIC PERFORMANCE Multiplying Gain Bandwidth MHz VIN(X) = 100mVP–P + 1.625V dc Slew Rate Measured 10% to 90% Positive 3.0 7.9 V/µs ∆V = 3.2V Negative –3.0 –8.3 V/µs ∆V = –3.2V Total Harmonic Distortion 0.003 VIN(X) = 3VP–P +1.625V dc, D=FFH; 1KHz, fLP=80KHz Output Settling Time 0.7 µs ±1 LSB Error Band Crosstalk dB Note 5 Digital Feedthrough nVs D = 0H to FFH Wideband Noise 42.5 µVrms VOUT = 3.25V, 400Hz to 80kHz SINAD dB VIN(X) = 3VP–P +1.625V dc, D=FFH; 1KHz, fLP=80KHz Digital Crosstalk nVs Note 6
SPECIFICATIONS (continued) VDD = +5V, All VINX= +0V, VREFL = 1.625, TA = 25° C for commercial–grade parts; TMIN ≤ TA = TMAX for industrial–grade parts; specifications apply to all DAC's unless noted otherwise.) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS DAC OUTPUTS Voltage Range VDD – 1.5 V RL = 5kΩ, VDD = 4.75V Output Current ±10 ±15 mA Note 7 Capacitive Load 47,000 pF No Oscillation DIGITAL OUTPUT Logic High 3.5 V IOH = –0.4mA Logic Low 0.4 V IOL = 1.5mA POWER REQUIREMENTS Power Supply Range 4.75 5.00 5.25 V To rated specifications Positive Supply Current mA PR = LOW Power Dissipation mW PR = LOW ENVIRONMENTAL AND MECHANICAL Operating Temperature Range Commercial +70 Industrial –40 +85 Storage Temperature Range –65 +150 Package SP9840N 24–pin, 0.3" Plastic DIP SP9840S 24–pin 0.3" SOIC SP9843S 20–pin, 0.3" SOIC Note 8 Notes: Code dependent All VIN(x) = GND; D = 55H Offset binary refers to the output voltage with respect to the signal ground at VREFL. For a positive VIN(x), the output will increase from negative fullscale to VREFL to positive (fullscale–1 LSB) as the input code is incremented from 0 to 128 to 255. Note that when VIN(x) is tied to ground and VREFL is driven to +1.625V, as in the production tests above, then the resulting DC at VOUT(x) will decrease from +2VREFL to VREFL/128 as the code is increased from 00H to FFH, due to the VIN(x) input being tied negative with respect to VREFL. The op amp limits linearity for VOUT <100mV. When VIN(x) is driven above ground such that the output voltage remains above 100mV, then the linearity specifications apply to all codes. For VREFL=1.625V, and VIN(x)=GND, codes 248 through 255 are not included in differential or integral linearity tests. Integral and differential linearity are computed with respect to the best fit straight line through codes 0 through 248. SP9840 is measured between adjacent channels, F=100kHz. SP9843 is measured between adjacent pairs, F=100kHz. SP9843 only; measured between channels with shared input; D = 7FH to 80H ∆VOUT < 10mV, VREFL = 1.625V, PR = LOW. For plastic DIP, consult factory
24 VOUTD
23 VINC
22 VIND
21 VDD
20 SDI
19 GND
18 SDO
17 CLOCK
16 LOADH
15 VINH
14 VING
13 VOUTH
Pin 1 — VOUTC — DACC Voltage Output. Pin 2 — VOUTB — DACB Voltage Output. Pin 3 — VOUTA — DACA Voltage Output. Pin 4 — VINB — DAC B Reference Voltage Input. Pin 5 — VINA — DAC A Reference Voltage Input. Pin 6 — VREFL — DAC Reference Voltage Input Low, common to all DACs. Pin 7 — PRESETL — Preset Input; active low; all DAC registers forced to 80H. Pin 8 — VINE — DAC E Reference Voltage Input. Pin 9 — VINF — DAC F Reference Voltage Input. Pin 10 — VOUTE — DACE Voltage Output. Pin 11 — VOUTF — DACF Voltage Output. Pin 12 — VOUTG — DACG Voltage Output. Pin 13 — VOUTH — DACH Voltage Output. Pin 14 — VING — DACG Reference Voltage Input. Pin 15 — VINH — DACH Reference Voltage Input. Pin 16 — LOADH — Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin 17 — CLOCK — Serial Clock Input; positive-edge triggered. Pin 18 — SDO — Serial Data Output; active totem-pole output. Pin 19 — GND — Ground. Pin 20 — SDI — Serial Data Input. Pin 21 — VDD — Positive 5V Power Supply. Pin 22 — VIND — DACD Reference Voltage Input. Pin 23 — VINC — DACC Reference Voltage Input. Pin 24 — VOUTD — DACD Voltage Output. SP9843 PINOUT
20 VOUTD
19 VINC/D
18 VDD
17 SDI
16 GND
15 SDO
14 CLOCK
13 LOADH
12 VING/H
11 VOUTH
Pin 1 — VOUTC — DACC Voltage Output. Pin 2 — VOUTB — DACB Voltage Output. Pin 3 — VOUTA — DACA Voltage Output. Pin 4 — VINA/B — DACA and B Reference Voltage Input. Pin 5 — VREFL — DAC Reference Voltage Input Low, common to all DACs. Pin 6 — PRESETL — Preset Input; active low; all DAC registers forced to 80H. Pin 7 — VINE/F — DAC E and F Reference Voltage Input. Pin 8 — VOUTE — DACE Voltage Output.
Pin 9 — VOUTF — DACF Voltage Output. Pin 10 — VOUTG — DACG Voltage Output. Pin 11 — VOUTH — DACH Voltage Output. Pin 12 — VING/H — DACG and H Reference Voltage Input. Pin 13 — LOADH — Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin 14 — CLOCK — Serial Clock Input; positive-edge triggered. Pin 15 — SDO — Serial Data Output; active totem-pole output. Pin 16 — GND — Ground. Pin 17 — SDI — Serial Data Input. Pin 18 — VDD — Positive 5V Power Supply. Pin 19 — VINC/D — DACC and D Reference Voltage Input. Pin 20 — VOUTD — DACD Voltage Output. SP9840/SP9843 Theory of Operation Each of the eight channels of the SP9840/9843 can be used for signal reconstruction, as a pro- grammable DC source, or as a programmable signed attenuator of –1 to +0.992 times a multi- plying AC reference input. The rugged wideband output amplifiers provide both current sink and source capability to DC applications, even into difficult loads. The DC source mode mimics the functionality of a programmable trimpot, with the added benefit of a low–impedance buffered output. The amplifier's bandwidth and high open loop gain allow use in programmable signed attenuator applications where even low–distor- tion, high resolution signals, such as audio, must be gated on and off, programmable phase shifted by 0° or 180° or gain controlled over a –42 to 0dB range at either phase. Each channel consists of a voltage–output DAC, realized using CMOS switches and thin–film resistors in an inverted R–2R configuration. Each DAC drives the positive terminal of an op amp, configured for a gain of –1 to +1 using equal value thin–film feedback and gain–setting resistors. Signal return is the VREFL pin, the common reference input return for the eight DAC–op amp channels. As shown in Figure 1, the DAC section can be thought of as a potentiometer across VIN(X) to VREFL. If this potentiometer is set to its minimum value of 0/256, the potentiometer will have no effect on the gain, and the output will be –RF/RIN = –1 times the input. If the potentiometer could be set to 256/256, then the amplifier positive terminal would see 100% of any input and no current would flow through RIN. The circuit would behave as a non–inverting unity gain circuit, although with a noise gain of two, not one. In reality, the "potentiometer" can only be set to 255/256, and the maximum positive gain is 0.992 times the voltage between VIN(X) and VREFL. The true relation between the DC levels at the VIN(X) pins, VREFL and the output can be de- scribed as: where D is programmable from 0 to 255. For single supply operation VREFL is usually externally driven to some voltage above ground — typically 1.5 to 2.5V. IF VREFL is driven to 1.5V, and VIN(X) is grounded, then code 0 would output +3.0V, and code 255 would output +11.7mV. If VREFL were grounded and VIN(X) driven to 1.5V, then codes between 0 and 128 would attempt to drive the output below ground, which will saturate the output amplifier at some voltage slightly above ground. V D V V V OUT IN REFL REFL = ( ) − ) + 128 USING THE SP9840/9843 Multiplication of Input Voltages While both the SP9840 and SP9843 are capable of four–quadrant multiplication, this terminology is not
Figure 2. a) Inverted Single–Quadrant Operation; b) 4–Quadrant Operation SP9841 or SP9842 two–quadrant multiplying DACs. limited by the legal voltage swing at the op amp output. ity of driving the output to voltages close to ground. high attenuations (i.e. near code 80HEX). Table 2. Logic Control Input Truth Table. Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high.
the specified load resistance and capacitance. The reference inputs are useful for both AC and DC input sources. However, series resistance into these pins will degrade the linearity of the DAC — 50 Ohms of series resistance can cause up to 0.5LSB of additional integral linearity degradation for codes near zero, due to the code–dependent input current dropping across this error resistance. AC–coupled applications should use the largest capacitor value (lowest series imped- ance) which is practical, or use an external buffer to drive the inputs. The DAC switches function in a break–before–make manner in order to minimize current spikes at the reference inputs. The reference inputs can withstand driving voltages slightly beyond the power rails with- out harm; the gain of ±1 at the op amps limits the choice of VIN/VREFL combinations if clipping is to be avoided at very high or very low codes. Note that rail– to–rail inputs can always be attenuated by choosing a code nearer midscale, if clipping of the output is undesirable. Output Considerations Each DAC output amplifier can easily drive 1Kohm loads in parallel with 15pF at its rated slew rate. The unique BiCMOS amplifier design also ensures stabil- ity into heavily capacitive loads — up to 47,000pF. Under these conditions, the slew rate will be limited by the instantaneous current available for charging the capacitance — the slew rate will be severely degraded, and some damped ringing will occur. Especially under heavy capacitive loading, a large, low imped- ance local bypass capacitor will be required. A 0.047µF ceramic in parallel with a low–ESR 2.2 to 10µF tantalum are recommended for worst–case loads. The amplifier outputs can withstand momentary shorts to VDD or ground. Continuous short circuit operation can result in thermally induced damage, and should be avoided. If the input reference voltage is reduced to 0.6V, then both the amplifier and DAC are functional at room temperature at supply voltages as low as 2.5V. At VDD = 2.7V, power dissipation is 9.3mW typical, with the serial clock at 4MHz, or 7.0mW typical with the serial clock gated off. Interfacing to the SP9840/SP9843 A simple serial interface, similar to that used in a 74HC594 shift–register with output latch, has been implemented in these products. A serial clock is used to strobe serial data into a 12–stage shift–register at each rising clock edge. The first four serial bits contain the address of the DAC to be updated, MSB first. The next 8 bits contain the binary value to be loaded into the desired DAC, again MSB first. After the 12th serial bit is clocked in, the LOADH line can be strobed to latch the 8 bits of data into the data holding register for the desired DAC. The address bits feed a decoding network which steers the LOADH pulse to the clock input of the desired DAC data holding register. The output of the 12th shift–register is also buffered and brought out as the SERIAL DATA OUT (SDO), which can be used to cascade multiple devices, or for data verification purposes. The address field is set up such that DACA is ad- dressed at 0001 (binary) and the others consecutively through DACH at 1000(binary). Address 0000(bi- nary) will not affect the operation of any channel, as this combination is easily generated inadvertently at power–up. Other no–operation addresses exist at 1001(binary) through 1111(binary). Another use for no–operation addresses is to mask off updates of any DAC channel in a multiple–part system with cas- caded serial inputs and outputs. By sending a valid address and data only to the desired channel, it is possible to simplify the system hardware by driving the LOADH pin at each part in parallel from a single source. Table 1 shows a register–level diagram of the addresses, data, and the resulting operation. A fourth control pin, PRESETL, can be used to simultaneously preset all DAC data holding registers to their mid–scale (80H) values. This will asynchro- nously force all DAC outputs to buffer the voltages at their respective inputs to their outputs with unity gain. This feature is useful at power–up, as a simple resistor to the supply and capacitor to ground can insure that all DAC outputs start at a known voltage. For four– channel multiplying applications, this sets the default start–up gain to zero; only –70dB of feedthrough from the VIN(X) inputs will be present at the outputs. Table 2 summarizes the operation of the four digital inputs.
output can drive either TTL or CMOS inputs. level, used to strobe the LOADH line at the DACs. when driving some other Microwire™ peripherals. Figure 3. Timing