SP9502JS

SP9502 SIPEX | Alldatasheet

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SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation I Low Cost I Two 12-bit DAC’s on a Single Chip I Low Power — 40 mW (20mW/DAC) I Double-Buffered Inputs I ± 5V Supply Operation I Voltage Outputs, ± 4.5V Range I Midscale Preset, Zero Volts Out I Guaranteed +0.5 LSB Max INL I Guaranteed +0.75 LSB Max DNL I 2 MHz 4-Quadrant Multiplying Bandwidth I Separate Reference Inputs I 28–pin SOIC and Plastic DIP Packages I Either 12 or 8 bit µp bus

DESCRIPTION

The SP9502 is a low power, dual version of the popular SP9345, Quad 12-Bit Digital-to-Analog Converter. It features ±4.5V output swings when using ±5 volt supplies. The converter is double- buffered for easy microprocessor interface. Each 12-bit DAC is independently addressable and both DACS may be simultaneously updated using a single transfer command. The output settling-time is specified at 4µs. The SP9502 is available in 28–pin SOIC and DIP packages, specified over commercial temperature range. DAC DAC LATCH LATCH LATCH LATCH

8 MSB's

4 LSB's

A CS WR1 B1/B2 WR2 XFER CLR CONTROL LOGIC INPUT REGISTERS DAC REGISTERS DATA INPUTS SP9502 Dual, 12–Bit, Voltage Output D/A Converter SIGNAL PROCESSING EXCELLENCE

SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Power Dissipation (derate 7mW/°C above +70°C) (derate 7mW/˚C above +70˚C) SPECIFICATIONS (Typical at 25˚C, TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DIGITAL INPUTS Logic Levels VIH 2.4 Volts VIL 0.8 Volts

4 Quad, Bipolar Coding

+4.5 Volts Note 5 Input Resistance 8.8 kΩ DIN = 1877, code dependent ANALOG OUTPUT Gain +0.5 +2.0 LSB VREF = ±3V; Note 3 +1.0 +4.0 LSB VREF = ±3V; Note 3 +1.0 +5.0 LSB VREF = ±4.5V; Note 3 Initial Offset Bipolar +0.25 +3.0 LSB DIN = 2,048 Voltage Range Bipolar +3.0 +4.5 Volts Output Current +5.0 mA VREF = ±3V +0.5 mA VREF = ±4.5V STATIC PERFORMANCE Resolution Bits Integral Linearity +0.25 +0.5 LSB VREF = ±3V; Note 3 +0.5 +1.0 LSB VREF = ±3V; Note 3 +0.5 +3.0 LSB VREF = ±4.5V; Note 3 Differential Linearity +0.25 +0.75 LSB +0.25 +1.0 LSB Monotonicity Guaranteed DYNAMIC PERFORMANCE Settling Time Small Signal 0.5 µs to 0.012% Full Scale µs to 0.012% Slew Rate V/µs Multiplying Bandwidth MHz

SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation CODE 4095 INLE, DLNE Plots +0.25 lsb DNLE -0.25 lsb +0.25 lsb INLE -0.25 lsb SPECIFICATIONS (continued) (Typical at 25˚C, TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS STABILITY Gain ppm/˚C tMIN to tMAX Bipolar Zero ppm/˚C tMIN to tMAX SWITCHING CHARACTERISTICS tDS Data Set Up Time 140 100 ns to rising edge of WR1, tDN Data Hold Time ns Figure 4 tWR Write Pulse Width 140 100 ns tXFER Transfer Pulse Width 140 100 ns tWC Total Write Command 280 200 ns POWER REQUIREMENTS Note 5 VDD +5V, ±3%; Note 4, 5 –J, –K mA VSS -5V, ±3%; Note 4, 5 –J, –K mA Power Dissipation mW ENVIRONMENTAL AND MECHANICAL Operating Temperature -J, -K +70 Storage -60 +150 Package 28–pin Plastic DIP 28–pin SOIC Notes: Integral Linearity, for the SP9502, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 1 LSB = 2*VREF/4,096. VREF = 0V. The following power up sequence is recommended to avoid latch up: VSS (-5V), VDD (+5V), REFIN.

SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation are forced to 1000 0000 0000 and the DAC outputs will settle to OV. Active low. Pin 13 — WR1 — Write Input1 — In conjunction with CS (pin 14), enables input register selection, and controls the transfer of data from the input bus to the input registers. Active low. Pin 14 — CS — Chip Select — Enables writing data to input registers and/or transferring data from input bus to DAC registers. Pin 15 — VOUT1 — Voltage Output from DAC1. Pin 16 — DB11 — Data Bit 11; most significant bit. Pin 17 — DB10 — Data Bit 10. Pin 18 — DB9 — Data Bit 9. Pin 19 — DB8 — Data Bit 8. Pin 20 — DB7 — Data Bit 7. Pin 21 — DB6 — Data Bit 6. Pin 22 — DB5 — Data Bit 5. Pin 23 — DB4 — Data Bit 4. Pin 24 — DB3 — Data Bit 3. Pin 25 — DB2 — Data Bit 2. Pin 26 — DB1 — Data Bit 1. Pin 27 — DB0 — Data Bit 0; LSB Pin 28 — N.C. — No Connection. PINOUT — 28–PIN SOIC & DIP PIN ASSIGNMENTS Pin 1 — N.C. — No Connection. Pin 2 — VOUT 2 — Voltage Output from DAC2. Pin 3 — VSS — –5V Power Supply Input. Pin 4 — VDD — +5V Power Supply Input. Pin 5 — CLR — Clear. Gated with WR2 (pin 12). Active low. Clears both DAC outputs to 0V. Pin 6 — REF IN2 — Reference Input for DAC2. Pin 7 — GND — Ground. Pin 8 — B1/B2 — Byte 1/Byte 2 — Selects Data Input Format. A logic “1” on pin 8 selects the 12– bit mode, and all 12 data bits are presented to the DAC(s) unchanged; a logic “0” selects the 8–bit mode, and the four LSBs are connected to the four MSBs, allowing an 8–bit MSB–justified interface. Pin 9 — A — Address for DAC Selection — A logic “0” selects DAC 1; a logic “1” selects DAC 2. Pin 10 — REF IN1 — Reference Input for DAC1. Pin 11 — XFER — Transfer. Gated with WR2 (pin 12); loads all DAC registers simultaneously. Active low. Pin 12 — WR2 — Write Input 2 — In conjunction with XFER (pin 11), controls the transfer of data from the input registers to the DAC registers. In conjunction with CLR (pin 5), the DAC registers N.C. VOUT2 VSS VDD CLR Ref In 2 GND B1/B2 A Ref In 1 XFER WR2 WR1 CS N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 VOUT1 SP9502

SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation most significant bits (MSBs), allowing an 8-bit MSB-justified interface. All data inputs are enabled using the CS signal in both modes. The digital inputs are designed to be both TTL and 5V CMOS compatible. In order to reduce the DAC full scale output sensitivity to the large weighting of the MSB’s found in conventional R-2R resistor ladders, the 3 MSB’s are decoded into 8 equally weighted levels. This reduces the contribution of each bit by a factor of 4, thus, reducing the output sensitivity to mis- matches in resistors and switches by the same amount. Linearity errors and stability are both improved for the same reasons. Each D/A con- verter is separated from the data bus by two reg- isters, each consisting of level-triggered latches, Figure 1. The first register (input register) is 12- register to a precision voltage. feedback resistors connected as shown in Figure 2.

FEATURES

The SP9502 is a low power, dual version of the popular SP9345, Quad 12-Bit Digital-to-Analog Converter. This Dual, Voltage Output, 12-Bit Digital-to-Analog Converter features ±4.5V output swings when using ±5 volt supplies. The input coding format used is standard offset binary. (Refer to Table 1 below.) The converter utilizes double-buffering on each of the 12 parallel digital inputs, for easy microprocessor interface. Each 12-bit DAC is independently addressable and both DACS may be simulta- neously updated using a single XFER command. The output settling-time is specified at 4µs to full 12–bit accuracy when driving a 5Kohm, 50pf load combination. The SP9502, Dual 12-Bit Digital- to-Analog Converter is ideally suited for applica- tions such as ATE, process controllers, robotics, and instrumentation. The SP9502 is available in 28–pin plastic SOIC and plastic DIP packages, specified over the commercial (0°C to +70°C) temperature range. Table 1. Offset Binary Coding

1 LSB = 2VREF

5) Repeat sequence for each input register. CS through the “1” — “0” — “1” sequence.

3 TO 7

5 BITS

Figure 1. Detailed Block Diagram (only one DAC shown) user must be interfaced to a 12-bit bus only (B1=1). scale readings for both DAC’s; Figure 3, bottom.

Figure 2. Transfer Function X = Don’t care; ** = Don’t care; however, CS and WR1 = 1 will inhibit changes to the input registers. Table 2. Control Logic Truth Table

SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation D ALTERNATE END PINS (BOTH ENDS) D1 = 0.005" min. (0.127 min.) E PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) DIMENSIONS (Inches) Minimum/Maximum (mm) A = 0.210" max. (5.334 max). C Ø L A1 = 0.015" min. (0.381min.) B e = 0.100 BSC (2.540 BSC) eA = 0.300 BSC (7.620 BSC) B C D E L Ø 24–PIN 0.115/0.195 (2.921/4.953) 0.014/0.023 (0.356/0.584) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.155/1.280 (29.33/32.51) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°) 28–PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.385/1.454 (35.17/36.90) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°)

SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation D E H PACKAGE: PLASTIC SMALL OUTLINE (SOIC) DIMENSIONS (Inches) Minimum/Maximum (mm) 14–PIN A Ø L B e A B D E e H L Ø 16–PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.398/0.413 (10.10/10.49) 0.291/0.299 (7.402/7.600)

0.050 BSC

(1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) 18–PIN 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.447/0.463 (11.35/11.74) 0.291/0.299 (7.402/7.600) (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) 20–PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.496/0.512 (12.60/13.00) 0.291/0.299 (7.402/7.600) (1.270 BSC)) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) 24–PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.599/0.614 (15.20/15.59) 0.291/0.299 (7.402/7.600) (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) 28–PIN 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.697/0.713 (17.70/18.09) 0.291/0.299 (7.402/7.600) (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) 0.090/0.104 (2.29/2.649)) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.348/0.363 (8.83/9.22) 0.291/0.299 (7.402/7.600) (1.270 BSC) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°)

SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation

ORDERING INFORMATION

Monolithic 12-Bit Dual DAC Voltage Output: Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office

22 Linnell Circle

Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office

233 South Hillview Drive

Milpitas, CA 95035 TEL: (978) 934-7500 FAX: (978) 935-7600 Far East: JAPAN: Nippon Sipex Corporation Yahagi No. 2 Building 3-5-3 Uchikanda, Chiyoda-ku Tokyo 101 TEL: 81.3.3256.0577 FAX: 81.3.3256.0621 European Sales Offices: ENGLAND: Sipex Corporation

2 Linden House

TEL: 44-1420-549527 FAX: 44-1420-542700 e-mail: mikeb@sipex.co.uk GERMANY: Sipex GmbH Gautinger Strasse 10

82319 Starnberg

TEL: 49.81.51.89810 FAX: 49.81.51.29598 e-mail: sipex-starnberg@t-online.de Please consult the factory for pricing and availability on a Tape-On-Reel option.