SP9316

SP9316 SIPEX | Alldatasheet

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SIGNAL PROCESSING EXCELLENCE 181 SP9316 16–Bit CMOS Multiplying DAC n High Stability with No Laser–Trimming n 15–Bit Monotonicity over Temperature n Single Power Supply Operation n Upper/Lower Byte Input Registers n 2– and 4–Quadrant Multiplication n 60mW Power Dissipation LSB LATCH CONTROL REFERENCE INPUT MSB LATCH CONTROL IOUT2 I OUT1 FEEDBACK 5KΩ PRECISION 16-BIT RESISTOR NETWORK & SWICHES BIT: 9 10 11 12 13 14 15 16 ANA GND +15V 18 173 2 1 2 42 32 22 1 BIT: 8 7 6 5 4 3 2 1(MSB) 67891 0 1 1 1 2 INPUT REGISTER INPUT REGISTER SP9316 DESCRIPTION… The SP9316 is a 16–bit, monolithic CMOS, multiplying digital-to-analog converter with two 8–bit input registers for direct microprocessor interface. It offers two– and four–quadrant multiplying capability with TTL/DTL and CMOS logic compatibility. Operating from a single +15V supply, power dissipation is less than 60mW. The SP9316 is packaged in 24-pin ceramic or molded plastic. Models are available for operation over the commercial (0°C to 70°C) and military (–55°C to +125°C) temperature ranges. For product screened to MIL–STD–883, please consult the factory. Corporation SIGNAL PROCESSING EXCELLENCE

SIGNAL PROCESSING EXCELLENCE 182 ABSOLUTE MAXIMUM RATINGS (TA=25°C unless otherwise noted) These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. V SPECIFICATIONS (TA=25°C; VDD =+15V, VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS STATIC PERFORMANCE Resolution 16 Bits Integral Non-Linearity Note 5 C-4 ±0.006 %FSR B-4 ±0.006 %FSR Differential Non-Linearity Note 7 C-4 ±0.006 %FSR B-4 ±0.006 %FSR Offset Error 60 µV Note 3 Gain Error 0.1 0.2 %FSR Note 4 AC PERFORMANCE CHARACTERISTICS Propagation Delay 300 ns Note 9 Current Settling Time Major code settling times To 0.01% FSR (strobed) 2.0 µs To 0.00076% FSR (strobed) 3.0 µs Output Capacitance C O1 170 pF Digital input V IH C O2 30 pF Digital input V IH C O3 80 pF Digital input V IL C O4 100 pF Digital input V IL Glitch Energy 250 nV-s Note 10 Multiplying Feedthrough Error 3.0 mV P-P Note 11 0.3 mV P-P Note 12 STABILITY All Grades: Note 4 Gain Error TC ±1.0 ±4.0 ppm/ °C Note 6 Offset ±1.0 ppm/ °C Integral Non-Linearity TC ±0.1 ±1.0 ppm/ °C ±1.0 ppm/ °C Note 5 Monotonicity Guaranteed C-4 14 Bits B-4 14 Bits Power Supply Rejection ±0.0001 ±0.002 %/% V DD = 14.0V to 16.0V LONG-TERM STABILITY Differential Non-linearity 1 ppm/ °C Offset ±0.5 ppm/ °C Gain ±1 ppm/ °C REFERENCE INPUT Input Impedance 2.5 5.0 7.5 K Ω Voltage Range –10 +10 Volts SWITCHING CHARACTERISTICS Strobe Width 80 60 ns Data Setup Time 80 70 ns Data Hold Time 40 20 ns

SIGNAL PROCESSING EXCELLENCE 183 VREF (Volts) -10 -5 0 +5 + 10 0.5 1.0Error in LSB's Typical @ 25°C and +15V nominal SPECIFICATIONS (continued) (TA=25°C; VDD =+15V, VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS DIGITAL INPUTS Logic Levels VIH 2.4 V DD Volts VIL -0.3 0.8 Volts Input Current ±1.0 ±10.0 µA Note 1 Input Capacitance 8 pF Note 2 Coding 2-Quadrant Unipolar Binary 4-Quadrant Bipolar Offset Binary ANALOG OUTPUT Small Signal -3dB Bandwidth 1 MHz Output Capacitance C OUT1 90 pF C OUT2 70 pF POWER REQUIREMENTS Supply Current 2.0 4.0 mA DIG IN = V IL or VIH Voltage Range VDD +5 +15 +16 Volts Power Dissipation 60 mW DIG IN = V IL or VIH ENVIRONMENTAL AND MECHANICAL Operating Temperature Commercial 0 +70 °C Military -55 +125 °C Storage Temperature -65 +150 °C Package Commercial 24–pin Plastic DIP Military 24–pin CerDIP Notes and Cautions: 1. Logic inputs are MOS gates. I IN typically is less than 1nA @ 25°C. 2. Guaranteed by design, but not production tested. 3. Unipolar: Using the internal R FEEDBACK with nulled external amplifier in a constant 25°C ambient (offset doubles every 10°C). 4. Using internal feedback resistor. 5. Integral Linearity, for this product, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input combination. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 6. The SP9316 series is designed to be used only in those applications where the current output is virtual ground; i.e. the summing junction of an op amp in the inverting mode. The internal feedback resistor must be used to achieve temperature tracking. See applications information for recommended circuit configurations. 7. For military temperature range product, screened to MIL-STD-883C, please consult the factory. 8. Sample tested only to ensure compliance. 9. I O1 load RL = 100Ω , CEXT = 13pF; all data inputs 0V to VDD or VDD to 0V; from 50% digital input change to 90% of final analog output. 10. V REF = 0V, DAC register alternatively loaded with all 0’s and all 1’s. 11. Measured at output I O1 ; VREF = 20VP-P; F = 10kHz sinewave. 12. Measured at output I O1 ; VREF = 20VP-P; F = 1kHz sinewave. 0.008 0.006 0.004 0.002 0.000 0.010 10 2345 Warm–Up Time(Minutes) Parameter Change (% FSR)

either positive or negative polarity. Pin 20 — MSB LATCH — MSB Latch control. logic 1 allows data to update DAC directly. Pin 12 — DB1 — Data Bit 1 (MSB). Pin 13 — VREF In — Voltage Reference Input. Pin 14 — RFB — Feedback Resistor. Pin 15 — IOUT2 — Current Output. Pin 16 — IOUT1 — Inverted Current Output. Pin 17 — VDD — +15V Power Supply. Pin 19 — LSB LATCH — LSB Latch control. hermetic 24-pin ceramic or molded plastic. Figure 1. Unipolar Operation

Table 1. Unipolar Transfer Function affects the glitch performance. detail the low impedance guard track layout. offset voltage temperature coefficients. the choice of resistors R and 2R (see figure 2). Figure 2. Bipolar Operation Table 2. Bipolar Transfer Function

SIGNAL PROCESSING EXCELLENCE 187 DATA LATCH OUTPUT VALID DATA VALID DATA t1 t1 t2 t2 t1 = Data Setup Time (≤80ns) t2 = Strobe Width (≤80ns) t3 = Settling Time (2µs typical) Figure 6. Timing

Ordering Information

0°C to +70°C: -55°C to +125°C, MIL-STD-883C Screened:

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