SP8481 SIPEX | Alldatasheet
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DESCRIPTION… The SP8481 Series are complete monolithic data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter in 32–pin packages. Linearity errors of ±0.5 and ±1.0 LSB, and Differential Non-linearity to 12-bits is guaranteed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9µs maximum; A/D conversion time is 8.1µs maximum. CONTROL LOGIC ADD. LATCH MULTIPLEXER 8–BIT/4–BIT NIBBLE OUTPUT CLOCK REFERENCE 12-BIT A/D CONVERTER MUX DECODE I Complete Monolithic 8-Channel, 12-Bit DAS I 100kHz Throughput I 16-Bit Microprocessor Bus Interface I Latched MUX Address I All-channel Deselect I 8/4-Bit Nibble Output I No Missing Codes to 12-Bits I 32-Pin Packages I 200mW Max Power Dissipation * Formerly part of the SP410 Series. SP8481 Series* Monolithic, 12–Bit Data Acquisition System
(TA= 25°C and nominal supply voltages unless otherwise noted) MIN. TYP. MAX. UNIT CONDITIONS ANALOG INPUTS Input Voltage Range 0 to +5 V Multiplexer Inputs Configuration Single-ended Input Impedance ON Channel 109 Ω Parallel with 30pF OFF Channel 1010 Ω Parallel with 5pF Input Bias Current Per Channel ±10 nA 25°C ±250 nA –55°C to +125°C Crosstalk OFF to ON Channel –90 dB 10kHz, 0V to +5VPk–to–pk –80 dB 50kHz, 0V to +5VPk–to–pk –70 dB 100kHz, 0V to +5VPk–to–pk ACCURACY Resolution Bits Linearity Error –K, –B ±0.5 LSB –J, –A LSB Differential Non-Linearity –K, –B LSB –J, –A LSB Offset Error LSB Adjustable to zero Gain Error ±0.3 %FSR Adjustable to zero No Missing Codes –K, –B Guaranteed TRANSFER CHARACTERISTICS Throughput Rate 100 kHz MUX Settling/Acquisition 1.9 µs A/D Conversion 8.1 µs STABILITY Linearity ±0.5 ±2.5 ppm/°C Offset ±25 ppm/°C Gain ±10 ±50 ppm/°C DIGITAL INPUTS Capacitance pF Logic Levels VIH +2.4 +5.5 V VIL –0.5 +0.8 V IIH µA IIL µA
SPECIFICATIONS (continued) (TA= 25°C and nominal supply voltages unless otherwise noted) MIN. TYP. MAX. UNIT CONDITIONS DIGITAL OUTPUTS Capacitance pF Logic Levels VOH +2.4 V IOH ≤ 500µA VOL +0.4 V IOL ≤ 1.6mA Leakage Current ±40 µA High impedance, data bits only Data Output Offset Binary POWER REQUIREMENTS VLOGIC +4.5 +5.5 V ILOGIC 0.8 mA VCC +11.4 +16.5 V ICC mA Power Dissipation 140 200 mW ENVIRONMENTAL Operating Temperature Commercial; –J, –K +70 Industrial; –A, –B –40 +85 Storage Temperature –65 +150
Table 1. Multiplexer Truth Table Table 2. Control Truth Table
FEATURES… The SP8481 Series are complete data acquisi- tion systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D con- verter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V uni- polar full scale inputs. Output data is formatted as an 8-bit/4-bit nibble. Linearity errors of ±0.5 and ±1.0 LSB, and Differential Non-linearity to 12-bits is guaran- teed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9µs maximum; A/D conversion time is 8.1µs maxi- mum. Versions of the SP8481 Series are available in 32-pin plastic DIP or SOIC packages. Operating temperature ranges are 0°C to +70°C commer- cial and -40°C to +85°C industrial. CIRCUIT OPERATION… The SP8481 is a complete 8-channel data acqui- sition system (DAS), with on-board multiplexer, voltage reference, sample–and–hold, clock and tri–state outputs. The digital control architecture is very similar to the industry-standard 574-type A/D, and uses identical control lines and digital states. The multiplexer for the SP8481 is identical in operation to many discrete devices available today, except that it has been integrated into the single-chip DAS. The appropriate channel is selected using the MUX address lines MA0, MA1, and MA2 per the truth table. The selected analog input is fed through to the ADC. The input impedance into any MUX channel will be on the order to 109 ohms, since it is connected to the integral sampling structure of the capacitor DAC. Crosstalk is kept to -85dB at 0V to 5Vp-p over an input frequency range of 10kHz to 50kHz. When the control section of the SP8481 initiates a conversion command the internal clock is enabled, and the successive approximation reg- ister (SAR) is reset to all zeros. Once the conver- sion has been started it cannot be stopped or restarted. Data is not available at the output buffers until the conversion has been completed. The SAR, timed by the clock, sequences through the conversion cycle and returns an end–of– convert flag to the control section of the ADC. The clock is then disabled by the control section, which puts the STATUS output line low. The control section is enabled to allow the data to be read by external command (R/C). Multiplexer Control and Inputs On the SP8481 the multiplexer inputs are latched with LATCH. The address line latches MA0, MA1 and MA2 select the appropriate analog input channel. When low, the LATCH line re- tains the last MUX address data, and therefore the previously addressed MUX channel. All channels may be deselected by bringing the MAEN control line to a logic “1”. When this control function is used, the analog input will be connected to pin 8 or analog ground. Since the MUX address latches are controlled by the LATCH and MAEN control lines, MUX channel select data need not be held by the bus for any minimum period after the conversion has been initiated. However it is advisable that the MUX not be changed at all during the full 10µs conversion time due to capacitive coupling ef- fects of digital edges through the silicon. The SP8481 multiplexer inputs have been de- signed to allow substantial overvoltage condi- tions to occur without any damage. The inputs are diode-clamped and further protected with a 200Ω series resistor. As a result, momentary (10 seconds) input voltages can be as low as -16.5V or as high as +31.5V with no change or degrada- tion in multiplexer performance or crosstalk. This feature allows the output voltage of an externally connected op amp to swing to ±15V supply levels with no multiplexer damage. Com- plicated power-up sequencing is not required to protect the SP8481. The multiplexer inputs may be damaged, however, if the inputs are allowed to either source or sink greater than 100mA. Initiating a Conversion The SP8481 was designed to require a minimum of control to perform a 12-bit conversion. The control input used is R/C which tri-states the
Figure 3. Low Pulse for R/C Timing
Figure 4. Convert Mode Timing
Figure 5. Read Mode Timing
ORDERING INFORMATION
12-Bit Data Acquisition System, Latched Multiplexer Address, 8-Bit/4-Bit Data Output: Commercial (0°C to +70°C): Integral Non–Linearity Package Industrial (-40°C to +85°C): Integral Non–Linearity Package
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