SP8480 SIPEX | Alldatasheet
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8–BIT/4–BIT NIBBLE OUTPUT CLOCKREFERENCE 12-BIT A/D CONVERTER MUX DECODE DESCRIPTION… The SP8480 Series are complete monolithic data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter in 28–pin plastic DIP or SOIC packages. Linearity errors of ±0.5 and ±1.0 LSB, and Differential Non-linearity to 12-bits are guaranteed, with no missing codes over temperature. Multiplexer settling plus acquisition time is 1.9µs maximum; A/D conversion time is 8.1µs maximum. n Complete Monolithic 8-Channel, 12-Bit DAS n 100kHz Throughput n 16-Bit Microprocessor Bus Interface n MUX Inputs Overvoltage Protected n Parallel 8/4-Bit Nibble Output n Tri-State Latched Output n No Missing Codes to 12-Bits n 28-pin SOIC and PDIP package n 200mW Max Power Dissipation (140mw Typ.) *Formerly part of the SP410 Series. SP8480* Monolithic, 12–Bit Data Acquisition System
LOGIC +0.5V CC +0.5V SPECIFICATIONS (TA = 25°C and nominal supply voltages unless otherwise noted) MIN. TYP. MAX. UNIT CONDITIONS ANALOG INPUTS Input Voltage Range 0 to +5 V Multiplexer Inputs 8 Configuration Single-ended Input Impedance ON Channel 10 9 Ω Parallel with 30pF OFF Channel 10 10 Ω Parallel with 5pF Input Bias Current Per Channel ±10 nA 25 °C ±250 nA -55 °C to +125°C Crosstalk OFF to ON Channel -90 dB 10kHz, 0V to +5V pk-to-pk -80 dB 50kHz, 0V to +5V pk-to-pk -70 dB 100kHz, 0V to +5V pk-to-pk ACCURACY Resolution 12 Bits Linearity Error –K, –B ±0.5 LSB –J, –A ±1 LSB Differential Non-Linearity –K, –B ±1 LSB –J, –A ±2 LSB Offset Error ±2 LSB Adjustable to zero Gain Error ±0.3 %FSR Adjustable to zero No Missing Codes –K, –B Guaranteed TRANSFER CHARACTERISTICS Throughput Rate 100 kHz MUX Settling/Acquisition 1.9 µs A/D Conversion 8.1 µs STABILITY Linearity ±0.5 ±2.5 ppm/ °C Offset ±5 ±25 ppm/ °C Gain ±10 ±50 ppm/ °C DIGITAL INPUTS Capacitance 5 pF Logic Levels VIH +2.4 +5.5 V VIL -0.5 +0.8 V IIH ±5 µA IIL ±5 µA
(TA = 25°C and nominal supply voltages unless otherwise noted) MIN. TYP. MAX. UNIT CONDITIONS DIGITAL OUTPUTS Capacitance 5 pF Logic Levels VOH +2.4 V I OH ≤ 500µA VOL +0.4 V I OL ≤ 1.6mA Leakage Current ± 40 µA High impedance, data bits only Data Output Offset Binary POWER REQUIREMENTS VLOGIC +4.5 +5.5 V ILOGIC 0.8 4 mA VCC +11.4 +16.5 V ICC 91 2 m A Power Dissipation 140 200 mW ENVIRONMENTAL Operating Temperature Commercial; –J, –K 0 +70 °C Industrial; –A, –B -40 +85 °C Storage Temperature -65 +150 °C
PIN FUNCTION… A 0 — Device Address — Logic low enables 8 MSB read; logic high enables 4 LSB read STATUS — Identifies valid data output; goes to logic high during conversion; goes to logic low when conversion is completed and data is valid R/C — Read/Convert — Initiates conversion on the high-to-low transition; logic low disconnects data bus; logic high initiates read CE — Chip Enable — Logic low disables read or convert; logic high enables read or convert MA 0, MA1, MA2 — MUX Address 0, 1 & 2 — Selects analog input channels CH0 through CH7 DB 0 through DB11 — Data Outputs — Logic high is binary true; logic low binary false 23456789 1 0 1 1 1 2 1 3 1 4 151723 22 21 20 19 182428 27 26 25 STATUS DB11/DB3 DB10/DB2 DB9/DB1 DB8/DB0 (LSB) DB7 DB6 DB5 DB4 MA2 MA1 MA0 DIG. GND. V LOGICA0 R/C VCC OFFSET ADJ. GAIN ADJ. ANA. GND. ANA. IN. CH0 ANA. IN. CH1 ANA. IN. CH2 ANA. IN. CH3 ANA. IN. CH4 ANA. IN. CH5 ANA. IN. CH6 ANA. IN. CH7 CONTROL LOGIC CLOCK 12-BIT ADC 8-CHANNEL MULTIPLEXER DECODE REF MULTIPLEXER TRUTH TABLE MA 2 MA 1 MA 0 OPERATION
000 C H O Selected
001 C H 1 Selected
010 C H 2 Selected
011 C H 3 Selected
100 C H 4 Selected
101 C H 5 Selected
110 C H 6 Selected
111 C H 7 Selected
X H ->L Start Conversion 0 1 Enable 8 MSBs 1 1 Enable 4 LSBs
FEATURES… The SP8480 Series are complete data acquisi- tion systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D con- verter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V uni- polar full scale inputs. Output data is formatted as an 8-bit/4-bit nibble. Linearity errors of ±0.5 and ±1.0 LSB, and Differential Non-linearity to 12-bits is guaran- teed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9µs maximum; A/D conversion time is 8.1µs maxi- mum. Versions of the SP8480 are available in 28-pin plastic DIP, ceramic DIP or SOIC packages. Operating temperature ranges are 0°C to +70°C commercial and -40°C to +85°C industrial. The SAR, timed by the clock, sequences through the conversion cycle and returns an end–of– convert flag to the control section of the ADC. The clock is then disabled by the control section, which puts the STATUS output line low. The control section is enabled to allow the data to be read by external command (R/C). Multiplexer Control and Inputs On the SP8480 the multiplexer is independent of any other control line. The address line latches MA 0, MA1 and MA2 are hard-wired in an enabled mode in the SP8480 , and are therefore transpar- ent. Data setup time for these inputs is 50ns. If a device is required with additional MUX con- trol, please refer to the Sipex SP8481 DAS. Since the latches are enabled, MUX channel select data need not be held by the bus for a minimum period of 3.0µs after the conversion has been initiated. This is the time required for the MUX and Sample and Hold to settle. How- ever it is advisable that the MUX not be changed at all during the full 10µs conversion time due to capacitive coupling effects of digital edges through the silicon. The SP8480 multiplexer inputs have been de- signed to allow substantial overvoltage condi- tions to occur without any damage. The inputs are diode-clamped and further protected with a 200Ω series resistor. As a result, momentary (10 seconds) input voltages can be as low as -16.5V or as high as +31.5V with no change or degrada- tion in multiplexer performance or crosstalk. This feature allows the output voltage of an externally connected op amp to swing to ±15V supply levels with no multiplexer damage. Com- plicated power-up sequencing is not required to protect the SP8480 . The multiplexer inputs may be damaged, however, if the inputs are allowed to either source or sink greater than 100mA. Initiating A Conversion Please refer to Figure 4. The SP8480 was de- signed to require a minimum of control to per- form a 12-bit conversion. The control input used is R/C which tri-states the outputs and starts the conversion when low. The STATUS line indi- cates when a conversion is in process and when it is complete. The A 0 control input is used to CIRCUIT OPERATION… The SP8480 is a complete 8-channel data acqui- sition systems (DAS), with on-board multi- plexer, voltage reference, sample-and-hold, clock and tri-state outputs. The digital control archi- tecture is very similar to the industry-standard 574-type A/D, and uses identical control lines and digital states. The multiplexer for the SP8480 is identical in operation to many discrete devices available today, except that it has been integrated into the single-chip DAS. The appropriate channel is selected using the MUX address lines MA MA 1, and MA2 per the truth table. The selected analog input is fed through to the ADC. The input impedance into any MUX channel will be on the order to 10 9 ohms, since it is connected to the integral sampling structure of the capacitor DAC. Crosstalk is kept to -85dB at 0V to 5V p-p over an input frequency range of 10kHz to 50kHz. When the internal control section of the SP8480 initiates a conversion command the internal clock is enabled, and the successive approximation register (SAR) is reset to all zeros. Once the conversion has been started it cannot be stopped or restarted. Data is not available at the output buffers until the conversion has been completed.
Figure 3. Low Pulse for R/C Timing
Figure 4. Convert Mode Timing
Figure 5. Read Mode Timing
ORDERING INFORMATION
12-Bit Data Acquisition System with 12-Bit Parallel Data Output: Commercial (0°C to +70°C): Non–Linearity Package Industrial (-40°C to +85°C): Non–Linearity Package
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