SP8024 SIPEX | Alldatasheet
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Technical content
Rev. 6/02/03 SP8024, 25, 26 200V/ µs Integrated APC Amplifier © Copyright 2003 Sipex Corporation 200V/µs Integrated APC Amplifier with Gain Adjust & Differential Output SP8024/8025/8026 ■ Slew Rate of 200V/µs ■ Fast Settling Time - 10ns ■ Gain Switch ■ 2V Output Swing ■ Low Offset Voltage: < 10mV ■ Low Offset Drift: < 20µV/°C ■ 12dB External Gain Adjust Range
DESCRIPTION
The SP8024, SP8025, and SP8026 are high-speed, differential output APC amplifiers that integrate the photodiode and adjustable gain block on one chip. This allows the user to control the laser power of the system in high-speed DVDRW, DVDRAM and CDRW systems. The wide 2V output swing also allows better system performance. GAIN GND VCC VOUT + SP8024/25/26
8 Pin COB
(Flexible Flat Cable) 850 Rf1 Rf2 850 2463 2463 Advanced
FEATURES
Rev. 6/02/03 SP8024, 25, 26 200V/ µs Integrated APC Amplifier © Copyright 2003 Sipex Corporation These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ELECTRICAL SPECIFICATIONS Unless otherwise noted: VCC = +5.0V, CLOAD = 50pF to GND, RGAIN =262Ω and RLOAD = 1kΩ. -20°C ≤TA≤ +85°C, nominal gain PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage 4.5 5 5.5 V Nominal Output Sensitivity Any Select Mode SP8024 ODB Gain 1000 V/W SP8025 2000 SP8026 3000 Input Optical Power Required Any Select Mode to Produce 2 V Output Swing ODB Gain SP8024 2 mW SP8025 1 SP8026 0.666 Full Scale Output Voltage Swing(Vp-p) 1.9 2 V Output Common Mode Voltage V CC /2 V Differential Output Offset Voltage -10 10 mV Differential Output Offset Voltage Drift -20 20 µV/°C Differential Output Noise BW: 1kHz to 1MHz 1 2 mV Differential Output Noise BW: 1kHz to 100MHz 3 5 mV Differential Output Slew Rate 200 250 V/ µs Differential Output Settling Time 10 15 ns to 1% of Final Value, 2V Step Output Overshoot, 2V step 5 % Bandwidth (-3db) 65 100 MHz PSRR 4.5V < V CC < 5.5V 60 65 dB Power Supply Current T A = 25°C2 0 m A Full Temp No Load 25 Gain Adjust Range < 5% Overshoot, -9 3 dB 150 < RGAIN < 1350Ω Input Voltage Vlow(TTL Level) 0.8 V Vhigh(TTL Level) 2.2 V TJA, 3mm x 3.5mm Package 75 °C/W ABSOLUTE MAXIMUM RATINGS
Rev. 6/02/03 SP8024, 25, 26 200V/ µs Integrated APC Amplifier © Copyright 2003 Sipex Corporation PIN DESCRIPTION PIN NUMBER NAME FUNCTION 1V CC Supply Voltage
2 GAIN Gain Select
3R COM Common connection point for RGAIN 1 and RGAIN 2
4 GND Power Ground
The SP8024/25/26 APC circuits have an inte- grated photo detector and are designed with three nominal sensitivities of 1mV/µW, 2mV/ µW and 3mV/µW respectively. Each part’s sen- sitivity can also be adjusted continuously and independently for two different gain modes via two external resistors over a range of 12dB. The two gain modes are controlled by a TTL com- patible logic input. This logic input also normal- izes the internal photo detector’s responsivity for 650nm and 780nm laser wavelengths. The logic pin selects between the two external gain setting resistors to allow independent control and settings for the two gain functions. The 8024 APC family uses two stages of gain to optimize for speed and offset. The two stages consist of a differential trans-impedance ampli- fier (TIA), and a differential gain adjust ampli- fier. TIA The first stage is a differential trans-impedance amplifier (TIA) for converting the photo detec- tor output current to a balanced differential voltage. This topology allows for fast settling of the photo detector and also cancels offset ef- fects. The TIA has no external components. Variable Gain Amplifier This stage is used to vary the gain of the system. It provides selection for two different gain set- ting resistors, R GAIN1 and RGAIN2 , at pins 5 and 6 via internal MOSFET switches S1 and S2. The logic input at pin 2 controls the selection of the two external gain set resistors. Table 1: Gain Select Logic Truth Table Gain Sensitivity Select Rexternal, Gain (mV/ µW) Pin 2 Pin 3 to: Factor (x) R G1 = RG2 = 262Ω SP8024 SP8025 SP8026 0 or Open R G1 - Pin 5 6.25 1 2 3 1R G2 - Pin 6 6.25 1 2 3 The gain of this balanced amplifier topology is given by: GAIN = 1 + Rf1 + Rf2 R EXT where RGAIN is external and Rf1 = Rf2 = 850Ω in feedback. The nominal gain is defined as 6.25. THEORY OF OPERATION
tance at pins 5 and 6 should be kept below 1pF. capacitive load plus inductance and resistance. Figure 1. System Gain versus Gain Set Resisitor
paths for power and ground and output traces. Figure 2. Test and Evaluation PCB Layout for COB 8 Lead Package talum. The layout of the PCB is pictured here. traces associated with the gain-setting resistors.
Figure 3. Test and Evaluation Schematic
Rev. 6/02/03 SP8024, 25, 26 200V/ µs Integrated APC Amplifier © Copyright 2003 Sipex Corporation H 0.090 0.600 D b e L BOTTOM VIEWTO P VIEW SIDE VIEW 5° (2X) E A C FS B PIN SIDE VIEW DETECTOR SIZE 0.35mm Detector Area 0.70mm (3.5mm x 3.0mm) DIMENSIONS in mm Minimum/Maximum 8–PIN COB A B b c D E e H L F S 0.90/1.10 .127/.33 0.30/0.50 0.50 nom 2.90/3.10 3.00/3.20 0.75 nom 3.40/3.60 0.40/0.60 0.28/0.48 0.075/0.275 PACKAGE : 8 PIN COB
Rev. 6/02/03 SP8024, 25, 26 200V/ µs Integrated APC Amplifier © Copyright 2003 Sipex Corporation
ORDERING INFORMATION
Part Number Temperature Range Package Type ANALOG EXCELLENCE Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Corporation Sipex Corporation Headquarters and Sales Office
233 South Hillview Drive
Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office
22 Linnell Circle
Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com