SP690RCP

SP690T SIPEX | Alldatasheet

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SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation SP690T/S/R, SP802T/S/R, SP804T/S/R, and SP805T/S/R 3.0V/3.3V Low Power Microprocessor Supervisory with Battery Switch-Over The SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices are a family of microprocessor (µP) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in µP and digital systems. The series will significantly improve system reliability and operational efficiency when compared to discrete solutions. The features of the SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices include a watchdog timer, a µP reset and backup- battery switchover, and power-failure warning; a complete µP monitoring and watchdog solution. The series is ideal for 3.0V or 3.3V applications in portable electronics, computers, controllers, and intelligent instruments and is a solid match for designs where it is critical to monitor the power supply to the µP and it’s related digital components. Refer to Sipex's SP690A/692A/802L/802M/805L/805M series for similar devices designed for +5V systems. n RESET and RESET Outputs n Reset asserted down to V CC = 1V n Reset Time Delay - 200ms n Watchdog Timer - 1.6 sec timeout n 40µA Maximum V CC Supply Current n 1µA Maximum Battery Supply Current n Power Switching 50mA Output in VCC Mode (1.5Ω ) 10mA Output in Battery Mode (15Ω ) n Battery Can Exceed VCC in Normal Operation n Precision Voltage Monitor for Power-Fail or Low-Battery Warning n Available in 8 pin SO and DIP packages n Pin Compatible Upgrades to MAX690T/S/R, MAX802T/S/R, MAX804T/S/R, MAX805T/S/R

DESCRIPTION

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SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. V Continuous Input Current: V Continuous Output Current: V Power Dissipation per Package: SPECIFICATIONS TA = TMIN to TMAX unless otherwise noted. Typical values taken at TAMB = +25O C. SRETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC ,egnaRegatloVgnitarepO0 .15 .5s tloV V CC Vro YRETTAB ,E TON1 V CC I,tnerruCylppuS YLPPUS 520 4 µA Ignidulcxe TUO V CC yrettaBnitnerruCylppuS edoMpukcaB 020 4 µA V CC V,V0.2= YRETTAB ,V3.2= Ignidulcxe TUO V YRETTAB nitnerruCylppuS ,edoMynAE TON2 4.01 µA Ignidulcxe TUO V YRETTAB ETON,tnerruCegakaeL3 100.05 .0 µA V YRETTAB ETON,tnerruCegakaeL4 1 .0- 20.0 µA V>V3.3 CC V> YRETTAB V2.0+ V,egatloVtuptuO TUO V CC 30.0- V CC 3.0- V CC 5100.0- V CC 5700.0- V CC 570.0- V CC 3000.0- V Am5=I I TUO Am05= I TUO 052= µ V,A CC V5.2> V TUO edoMpukcaB-yrettaBniV YRETTAB 20.0-V YRETTAB 5400.0- V YRETTAB 810.0- V YRETTAB 51.0- V I TUO V,Aµ052= YRETTAB V3.2= I TUO V,Am1= YRETTAB V3.2= I TUO BV,Am01= YRETTA V3.3= ,dlohserhThctiwSyrettaB V CC gnillaf 560.0 03.2 520.0 04.20 5.2 V V YRETTAB V- CC V, WS V> CC 5ETON,V57.1> V YRETTAB V> CC 6ETON, ,dlohserhThctiwSyrettaB V CC 7ETON,gnisir V teseRehtotlacitnedieraseulaV VtaseulavdlohserhT CC gnisir

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation SRETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC V,dlohserhTteseR TSR 8ETON 00.3 00.3 58.2 58.2 55.2 55.2 570.3 580.3 529.2 539.2 526.2 536.2 51.3 71.3 00.3 20.3 07.2 27.2 V V,T508/T096PS CC gnillaf V,T508/T096PS CC gnisir V,S508/S096PS CC gnillaf V,S508/S096PS CC gnisir V,R508/R096PS CC gnillaf V,R508/R096PS CC gnisir 00.3 00.3 88.2 88.2 95.2 95.2 570.3 580.3 529.2 539.2 526.2 536.2 21.3 41.3 00.3 20.3 07.2 27.2 V V,T408/T208PS CC gnillaf V,T408/T208PS CC gnisir V,S408/S208PS CC gnillaf V,S408/S208PS CC gnisir V,R408/R208PS CC gnillaf V,R408/R208PS CC gnisir teseRt ,doirePtuoemiT PW 0410 020 82s m V,egatloVtuptuOOFP,TESER HO V CC 3.0-V CC 51.0-V I ECRUOS Aµ03= V,egatloVtuptuOOFP,TESER LO 60.00 3.0V I KNIS erehw_208/_096PS,Am2.1= V CC V= TSR muminim V,egatloVtuptuOOFP,TESER LO 31.00 3.0V V YRETTAB V,V0= CC I,V0.1= KNIS Aµ04= V,egatloVtuptuOTESER LO 60.00 3.0V I KNIS erehw_508/_408PS,Am2.1= V CC V= TSR mumixam ,tnerruCegakaeLtuptuOTESER 11ETON 1-1 - µA V YRETTAB V,V0= CC V= TSR ,muminim V TESER VroV0= CC I,tnerruCDNGottrohStuptuO SO , TESERdnaOFP 0810 05 µA V CC V,V3.3= HO V0= t,tuoemiTgodhctaW DW 21.10 6.14 2.2s V CC V6.3< htdiWesluPIDW0 020 4s n dlohserhTtupnIIDW V HI V LI Vx3.0 CC Vx7.0 CC V tnerruCtupnIIDW1 -1 0.01 µA V<V0 CC V5.5< dlohserhTtupnIIFP0 02.1 522.1 52.1 52.1 003.1 572.1 V V,_508/_096PS CC < V,V6.3 IFP gnillaf V,_408/_208PS CC < V,V6.3 IFP gnillaf tnerruCtupnIIFP5 2-1 0.05 2A n V,siseretsyHIFP HFP 010 2V mV ,gnisirIFP CC < V6.3 SPECIFICATIONS (continued) TA = TMIN to TMAX unless otherwise noted. Typical values taken at TAMB = +25O C.

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) TA = TMIN to TMAX unless otherwise noted. Typical values taken at TAMB = +25O C. NOTE 1: The following are tested at VBATT = 3.6V and VCC = 5.5V: VCC supply current, watchdog functionality, logic input leakage, PFI functionality, and the RESET and RESET states. The state of RESET or RESET and PFO is tested at V CC = VCC (min). NOTE 2: Tested VBATT = 3.6V, VCC = 3.5V and 0V. NOTE 3: Leakage current into the battery is tested under the following worst-case conditions: VCC NOTE 4: "-" equals the battery-charging current, "+" equals the battery-discharging current. NOTE 5: When VSW > VCC > VBATT , VOUT remains connected to VCC until VCC drops below VBATT . The V CC -to-VBATT comparator has a small 25mV typical hysteresis to prevent oscillation. NOTE 6: When VBATT > VCC > VSW , VOUT remains connected to VCC until VCC drops below the battery switch threshold, VSW . NOTE 7: VOUT switches from VBATT to VCC when VCC rises above the reset threshold, independent of V BATT . Switchover back to VCC occurs at the exact voltage that causes RESET to go HIGH (on the SP804_ and SP805_ RESET goes LOW). Switchover occurs 200ms prior to reset. NOTE 8: The reset threshold tolerance is wider for V CC rising than for VCC falling to accommodate the 10mV typical hysteresis, which prevents internal oscillation. NOTE 9: SP690_ and SP802_ devices only. NOTE 10: SP804_ and SP805_ devices only. NOTE 11: The leakage current into or out of the RESET pin is tested with RESET asserted (RESET output high impedance).

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation INTERNAL BLOCK DIAGRAM 1.25V BATTERY SWITCHOVER CIRCUIT PFI WATCHDOG TIMER RESET GENERATOR VCC BATTERY SWITCHOVER COMPARATOR RESET COMPARATOR 1.25V 1.25V WDI VBATT PFO RESET / RESET* SP690T/S/R SP802T/S/R SP804T/S/R SP805T/S/R *SP804T/S/R and SP805T/S/R only POWER-FAIL COMPARATOR VOUT GND 3

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation PIN ASSIGNMENTS Pin 1 —V OUT — Output Supply Voltage for CMOS RAM. When V CC is above the reset threshold, VOUT connects to VCC through a P-channel MOSFET switch. When V CC falls below the VSW and V BATTERY , VBATTERY connects to VOUT . Connect to VCC if no battery is used. Pin 2 — VCC — +5V Supply Input Pin 3 — GND — Ground reference for all signals Pin 4 — PFI — Power-Fail Comparator Input. When PFI is less than 1.25V or when VCC falls below the VSW , PFO goes LOW, otherwise PFO remains HIGH. Connect to GND if unused. Pin 5 — PFO — Power-Fail Comparator Output. Leave open if unused. Pin 6 — WDI — Watchdog Input. If WDI remains HIGH or LOW for 1.6 seconds, the internal watchdog timer triggers a reset. The internal watchdog timer clears when reset is asserted or WDI sees a rising or falling edge. The watchdog function cannot be disabled. Pin 7 for SP690_/802_ only — Active-LOW Reset Output. — Whenever RESET is triggered by a watchdog timeout, it goes LOW for 200ms. It stays LOW whenever V CC is below the reset threshold and re- mains LOW for 200ms after VCC rises above the reset threshold or when the watchdog triggers a reset. Pin 7 for SP804_/805_ only — Active-HIGH Open-Drain Reset Output. — The inverse operation of RESET. Pin 8 — VBATTERY — Backup-Battery Input. When V CC falls below VSW and VBATTERY , V OUT switchesfrom VCC to VBATTERY . When V CC rises above the reset threshold, V OUT reconnects to VCC . VBATTERY may exceed VCC . Connect to VCC if no battery is used. VOUT VCC GND PFI VBATTERY RESET / RESET* WDI PFO 4 5 *SP804T/S/R and SP805T/S/R only SP690T/S/R SP802T/S/R SP804T/S/R SP805T/S/R PINOUT

Figure 19. Timing Diagram *SP804T/S/R and SP805T/S/R only; Reset externally pulled up to VCC .

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation The watchdog timer can also initiate a reset. Refer to the Watchdog Input section. The SP804T/S/R and SP805T/S/R active-HIGH RESET output is open drain and the inverse of the SP690T/S/R and SP802T/S/R RESET outputs. RESET is also triggered by a watchdog timeout. If WDI remains either high or low for a period that exceeds the watchdog timeout period (1.6 sec), RESET pulses low for 200mS. As long as RESET is asserted, the watchdog timer remains cleared. When RESET comes high, the watch- dog resumes timing and must be serviced within 1.6sec. If WDI is tied high or low, a RESET pulse is triggered every 1.8sec (t WD plus tRS ). Reset Threshold The SP690T and SP805T devices are designed for 3.3V systems with a ±5% power-supply tolerance and a 10% system tolerance. Except for watchdog faults, reset will not assert as long as the power supply remains above 3.15V (3.3V - 5%). Reset is guaranteed to assert before the power supply falls below 3.0V. The SP690S and SP805S devices are designed for 3.3V ±10% power supplies. Except for watchdog faults, they are guaranteed not to assert reset as long as the supply remains above 3.0V (3.3V - 10%). Reset is guaranteed to assert before the power supply fails below 2.85V CC - 14%). The SP690R and SP805R devices are optimized for monitoring 3.0V ±10% power supplies. Reset will not occur until VCC falls below 2.7V (3.0V - 10%), but is guaranteed to occur before the supply falls below 2.55V (3.0V - 15%). The SP802T/S/R and SP804T/S/R devices are respectively similar to the SP690T/S/R and SP805T/S/R devices with tightened reset and power-fail threshold tolerances. Watchdog Input The watchdog circuit monitors the µP's activity. If the µP does not toggle the watchdog input (WDI) within 1.6sec, a reset pulse is triggered. The internal 1.6sec timer is cleared by either a reset pulse or by a transition (LOW-to-HIGH or HIGH-to-LOW) at WDI. If WDI is tied HIGH or LOW, a RESET pulse is triggered every 1.8sec (t WD plus tRS ). As long as reset is asserted, the timer remains cleared and does not count. As soon as reset is de-asserted, the timer starts counting. Unlike the 5V SP690A series, the watchdog function cannot be disabled. Power-Fail Comparator The power-fail comparator can be used as an under-voltage detector to signal the failing of a power supply (it is completely separate from the rest of the circuitry and does not need to be dedicated to this function). The PFI input is compared to an internal 1.25V. If PFI is less than V PFT , PFO goes low. The power-fail comparator turns off and PFO goes LOW when V CC falls below VSW on power-down. The power-fail comparator turns on as VCC crosses VSW on power-up. If the comparator is not used, connect PFI to ground and leave PFO unconnected. Backup-Battery Switchover In the event of a brownout or power failure, it may be necessary to preserve the contents of RAM. With a backup battery installed at V BATTERY , the devices automatically switch RAM to backup power when VCC fails. This family of µP supervisors (designed for 3.3V and 3V systems) doesn't always connect V BATTERY to VOUT when V BATTERY is greater than VCC . VBATTERY connects to VOUT (through a 15Ω switch) when VCC is below VSW and V BATTERY is greater than VCC .

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation D ALTERNATE END PINS (BOTH ENDS) D1 = 0.005" min. (0.127 min.) E PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) DIMENSIONS (Inches) Minimum/Maximum (mm) A = 0.210" max. (5.334 max). C ØL A1 = 0.015" min. (0.381min.) B e = 0.100 BSC (2.540 BSC) eA = 0.300 BSC (7.620 BSC) B C D E L Ø 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.735/0.775 (18.669/19.685) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°) 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.355/0.400 (9.017/10.160) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°) 22–PIN8–PIN 14–PIN 16–PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.145/1.155 (29.083/29.337) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°) 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.780/0.800 (19.812/20.320) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°) 18–PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.880/0.920 (22.352/23.368) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°) 20–PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.980/1.060 (24.892/26.924) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°)

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation D EH PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (NARROW) DIMENSIONS (Inches) Minimum/Maximum (mm) 8–PIN A Ø LBe h x 45° A B D E e H h L Ø 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249 0.014/0.019 (0.35/0.49) 0.189/0.197 (4.80/5.00) 0.150/0.157 (3.802/3.988)

0.050 BSC

(1.270 BSC) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) 14–PIN 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249) 0.013/0.020 (0.330/0.508) 0.337/0.344 (8.552/8.748) 0.150/0.157 (3.802/3.988) (1.270 BSC) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) 16–PIN 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249) 0.013/0.020 (0.330/0.508) 0.386/0.394 (9.802/10.000) 0.150/0.157 (3.802/3.988) (1.270 BSC) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°)

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation

ORDERING INFORMATION

Model Temperature Range Package Types Please consult the factory for pricing and availability on a Tape-On-Reel option.

SP690T/S/R DS/10 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Sipex Corporation Headquarters and Sales Office

22 Linnell Circle

Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office

233 South Hillview Drive

Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600