SP674A

HS574A SIPEX | Alldatasheet

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DESCRIPTION… The HS574A/SP674A Series are complete 12–bit successive–approximation A/D converters integrated on a single die with tri-state output latches, an internal reference, clock and a sample– hold. They feature 12–bit linearity over temperature, low power dissipation and fast conversion time. They are available in commercial and military temperature ranges. I Complete 12–bit A/D Converters with Sample– Hold, Reference, Clock and Tri–state Outputs I Low Power Dissipation — 110mW Maximum I 12–Bit Linearity Over Temperature I Fast Conversion time: 25µs Max (HS574A) 15µs Max (SP674A) I Monolithic Construction HS574A/SP674A 12–Bit Sampling A/D Converters STS DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND VLOGIC CS R/C CE VCC REF OUT AGND REF IN VEE BIP OFF 10V IN 20V IN NIBBLE A NIBBLE B NIBBLE C THREE–STATE BUFFERS AND CONTROL N/C 7.5K 15K 15K 7.5K 7.5K OFFSET/GAIN TRIM 12–BIT CAPACITANCE DAC COMP REF CONTROL LOGIC 12–BIT SAR OSC

(CE, CS, A0, 12/8, R/C) (REF IN, BIP OFF, 10VIN) Momentary short to VCC

• Inputs exceeding +30% or –30% of FS will cause erratic performance. CAUTION: ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed. SPECIFICATIONS (Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS RESOLUTION All models Bits ANALOG INPUTS Input Ranges Bipolar ±5, ±10 V Unipolar 0 to +10, 0 to +20 V Input Impedance

10 Volt Input

3.75 6.25 KΩ

20 Volt Input

KΩ DIGITAL INPUTS Logic Inputs CE, CS R/C, AO, 12/8 Logic 1 +2.4 +5.5 V Logic 0 –0.3 +0.8 V Current ±0.1 ±50 µA 0V to +5.5V Input Capacitance pF 12/8 Control Input Hardwire to VLOGIC or DIGITAL COMMON (SP574A only) DIGITAL OUTPUTS Logic Outputs DB11–DB0, STS Logic 1 +2.4 V ISOURCE ≤ 500µA Logic 0 +0.4 V ISINK ≤ 1.6mA Leakage (High Z State) ±40 µA Data bits only Capacitance pF Parallel Data Output Codes Unipolar Positive true binary Bipolar Positive true offset binary REFERENCE Internal 10.00 ±0.1 V Output Current mA Note 1 CONVERSION TIME HS574A 12–Bit Conversion µs 8–Bit Conversion µs SP674A 12–Bit Conversion µs 8–Bit Conversion 11.25 µs

SPECIFICATIONS (continued) (Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS ACCURACY Linearity Error @ 25°C –J, –S ±1.0 LSB @ 25°C and TMIN to TMAX –K, –L, –T, –U ±0.5 LSB @ 25°C and TMIN to TMAX Differential Linearity Error Note 2 –J, –S Bits @ 25°C Bits TMIN to TMAX –K, –L, –T, –U Bits @ 25°C Bits TMIN to TMAX Offset Note3 Unipolar LSB Bipolar –J, –S ±10 LSB –K, –L, –T, –U LSB Full Scale (Gain) Error % of full scale; TMIN to TMAX ±0.3 %FS Note 4 ±0.5 %FS No adjustment @ 25°C ±0.22 %FS With adjustment @ 25°C ±0.4 %FS No adjustment @ 25°C ±0.12 %FS With adjustment @ 25°C ±0.35 %FS No adjustment @ 25°C ±0.05 %FS With adjustment @ 25°C ±0.8 %FS No adjustment @ 25°C ±0.5 %FS With adjustment @ 25°C ±0.6 %FS No adjustment @ 25°C ±0.25 %FS With adjustment @ 25°C ±0.4 %FS No adjustment @ 25°C ±0.12 %FS With adjustment @ 25°C STABILITY Unipolar Offset ±10 ppm/°C TMIN to TMAX –K, –L, –S ppm/°C TMIN to TMAX –T, –U ±2.5 ppm/°C TMIN to TMAX Bipolar Offset –J, –S ±10 ppm/°C TMIN to TMAX –K, –L, –T ppm/°C TMIN to TMAX ±2.5 ppm/°C TMIN to TMAX Gain (Scale Factor) –J, –S ±50 ppm/°C TMIN to TMAX –K, –T ±25 ppm/°C TMIN to TMAX –L, –U ±10 ppm/°C TMIN to TMAX PSRR VLOGIC ±0.5 LSB +4.5V ≤ VLOGIC ≤ +5.5V VCC Note 5 –J, –S LSB –K, –L, –T, –U LSB POWER REQUIREMENTS VLOGIC +4.5 +5.5 V ILOGIC HS574A mA SP674A mA VCC +11.4 +16.5 V ICCHS574A mA SP674A mA

SPECIFICATIONS (continued) (Typical @ 25°C with VCC = +15V, VEE = 0V, VLOGIC = +5V unless otherwise noted) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS Power Dissipation HS574A 110 150 mW SP674A 110 150 mW ENVIRONMENTAL Operating Temperature Range –J, –K, –L +70 –S, –T, –U –55 +125 Storage Temperature Range –J, –K, –L –40 +85 –A, –S, –T, –U –65 +150 Notes: Available for external loads. External load should not change during conversion. When supplying an external load and operating on a +12V supply, a buffer amplifier must be provided for the reference output. Minimum resolution for which no missing codes are guaranteed. Externally adjustable to zero. See Calibration information. Fixed 50Ω resistor between REF OUT and REF IN. Specifications are identical for all models unless otherwise noted. PIN ASSIGNMENTS… PIN FUNCTION PIN FUNCTION VLOGIC STS DB11(MSB) CS DB10 DB9 R/C DB8 CE DB7 VCC DB6 REF OUT DB5 ANA GND(AC) DB4 REF IN DB3 N/C* DB2 BIP OFF DB1 10VIN DB0(LSB) 20VIN DIG. GND *HS574A – This pin is not connected to the device; it can be tied to –15V, ground, or left floating. *SP674A – This pin is not connected to the device; VEE is generated internally.

FEATURES… The HS574A/SP674A feature standard bipolar and unipolar input ranges of 10V and 20V. Input ranges are controlled by a bipolar offset pin and laser-trimmed for specified linearity, gain and offset accuracy. Power requirements are +5V and +12V to +15V with a maximum dissipation of 150mW at the specified voltages. Conversion times of 8µs, 10µs, 15µs and 25µs are available, as are units with 10, 25 or 50ppm/°C temperature coefficients for flexible matching to specific application requirements. The HS574A/SP674A are available in six prod- uct grades for each conversion time. The –J, –K and –L models are specified over 0˚C to + 70˚C commercial temperature range; the –S, –T and – U models are specified over the –55˚C to +125˚C military temperature range. Processing in accor- dance with MIL–STD–883C is also available. The HS574A/SP674A are packaged in a 28–pin CerDIP. Please consult the factory for other packaging options. the LSB at the beginning of the conversion cycle to provide an output voltage from the CDAC that is equal to the input signal voltage (which is divided by the input voltage divider network). The comparator determines whether the addition of each successively–weighted bit voltage causes the CDAC output voltage summation to be greater or less than the input voltage; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12– bit binary code which accurately represents the input signal to within ±1⁄2 LSB. The internal reference provides the voltage refer- ence to the CDAC with excellent stability over temperature and time. The reference is trimmed to 10.00 Volts ±1% and can supply up to 2mA to an external load in addition to that required to drive the reference input resistor (1mA) and offset resistor (1mA) when operating with ±15V supplies. If the HS574A/SP674A is used with ±12V supplies, or if external current must be supplied over the full temperature range, an external buffer amplifier is recommended. Any external load on the HS574A/SP674A reference must remain constant during conversion. The sample and hold is a default function by virtue of the CDAC architecture. Therefore the majority of the S/H specifications are included within the A/D specifications. Sample–and–Hold Function Although there is no sample-and-hold circuit in the classical sense, the sampling nature of the capacitive DAC makes the HS574A/SP674A appear to have a built in sample and hold. This sample and hold action substantially increases the usefulness of the HS574A/SP674A over that of similar competing devices. Note that even though the user may use an external sample and hold for very high fre- quency inputs, the internal sample and hold still provides a very useful isolation function. Once the internal sample is taken by the CDAC capaci- tance, the input of the HS574A/SP674A is dis- connected from the input. This prevents tran- sients occurring during conversion from being inflicted upon the attached buffer. All other 574/ 674 circuits will cause a transient load current on CIRCUIT OPERATION… The HS574A/SP674A are complete 12–bit ana- log-to-digital converters with integral voltage reference, comparator, successive–approxima- tion register (SAR), sample–and–hold, clock, output buffers and control circuitry. The high level of integration of the HS574A/SP674A means they require few external components. When the control section of the HS574A/SP674A initiates a conversion command, the clock is enabled and the successive–approximation reg- ister is reset to all zeros. Once the conversion cycle begins, it can not be stopped or re–started and data is not available from the output buffers. The SAR, timed by the clock, sequences through the conversion cycle and returns an end–of– convert flag to the control section of the ADC. The clock is then disabled by the control section, the output status goes low, and the control sec- tion is enabled to allow the data to be read by external command. The internal HS574A/SP674A 12–bit CDAC is sequenced by the SAR starting from the MSB to

0 VOLTS

may add error to the conversion itself. throughput with the user's existing components. Figure 3. Sample–and–Hold Function Figure 1. Aperture Uncertainty ture delay” of this internal sample and hold. ±1.1µsecs between units and over temperatures. the HS574A/SP674A in a unipolar input mode. Figure 2. Equivalent SP574A Input Circuit

0 TO 10V

0 TO 20V

Figure 4. Unipolar Input Connections Figure 5. Bipolar Input Connections must be considered for correct operation.

Table 1. SPx74A Control Input Truth Table two or all three may be dynamically controlled. diagram is shown in Figure 8. high only when a conversion is in progress. conversion (8–versus 12–bits). pin 14 for the 0V to 20V range. by a 50Ω, 1% metal film resistor. the ±5V range or –9.9976V for the ±10V range. for the ±5 range or +9.9927V for the ±10V range. 20.48 (for an LSB of 5.0mV) is more convenient. 200Ω fixed resistor in series with pin 14.

bits (A0 high) or continues for 12–bits (A0 low). indicating a conversion is in progress. A0 is pulled low, the 8 MSB’s are enabled only. tDD and tHS before STS goes low. Figure 7. Interfacing SPx74A to 8–Bit Interface Bus

Typical @ 25˚C, VCC = +15V or +10V, VLOGIC = +5V, VEE = 0V, unless otherwise specified. Parameters guaranteed by design and sample tested. Parameters 100% tested @ 25˚C on special orders. Figure 8. Convert Mode Timing

Typical @ 25˚C, VCC = +15V or +12V, VLOGIC = +5V, VEE = 0V, unless otherwise specified. Parameters guaranteed by design and sample tested. Parameters 100% tested @ 25˚C on special orders. Figure 11. Read Mode Timing

ORDERING INFORMATION

25µs Conversion Time 15µs Conversion Time * MIL–STD–883C processing. NOTE: Electrical specifications for –AA, –AB and –AC grades are the same as –AJ, –AK, and –AL models respectively, with the exception of extended operating temperature range performance from –40°C to +85°C. Please consult the factory for other packaging options.