SP6652 SIPEX | Alldatasheet
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Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration SP6652
FEATURES
■ 1A Output Current ■ 1.2MHz Constant Frequency Operation ■ 97% Efficiency Possible ■ Pin Selectable Forced PWM or PWM/PFM Modes ■ Ultra Low Quiecent Current in PFM Mode: 50µA ■ 500nA (Max.) Shutdown Current ■ Output Adjustable Down to 0.75V ■ No External FET's or Schottky Diode Required ■ Uses Small Value Inductors and Ceramic Output Capacitors ■ Low Dropout Operation: 100% Duty Cycle ■ Soft Start and Thermal Shutdown Protection ■ Easy Frequency Synchonization ■ Small 10 Pin MSOP and 10 Pin DFN Package
APPLICATIONS
■ Mobile Phones ■ PDA's ■ DSC's ■ MP3 Players ■ USB Devices ■ Point of Use Power The SP6652 is high efficiency, synchronous buck regulator ideal for portable applications using one Li-Ion cell, with up to 1A output current. The 1.2MHz switching frequency and PWM control loop are optimized for small value inductor and ceramic output capacitor, for space constrained portable designs. At light load, the SP6652 can operate in either PFM mode for high efficiency, or PWM mode for constant frequency. In addition, the input voltage range of 2.7V to 5.5V; excellent transient response, output accuracy, and ability to transition into 100% duty cycle operation, further extending useful battery life, make the SP6652 a superior choice for a wide range of portable power applications. The output voltage is externally programmable down to 0.75V. A logic level shutdown control, external clock synchronization, and forced-PWM or automatic control inputs are provided. Other features include soft-start, over current protection and 140(C over-temperature shutdown. VOUT 3.3V at 1A 10µF 100k 340k 4.7µF VIN 10µF 6.2nF SP6652 PGND SGND FB COMP SD LX PVIN SVIN SYNC MODE ENABLE SHUTDOWN TYPICAL APPLICATION SCHEMATIC
DESCRIPTION
10 Pin MSOP
P VIN SVIN SYNC MODE PGND SGND FB COMP SD 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator Now Available in Lead Free Packaging
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration PARAMETER MIN TYP MAX UNITS CONDITIONS Input Voltage Operating UVLO 5.5 V Range FB Set Voltage 0.735 0.75 0.765 V T A = 27°C, FB = COMP FB Input Voltage -1 0.01 1 µAV FB = 0.8V Overall FB Accuracy -4 4 % FB = COMP FB Set Voltage (PFM Mode) 0.758 V Switching Frequency 1 1.2 1.4 MHz SYNC Tracking Frequency 1 1.2 1.4 MHz SYNC Input Current -1 0.01 1 µA SYNC Logic Threshold Low 0.3 0.6 Ω SYNC Logic Threshold High 1.7 PWM On-Time Blanking 50 ns PMOS Switch Resistance 0.25 0.6 Ω NMOS Switch Resistance 0.25 0.6 Ω Inductor Current Limit (PWM Mode) 1.2 1.4 1.6 A Inductor Current Limit (PFM Mode) 300 mA LX Leakage Current 0.1 3 µAS D\\=0V SVIN Quiecent Current 60 100 µA PFM Mode
2 TBD nA PWM Mode
1 500 mA Shutdown, SD\\=0V PVIN Quiecent Current 102 TBD µAV COMP = 0.6V ILX = 0 1 500 PWM Mode UVLO 2.6 2.7 2.8 V Undervoltage Lockout Threshold, V IN falling UVLO hysteresis 6 % Soft Start Current 1 2 3 µVV COMP = 1V SD\\, MODE Input Current -1 0.01 1 µA SD\\, MODE Logic Threshold Low 0.4 V SD\\, MODE Logic Threshold High 1.6 V Slope Compensation 700 mA/ µs Rising Over-Temperature Trip Point 140 °C Over-Temperature Hysteresis 14 °C ERROR AMPLIFIER Error Amplifier Transconductance 0.5 1 1.5 mS Error Amplifier Output Impedance 1 m Ω Error Amplifier Max Sink Current 15 40 60 µA Error Amplifier Max Source Current 15 40 60 µA VIN=UVIN=VSDN=3.6V, VOUT=VFB, IO = 0mA, TAMB = -40°C to +85°C, typical values at 27°C unless otherwise noted. ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.ELECTRICAL CHARACTERISTICS Note: This thermal Resistance Figure Applies only to a package with the exposed pad soldered to a PCB. Faliure to do this results in, approximately, a three-fold increase in thermal resistance.
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration PIN DESCRIPTION PIN NUMBER PIN NAME DESCRIPTION 1P GND Power Ground Pin. Synchronous rectifier current returns through this pin. 2S GND Internal Ground Pin. Control circuitry returns current to this pin. 3F B External feedback network input connection. Connect a resistor from to ground and from FB to output voltage to control the output voltage. Regulation point at FB=0.75V Typical. 4 COMP Compensation pin for error loop. Connect an R and C in series to ground to control open loop pole and zero. 5 SD\\ Shutdown control input. Tie pin to VIN for normal operation, tie to ground for shutdown. TTL input threshold.
6 MODE Connect this pin to VIN to force PWM operation and to S GND for
automatic PWM/PFM selection, for a better light load efficiency.
7 SYNC An external clock signal can be connected to this to synchronize the
switching frequency. The part runs in PWM mode in the precence of a sync clock. 8S VIN Internal supply voltage. Control circuitry is powered from from this pin. Use an RC filter close to the pin to cut down supply noise. 9P VIN Supply voltage for the output driver stage. Inductor charging current passes through this pin. 10 LX Inductor switching node. Inductor tied between this pin and the output capacitor to create regulated output voltage.
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration FUNCTIONAL DIAGRAM PARK PFM CLAMP CLR R S RST Slope Compensation CNTR R S Qn Q Reference NOSWITCH V0P3R VREF A=3 Gm A 300mA 2uA InternalSupply STRTSOFT SOFTSTRT CHG Soft Start M 7.5mV7.5mV DCHG FB_LO BLIM REFOK Pre-amp Error Amp S VIN P VIN ILPK CHG Current Loop Comparator PFM Loop Comparator 0.75V PWM Mode Comparator CLK ChargingPMOSReplica 0.3V0.75VREFOK V IN SD Shutdown Tr anslator GO PFMGO PWM Mode Select PWM/PFM CLK GO PFM GO PWM 0.75V 0.75V PFM Node Park Clamp Peak and Trough Current Detector R S CLR LX100mA 0mA + - + - - by 2OSC SYNC Co RL VOUT RF1 RF2 FB COMP MODE SYNC SGNDPGNDSD Driver DCHG Changing PMOS LX PWM/PFM Inductor Current Clamp 0.3V Low Vo Indicator FB_LO CLK Clock Generator Internal GND
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration DETAIL DESCRIPTION Current Mode Control and Slope Compensation The SP6652 is designed to use low value ce- ramic capacitors and low value inductors, to reduce the converter’s volume and cost in por- table devices Current mode PWM control was, therefore, chosen for the ease of compensation when using ceramic output capacitors and better transient line rejection, which is important in battery powered applications. Current mode control spreads the two poles of the output power train filter far apart so that the modulator gain crosses over at -20dB/decade instead of the usual -40dB/decade. The external compen- sation network is, simply, a series RC connected between ground and the output of the internal transconductance error amplifier. It is well known that an unconditional instability exists for any fixed frequency current-mode converter operating above 50% duty cycle. A simple, constant-slope compensation is chosen to achieve stability under these conditions. The most common high duty cycle application is a Li-Ion battery powered regulator with a 3.3V output (D ≥ 90%). Since the current loop is critically damped when the compensation slope (denoted MC V) equals the negative discharge slope (denoted M2V), the amount of slope com- pensation chosen is, therefore: M2 = dI L/dTOFF =-VOUT/L = -3.3V/4.7 µH = -702mA/µs M2V = M2*RPMOS MCV = -M2V = 702mA/µs*0.2Ω = 140mV/µs, for RPMOS = 0.20Ω The inductor current is sensed as a voltage across the PMOS charging switch and the NMOS synchronous rectifier (see BLOCK DIAGRAM) During inductor current charge, V(PVIN)-V(LX) represents the charging current ramp times the resistance of the PMOS charging switch. To keep the effective current slope compensation constant (remembering current is being com- pensated, not voltage) the voltage slope must be proportional to R PMOS. To account for this, the slope compensation voltage is internally gener- ated with a bias current that is also proportional to R PMOS. Over Current Protection In steady state closed loop operation the voltage at the COMP pin controls the duty cycle. Due to the current mode control and the slope compen- sation, this voltage will be: V(COMP) (I LPK* RPMOS + MCV *TON+ VBE(Q1) The COMP node will be clamped when the its voltage tries to exceed V(BLIM) + V BE (Q1). The VBE(Q1) term is cancelled by V BE(Q2) at the output of the translator. The correct value of clamp voltage is, therefore: V(BLIM) = IL(MAX)* RPMOS + MCV *tON The I L(MAX) term is generated with a bias current that is proportional to RPMOS, to keep the value of current limit approximately constant over process and temperature variations, while the MC V *TON is generated by a peak-holding cir- cuit that senses the amplitude of the slope com- pensation ramp at the end of T ON. There is minimum on-time (T ON) generated even if the COMP node is at 0V, since the peak current comparator is reset at the end of a charge cycle and is held low during a blanking time after the start of the next charge cycle. This is necessary to swamp the transients in the induc- tor current ramp around switching times. The minimum T ON (50ns, nominally) is not suffi- cient for the COMP node to keep control of the current when the output voltage is low. The inductor current tends to rise until the energy loss from the discharge resistances are equal to
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration the energy gained during the charge phase. For this reason, the clock frequency is cut in half when the feedback pin is below 0.3V, effec- tively reducing the minimum duty cycle in half. Above V(FB)=0.3V the clock frequency is nor- mal (see TYPICAL OPERATIONG CHAR- ACTERISTICS: Inductor current vs. VOUT) PFM Control for Light Loads If the MODE pin is connected to S GND, under light load conditions the SP6652 will transition to a PFM regulation mode. In this mode of operation, V(FB) is compared to the reference voltage plus 7.5mV, nominally (see BLOCK DIAGRAM). This sets the regulation point 1% higher than the PWM regulation voltage to prevent bouncing between modes at loading conditions near threshold. When V OUT falls below the PFM regulation point the voltage loop comparator issues a com- mand to turn on the PMOS switch to the output stage logic. The current sensing comparator compares the voltage across that switch to a reference set up by a biased replica of the PMOS switch, to set the peak PFM inductor current (nominally 300 mA). This comparator stops the charging cycle and initiates the discharge through the synchronous NMOS rectifier. Any new charging cycles are inhibited until a third comparator, the under-current compara- tor, which is setup to detect the instant when the inductor is fully discharged (NMOS V DS >0) enables the voltage loop. This keeps the PFM mode in discontinuous conduction mode (DCM). A timer disables both the Current Loop and Trough Current comparators 7µs after entering DCM, to save supply current under very light load conditions. The normal light load supply current is, nominally, 135 µA whereas the very light load supply current is 60 µA. DETAIL DESCRIPTION: Contunued Automatic Mode Selection If the MODE pin is connected to SVIN, the part will be forced into a PWM-only regulation mode. If the MODE pin is connected to SGND, the mode selection circuitry decides whether the con- verter should be in PWM or PFM mode, depend- ing on the load. Light loads call for the PFM loop, which is forced into DCM as well. Me- dium to heavy loads activate the PWM loop. Starting from a PWM state, the Peak and Trough Current Detector window comparator monitors the peak inductor current during charge and the trough inductor current during discharge. Both the peak and trough are monitored because the ripple current varies considerably across the application spectrum. The lossless inductor cur- rent ripple is: I L(RIPPLE)=(VIN-VOUT)*(VOUT/VIN)*(1/L *fCLK) Where fCLK is the switching frequency (1.2MHz, nominally). If the peak inductor current is below 100mA or the trough reaches 0mA (or less) during one cycle, then the current is defined as low enough for PFM mode. This has to happen during 32 consecutive clock cycles before the output sig- nal goes high and switches modes. This delay is to avoid prematurely switching into PFM mode during a negative load transient. Once in PFM mode, the regulated output volt- age will be 1% higher than in PWM and con- tinue regulating there, as described in the PFM Control For Light Loads section. When the load increases past the point where the PFM mode can regulate while remaining in DCM (which is l 1/2 of the peak inductor current in PFM, or 1/ 2*300mA=150mA), the output voltage will start dropping. When it falls 1% below the reference voltage, that is 2% below the PFM regulation point, the PWM Mode Comparator will switch and set the Mode Control latch to PWM mode.
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration Voltage Loop and Compensation in PWM Mode The voltage loop section of the circuit consists of the error amplifier and the translator circuits (see functional diagram). The input of the volt- age loop is the 0.75V reference voltage minus the divided down output voltage at the feedback pin. The output of the error amplifier is trans- lated from a ground referred signal (the COMP node) to a power input voltage referred signal. The output of the voltage loop is fed to the positive terminal of the Current Loop compara- tor, and represents the peak inductor current necessary to close the loop. The total power supply loop is compensated with a series RC network connected from the COMP pin to ground. Compensation is simple due to current-mode control. The modulator has two dominant poles: one at a low frequency, and one above the crossover frequency of the loop, as seen in the graph below, Linearized Modula- tor Frequency Response vs. Inductor Value. The low frequency pole for L1=5 µH is 4kHz, the second pole is 500kHz, and the gain-band- width is 20kHz. The total loop crossover fre- quency is chosen to be 200kHz, which is 1/6 th of the clock frequency. This sets the 2nd modula- tor pole at 2.5 times the crossover frequency. Therefore the gain of the error amplifier can be 200kHz/20kHz = 10 at the first modulator pole of 4kHz. The error amp transconductance is 1mS, so this sets the RZ resistor value in the compensation network at 10/1mS = 10kΩ. The zero frequency is placed at the first pole to provide at total system response of -20dB/de- cade (the zero from the error amp cancels the first modulator pole, leaving the 1 pole rolloff from the error amp pole). The compensation capacitor becomes: Cc = 1/(2*π*Rz*pole1) = 1/(6.28*10kΩ*4kHz) = 4nF DETAIL DESCRIPTION: Contunued L1VAL 2u 3u 4u 5u 6u 7u 8u 9u 10u Mod_pole1 Mod_pole2 Gbw_modfb 12K 16K 20K1 0.4M 0.8M 1.2M 1.6M 2.0M2 10K 20K 30K 40K 50K3 1 2 3 Conditions: VIN=5V, VOUT=3.3V, fCLK=1.2MHz, COUT=10µF, and MCV=132mV/µs. The inductor is varied from 2µH to 10µH Linearized Modulator Frequency Response vs. Inductor Value.
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration APPLICATIONS INFORMATION VOUT 10µF RFBH RFBL SYNC MODE SD Rz 16.2nF Cc 4.7µH 10Ω 1µF 10µF VIN SP6652 PGND SGND FB COMP SD LX PVIN SVIN SYNC MODE Complete Application Circuit.
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration PACKAGE: 10 PIN MSOP (ALL DIMENSIONS IN MILLIMETERS) 0.07 - - L ØØ1 R Seating Plane E/2 e E D Gauge Plane D A2 A b - - 1.1 0 - 0.15 Dimensions in (mm) 10-PIN MSOP JEDEC MO-187 (BA) Variation 0.75 0.85 0.95 0.17 - 0.27 0.08 - 0.23
3.00 BSC
4.90 BSC
0.4 0.60 0.80 0.95 - 0.25 - - 10 - 0.07 - - 0º 8º A b c D E L N R Ø 0º - 15ºØ1 MIN NOM MAX e
2.00 BSC
0.50 BSC
c WITH PLATING BASE METAL (b) Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration PACKAGE: 10 PIN DFN Top View D/2 Bottom View D E E/2 e b L Pin 1 identifier to be located within this shaded area. Terminal #1 Index Area (D/2 * E/2) K Side View DIMENSIONS Minimum/Maximum (mm)
10 Pin DFN
(JEDEC MO-229, VEED-5 VARIATION) COMMON HEIGHT DIMENSION A b D E e L K 0.80 0.90 1.00
0.20 REF
2.20 - 2.70 1.40 - 1.75 0.30 0.40 0.50 0.20 0.18 0.25 0.30
0.50 PITCH
0 0.02 0.05
Date:5/25/04 SP6652 1A, High Efficiency, High Frequency Current Mode PWM Buck Regulator © Copyright 2004 Sipex Corp oration Corporation ANALOG EXCELLENCE Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. Sipex Corporation Headquarters and Sales Office
233 South Hillview Drive
Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
ORDERING INFORMATION
Part Number Operating Temperature Range Package Type /TR = Tape and Reel Pack quantity is 2,500 for MSOP and 3,000 for DFN. Available in lead free packaging. To order add "-L" suffix to part number. Example: SP6652EU/TR = standard; SP6652EU-L/TR = lead free