SP6330

SP6330 SIPEX | Alldatasheet

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Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation SP6330, SP6332 and SP6334 Quad µPower Supervisory Circuits with Manual Reset & Watchdog SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of microprocessor reset supervisory circuits with multiple reset voltages. The family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. These circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are fully specified over -40oC to +85oC temperature range.

FEATURES

■ Low operating voltage of 1.6V ■ Low operating current of 20 µA typical ■ Monitors up to four supplies simultaneously ■ Adjustable inputs monitor down to 0.5V ■ Reset asserted down to 0.9V ■ 2% accuracy over temperature range ■ Open Drain (OD) or CMOS RSTB output or CMOS RST output ■ 4 Reset Timeout Periods: 50ms, 100ms, 200ms and 400ms ■ Watch Dog Input Functionality -- WDI ■ Manual Reset Input (Active Low) -- MRIB ■ 8 Pin TSOT package

DESCRIPTION

Available in Lead Free Packaging SEE PAGE 2 FOR OTHER AVAILABLE PINOUTS 4 5

8 Pin TSOTV2

TYPICAL APPLICATION CIRCUIT

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporatio n Terminal Voltage (with respect to GND) Input Current/Output ABSOLUTE MAXIMUM RATINGS Feature and Pinout Diagram Operating Temperature Storage Temperature PART NUMBER V1 V2 V3 V4 Reset MRIB WDI SP6330 √ √ √ √ OD Active Low √ √ SP6332 √ √ √ √ CMOS Active Low √ √ SP6334 √ √ √ √ CMOS Active High √ √ 4 5 These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. Representative Samples Available PINOUT DIAGRAMS Sipex Product Product Description Package V1 (Volts) (Volts) (Volts) (Volts) Reset (ms) Ordering # SP6330 Quad Supervisor Open Drain low 8 Pin TSOT 2.925 1.575 0.5 0.5 200 SP6330EK1-L-W-G-C SP6330 Quad Supervisor Open Drain low 8 Pin TSOT 3.075 2.313 0.5 0.5 200 SP6330EK1-L-X-J-C SP6330 Quad Supervisor Open Drain low 8 Pin TSOT 4.625 2.313 0.5 0.5 200 SP6330EK1-L-Z-J-C SP6332 Quad Supervisor CMOS low 8 Pin TSOT 2.625 1.575 0.5 0.5 200 SP6330EK1-L-V-G-C

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation

ELECTRICAL CHARACTERISTICS

PARAMETER MIN TYP MAX UNITS CONDITIONS Operating Voltage Range 0.9 5.5 V TA = -40ºC to +85ºC 20 30 uA V1 < 5.5V, V2 < 3.60V, all I/O pins open 15 25 V1 < 3.6V, V2 < 2.75V, all I/O pins open 4.532 4.625 4.718 Z (valid for V1 falling) 4.287 4.375 4.463 Y (valid for V1 falling) 3.013 3.075 3.137 X (valid for V1 falling) 2.866 2.925 2.984 W (valid for V1 falling) V1 Reset 2.572 2.625 2.678 V (valid for V1 falling) Threshold 2.273 2.320 2.367 U (valid for V1 falling) 2.146 2.190 2.234 T (valid for V1 falling) 1.636 1.670 1.704 S (valid for V1 falling) 1.548 1.580 1.612 R (valid for V1 falling) 2.266 2.313 2.360 J (valid for V2 falling) 2.144 2.188 2.232 I (valid for V2 falling) 1.631 1.665 1.698 H (valid for V2 falling) 1.543 1.575 1.607 G (valid for V2 falling) V2 Reset 1.360 1.388 1.416 F (valid for V2 falling) Threshold 1.286 1.313 1.340 E (valid for V2 falling) 1.087 1.110 1.133 D (valid for V2 falling) 1.029 1.050 1.071 C (valid for V2 falling) 0.816 0.833 0.850 B (valid for V2 falling) 0.772 0.788 0.804 A (valid for V2 falling) Threshold 1 Tempco 0.06 mV/ºC Threshold 2 Tempco 0.04 mV/ºC Threshold 1 Hysteresis 0.65 % reference to Vth1 typical Threshold 2 Hysteresis 0.5 % reference to Vth2 typical V1 to RST/RSTB Delay 50 us V1 = Vth1 to (Vth1-0.1V), Vth1 = 3.075 V2 to RST/RSTB Delay 50 us V2 = Vth2 to (Vth2-0.1V), Vth2 = 1.575 Reset Timeout Period (T1) 37 50 63 ms TOPT-1 Reset Timeout Period (T2) 74 100 126 ms TOPT-2 Reset Timeout Period (T3) 148 200 252 ms TOPT-3 Reset Timeout Period (T4) 296 400 504 ms TOPT-4 V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC Supply Current V V

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation PARAMETER MIN TYP MAX UNITS CONDITIONS V3 Input Threshold 490 500 510 mV V3 Input Current -50 50 nA TA = +25ºC V3 Threshold Hysteresis 1.5 mV V4 Input Threshold 490 500 510 mV V4 Input Current -50 50 nA TA = +25ºC V4 Threshold Hysteresis 1.5 mV MRIB Input Threshold 0.2*V1 V Vil MRIB Input Threshold 0.8*V1 V Vih MRIB Minimum Input Pulse Width 1 us MRIB Glitch Rejection 150 ns MRIB to RST/RSTB Delay 100 ns MRIB Pull-Up Resistance 30 55 85 kΩ Watchdog Timeout Period 1.3 1.6 1.9 sec WDI Pulse Width 0.1 us WDI Input Threshold 0.2*V1 V Vil WDI Input Threshold 0.8*V1 V Vih WDI Input Current -500 500 nA WDI = 0.0V or V1 RSTB (CMOS or OD) 0.2*V1 V V1 = Vth1 - 0.1V, Isink = 1mA, output asserted RSTB (CMOS) 0.8*V1 V V1 = Vth1 + 0.1V, Isource = 1mA, output not asserted RST (CMOS) 0.8*V1 V V1 = Vth1 - 0.1V, Isource = 1mA, output asserted RST (CMOS) 0.2*V1 V V1 = Vth1 + 0.1V, V2 > Vth2, V3 > 0.5, V4 > 0.5, Isource = 1mA, output not asserted RSTB Output OD Leakage Current 2 nA TA = +25ºC V3 RESET COMPARATOR INPUT V4 RESET COMPARATOR INPUT MRIB - MANUAL RESET INPUT V1 =1.6V to 5.5V; TA = -40ºC to +85ºC; unless otherwise noted. Typical values are at TA =+25ºC RESET OUTPUTS RST / RSTB WDI - WATCHDOG INPUT

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation PIN DESCRIPTION Pin # Name Description 1 V1 First supply voltage input. Also powers internal circuitry. Trip threshold voltage internally set. 2 V2 Second supply voltage input. Trip threshold voltage internally set.

3 MRIB

Manual Reset Input pin. Active low. It has an internal pull-up resistor. Reset asserted when MRIB is pulled low and is kept asserted for 200ms after MRIB is released or pulled high. Leave open if not used. 4 V3 Input for the third supply voltage. Trip threshold is 0.5V. 5 V4 Input for the fourth supply voltage. Trip threshold is 0.5V. 6 GND Common ground reference pin.

7 WDI

Watch-Dog Input pin. When no transition is detected at the WDI pin for the duration of WDI timeout period, reset is asserted. Leave open if not used. RST/RSTB output is used to signal watchdog timeout overflow. RST/RSTB output pulses high/low (depending on the active reset polarity) for the reset timeout period after each watchdog timeout overflow. The watchdog timer clears whenever the reset is asserted or manual reset is asserted or a transition is observed at WDI pin. Watchdog timer functionality can be disabled in parts by leaving this input floating.

8 RST/RSTB

Reset output. Open-Drain or CMOS, active high or low. Reset is asserted when any of the four supply inputs is below its trip threshold. It stays asserted for 200 ms (typical / default) after the last supply input traverses its trip threshold. Reset is guaranteed to be in the correct state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop below their corresponding reset thresholds, or MRIB is pulled “LOW” or the watchdog timer triggers a reset (devices without WDOB). RST/RSTB remains asserted for the reset timeout period after V1 and V2 and V3 and V4 exceed their corresponding reset thresholds or MRIB goes “LOW” to “HIGH”. Open-drain outputs require an external pull-up resistor. CMOS outputs are referenced to V1.

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation The SP6330, SP6332, and SP6334 include a low-voltage precision bandgap reference, four precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. The family is designed to supervise up to 4 independent supply voltages. V1 and V2 supply inputs have their resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow user to customize Block Diagram THEORY OF OPERATION two additional supply thresholds to be monitored by means of external resistor dividers. The devices also feature manual reset and watchdog functionalities. As these devices do not have watchdog outputs, the watchdog timer is serviced internally during the watchdog timeout period when WDI is left unconnected. The watchdog functionality can be disabled by leaving the WDI input floating. OSC WDI LOGIC CONTROL LOGIC V1 V2 V3 V4 WDI RSTB (RST) GND 1.25V 0.5V MRIB Bandgap Ref

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation Figure 1: Functionality of a SP63XX family member with manual reset and watchdog capabilities but without WDOB output.

• V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding thresholds)---> RSTB is de-asserted after reset timeout period (Trp).
• MRIB goes to “LOW” to force “Reset” ----> RSTB is asserted immediately.
• WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is asserted for a duration of reset timeout period (Trp).
• One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB is asserted immediately. THEORY OF OPERATION Vth1 Vth2 Vth3=0.5V Vth4=0.5V MRIB WDI RSTB Trp Trp Twd Trp T<Twd T<Twd T<Twd T<Twd T<Twd

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation RSTB ResetB Timeout Delay

APPLICATION INFORMATION

WDI = GND, V1=V2=V3=V4=5V, MRIB = ope n. Watchdog Timeout Period = 1.52S Watchdog Timeout Period

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporatio n 100 200 300 400 500 85 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 D e g C R e s e t T i m e o u t ( m S e c ) Reset Timeout vs. Temperature ResetTimeout Delay Vs. Temperature R S T B v s . V 1 (V 2 = G N D ) 0.5 1.5 2.5 3.5 4.5 V1 (Vdc) RS T B (V o lt s DC) Reset Good (400ms Reset)

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation V 1 a n d V 2 G litc h r e je c tio n 100 150 200 250 0 20 40 60 80 100 120 Overdrive (mV) RS TB asser ted above line D u r a t i o n ( u Se c ) V 3 a n d V 4 g litc h re je c tio n 100 120 0 20 40 60 80 100 120 O v e rdriv e (mV) RSTB asser ted above line D u r a t i o n ( u Se c ) V1 and V2 Glitch Rejection V3 and V4 Glitch Rejection

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation PACKAGE: 8 PIN TSOT FRONT VIEW L Gauge Plane c R ø Seating Plane SIDE VIEW A Seating Plane D E E/2 321 b e E1/2 Pin1 Designator to be within this INDEX AREA (D/2 x E1/2) TOP VIEW (L1) D/2 8 7 6 MIN NOM MAX MIN NOM MAX A1 0.00 - 0.10 0.000 - 0.004 c 0.08 - 0.20 0.003 - 0.008 D E Ø 0˚ 4º 8º 0º 4º 8º Ø1 4˚ 10º 12º 4º 10º 12º R1 0.10 - 0.25 0.004 - 0.010 b 0.22 - 0.38 0.009 - 0.015 e e1 1.95 BSC 0.60 REF 0.024 REF 1.60 BSC 0.063 BSC

0.077 BSC

0.65 BSC 0.026 BSC 0.25 BSC 0.010 BSC SIPEX Pkg Signoff Date/Rev: JL Oct3-05 / Rev A SYMBOL

8 Pin TSOT JEDEC MO-193 Variation BA

2.90 BSC 0.114 BSC 2.80 BSC 0.110 BSC Dimensions in Millimeters: Controlling Dimension Dimensions in Inches Conversion Factor: 1 Inch = 25.40 mm

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation Part Naming Nomenclature SP63NN - Th1 - Th2 - TOPT T1 -- 50 ms T2 -- 100 ms T3 -- 200 ms T4 -- 400 ms A -- 0.788 V B -- 0.833 V C -- 1.050 V D -- 1.110 V E -- 1.313 V F -- 1.388 V G -- 1.575 V H -- 1.665 V I -- 2.188 V J -- 2.313 V Z -- 4.625 V Y -- 4.375 V X -- 3.075 V W -- 2.925 V V -- 2.625 V U -- 2.320 V T -- 2.190 V S -- 1.670 V R -- 1.580 V30 -- Quad Sp, MR, WDI, OD RSTB 31 -- Quad Sp, OD RSTB 32 -- Quad Sp, MR, WDI, CMOS RSTB 33 -- Quad Sp, CMOS RSTB 34 -- Quad Sp, MR, WDI, CMOS RST 35 -- Quad Sp, CMOS RST 36 -- Triple Sp, WDI, PF, OD RSTB 37 -- Triple Sp, WDI, PF, CMOS RSTB 38 -- Triple Sp, WDI, PF, CMOS RST 39 -- Triple Sp, MR, WDI, OD RSTB - WDOB 40 -- Dual Sp, WDI, OD RSTB - WDOB 41 -- Triple Sp, WDI, PF, CMOS RSTB - WDOB 42 -- Dual Sp, WDI, CMOS RSTB - WDOB A B C D E F G H I J K L M A B C D Example: AZJD means: SP6330 in TSOT-8 lead package V1 Threshold is 4.625V V2 Threshold is 2.313V Reset Timeout is 400ms AZJD Pin 1

Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family © Copyright 2006 Sipex Corporation Model Temperature Range Package Types Available in lead free packaging only. /TR = Tape and Reel Pack quantity 2,500 forTSOT-8 Contact Factory for availability of particular voltage threshold and reset timeout options. Note that the Ordering Information denoting those options corresponds to the Part Naming Nomenclature shown on the previous page. Voltage Threshold 2; and C -- 200ms reset timeout.

ORDERING INFORMATION

233 South Hillview Drive

Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.