SP505

SP505 SIPEX | Alldatasheet

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Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation The SP505 is a monolithic device that supports eight (8) popular serial interface standards for DTE to DCE connectivity. The SP505 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex patented (5,306,954) charge pump allowing +5V only operation. Seven (7) drivers and seven (7) receivers can be configured via software for any of the above interface modes at any time. The SP505 requires no additional external components for compliant operation for all of the eight (8) modes of operation. All necessary termination is integrated within the SP505 and is switchable when Additional features with the SP505 include internal loopback that can be initiated in either single-ended or differential modes. While in loopback mode, driver outputs are internally connected to receiver inputs creating an internal signal path convenient for diagnostic testing. This eliminates the need for an external loopback plug. The SP505 also includes a latch enable pin with the driver and receiver address decoder. Tri-state ability for the driver and receiver outputs is controlled by supplying a 4-bit word into the address decoder. Seven (7) drivers and one (1) receiver in the SP505 include separate enable pins for added convenience. The SP505 is ideal for WAN serial ports in networking equipment such as routers, switches, DSU/CSU's, and other access devices. SP505 W AN Multi-Mode Serial Transceiver DESCRIPTION... ■ +5V Only Operation ■ Seven (7) Drivers and Seven (7) Receivers ■ Driver and Receiver Tri-state Control ■ Internal Transceiver Termination Resistors for V.11 and V.35 Protocols ■ Loopback Self-Test Mode ■ Software Selectable Protocol Selection ■ Interface Modes Supported: ✓ V.36 (V.10 & V.11) ✓ RS-485 (un-terminated V.11) ■ Improved ESD Tolerance for Analog I/Os ■ High Differential Transmission Rates ➥ SP505A - 10Mbps ➥ SP505B - over 16Mbps ■ Compliant to NET1/2 and TBR2 Physical Layer Requirements (TUV Test Report NET2/052101/98) (TUV Test Report CTR2/052101/98) EIA-530 WAN V.35

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS LOGIC INPUTS VIL 0.8 Volts VIH 2.0 Volts LOGIC OUTPUTS VOL 0.4 Volts I OUT = –3.2mA VOH 2.4 Volts I OUT = 1.0mA V.28 DRIVER DC Parameters Outputs Open Circuit Voltage +15 Volts per Figure 1 Loaded Voltage +5.0 +15 Volts per Figure 2 Short-Circuit Current +100 mA per Figure 4 Power-Off Impedance 300 Ω per Figure 5 AC Parameters V CC = +5V for AC parameters Outputs Transition Time 1.5 µs per Figure 6; +3V to -3V Instantaneous Slew Rate 30 V/ µs per Figure 3 Propagation Delay tPHL 0.5 1 5 µs tPLH 0.5 1 5 µs Max.Transmission Rate 120 230 kbps V.28 RECEIVER DC Parameters Inputs Input Impedance 3 7 k Ω per Figure 7 Open-Circuit Bias +2.0 Volts per Figure 8 HIGH Threshold 1.7 3.0 Volts LOW Threshold 0.8 1.2 Volts AC Parameters V CC = +5V for AC parameters Propagation Delay tPHL 50 100 500 ns tPLH 50 100 500 ns ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. V Input Voltages: Output Voltages: Package Derating: STORAGE CONSIDERATIONS Due to the relatively large package size of the 80-pin quad flat-pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order remove moisture prior to soldering. Sipex ships the 80-pin QFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH.

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS V.28 RECEIVER (continued) AC Parameters (cont.) Max.Transmission Rate 120 230 kbps V.10 DRIVER DC Parameters Outputs Open Circuit Voltage +4.0 +6.0 Volts per Figure 9 Test-Terminated Voltage 0.9VOC Volts per Figure 10 Short-Circuit Current +150 mA per Figure 11 Power-Off Current +100 µA per Figure 12 AC Parameters V CC = +5V for AC parameters Outputs Transition Time 200 ns per Figure 13; 10% to 90% Propagation Delay t PHL 50 100 500 ns tPLH 50 100 500 ns Max.Transmission Rate 120 kbps V.10 RECEIVER DC Parameters Inputs Input Current –3.25 +3.25 mA per Figures 14 and 15 Input Impedance 4 k Ω Sensitivity +0.3 Volts AC Parameters V CC = +5V for AC parameters Propagation Delay tPHL 50 120 250 ns tPLH 50 120 250 ns Max.Transmission Rate 120 kbps V.11 DRIVER DC Parameters Outputs Open Circuit Voltage +5.0 Volts per Figure 16 Test Terminated Voltage+2.0 Volts per Figure 17 0.5VOC 0.67VOC Volts Balance +0.4 Volts per Figure 17 Offset +3.0 Volts per Figure 17 Short-Circuit Current +150 mA per Figure 18 Power-Off Current +100 µA per Figure 19 AC Parameters V CC = +5V for AC parameters Outputs Transition Time 20 ns per Figures 21 and 36; 10% to 90% Propagation Delay t PHL 50 85 110 ns per Figures 33 and 36, C L = 50pF tPLH 50 85 110 ns per Figures 33 and 36, C L = 50pF Differential Skew 10 20 ns per Figures 33 and 36, C L = 50pF Max.Transmission Rate per Figure 33, C L = 50pF SP505ACF 10 12 Mbps f IN = 5MHz SP505BCF 16.4 18 Mbps f IN = 8.2MHz V.11 RECEIVER DC Parameters Inputs Common Mode Range –7 +7 Volts Sensitivity +0.3 Volts

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS V.11 RECEIVER (continued) DC Parameters (cont.) Input Current –3.25 +3.25 mA per Figure 20 and 22 Current w/ 100 Termination +60.75 mA per Figure 23 and 24 Input Impedance 4 k Ω AC Parameters V CC = +5V for AC parameters Propagation Delay t PHL 80 110 130 ns per Figures 33 and 38; C L = 50pF tPLH 80 110 130 ns per Figures 33 and 38; C L = 50pF Differential Skew 20 ns per Figure 33; C L = 50pF Max.Transmission Rate per Figure 33; C L = 50pF SP505ACF 10 12 Mbps f IN = 5MHz SP505BCF 16.4 18 Mbps f IN = 8.2MHz V.35 DRIVER DC Parameters Outputs Open Circuit Voltage +1.20 Volts per Figure 16 Test Terminated Voltage+0.44 +0.66 Volts per Figure 25 Offset +0.6 Volts per Figure 25 Source Impedance 50 150 Ω per Figure 27; ZS = V2/V1 x 50 Short-Circuit Impedance 135 165 Ω per Figure 28 AC Parameters V CC = +5V for AC parameters Outputs Transition Time 30 40 ns per Figure 29; 10% to 90% Propagation Delay t PHL 50 90 110 ns per Figures 33 and 36; C L = 20pF tPLH 50 90 110 ns per Figures 33 and 36; C L = 20pF Differential Skew 20 30 ns per Figures 33 and 36; C L = 20pF Max.Transmission Rate per Figure 33; C L = 20pF SP505ACF 10 12 Mbps f IN = 5MHz SP505BCF 16.4 18 Mbps f IN = 8.2MHz V.35 RECEIVER DC Parameters Inputs Sensitivity +80 mV Source Impedance 90 110 Ω per Figure 30; ZS = V2/V1 x 50 Short-Circuit Impedance 135 165 Ω per Figure 31 AC Parameters V CC = +5V for AC parameters Propagation Delay t PHL 80 110 130 ns per Figures 33 and 38; C L = 20pF tPLH 80 110 130 ns per Figures 33 and 38; C L = 20pF Differential Skew 20 ns per Figure 33; C L = 20pF Max.Transmission Rate per Figure 33; C L = 20pF SP505ACF 10 12 Mbps f IN = 5MHz SP505BCF 16.4 18 Mbps f IN = 8.2MHz TRANSCEIVER LEAKAGE CURRENTS Driver Output 3-State Current 100 500 µA per Figure 32; Drivers disabled Rcvr Output 3-State Current 1 10 µA DEC X = 0000, 0.4V VO 2.4V

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation OTHER AC CHARACTERISTICS TA = +25°C and VCC = +5.0V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL ; Tri-state to Output LOW 0.70 5.0 µsC L = 100pF, Fig. 34 & 40; S1 closed tPZH ; Tri-state to Output HIGH 0.40 2.0 µsC L = 100pF, Fig. 34 & 40; S2 closed tPLZ ; Output LOW to Tri-state 0.20 2.0 µsC L = 100pF, Fig. 34 & 40; S1 closed tPHZ ; Output HIGH to Tri-state 0.40 2.0 µsC L = 100pF, Fig. 34 & 40; S2 closed RS-423/V.10 tPZL ; Tri-state to Output LOW 0.15 2.0 µsC L = 100pF, Fig. 34 & 40; S1 closed tPZH ; Tri-state to Output HIGH 0.20 2.0 µsC L = 100pF, Fig. 34 & 40; S2 closed tPLZ ; Output LOW to Tri-state 0.20 2.0 µsC L = 100pF, Fig. 34 & 40; S1 closed tPHZ ; Output HIGH to Tri-state 0.15 2.0 µsC L = 100pF, Fig. 34 & 40; S2 closed RS-422/V.11 tPZL ; Tri-state to Output LOW 2.80 10.0 µsC L = 100pF, Fig. 34 & 37; S1 closed tPZH ; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S2 closed tPLZ ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 34 & 37; S1 closed tPHZ ; Output HIGH to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 34 & 37; S2 closed V.35 tPZL ; Tri-state to Output LOW 2.60 10.0 µsC L = 100pF, Fig. 34 & 37; S1 closed tPZH ; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S2 closed tPLZ ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 34 & 37; S1 closed tPHZ ; Output HIGH to Tri-state 0.15 2.0 µsC L = 15pF, Fig. 34 & 37; S2 closed RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL ; Tri-state to Output LOW 0.12 2.0 µsC L = 100pF, Fig. 35 & 38; S1 closed tPZH ; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 35 & 38; S2 closed tPLZ ; Output LOW to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 35 & 38; S1 closed tPHZ ; Output HIGH to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 35 & 38; S2 closed RS-423/V.10 tPZL ; Tri-state to Output LOW 0.10 2.0 µsC L = 100pF, Fig. 35 & 38; S1 closed tPZH ; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 35 & 38; S2 closed tPLZ ; Output LOW to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 35 & 38; S1 closed tPHZ ; Output HIGH to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 35 & 38; S2 closed

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation POWER REQUIREMENTS PARAMETER MIN. TYP. MAX. UNITS CONDITIONS VCC 4.75 5.00 5.25 Volts ICC (No Mode Selected) 30 mA All ICC values are with VCC = +5V, (V.28/RS-232) 60 mA T = +25 oC, all drivers are loaded to (V.11/RS-422) 300 mA their specified maximum load and all (RS-449) 250 mA drivers are active at their maximum (V.35) 105 mA specified data transmission rates. EIA-530 260 mA EIA-530A 250 mA V.36 65 mA OTHER AC CHARACTERISTICS (Continued) TA = +25°C and VCC = +5.0V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-422/V.11 tPZL ; Tri-state to Output LOW 0.10 2.0 µsC L = 100pF, Fig. 35 & 39; S1 closed tPZH ; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 35 & 39; S2 closed tPLZ ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 35 & 39; S1 closed tPHZ ; Output HIGH to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 35 & 39; S2 closed V.35 tPZL ; Tri-state to Output LOW 0.10 2.0 µsC L = 100pF, Fig. 35 & 39; S1 closed tPZH ; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 35 & 39; S2 closed tPLZ ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 35 & 39; S1 closed tPHZ ; Output HIGH to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 35 & 39; S2 closed TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 33, 36, 38) V.28 Driver 100 ns | (t phl )Tx1 – (tphl )Tx6,7 | 100 ns | (t plh )Tx1 – (tplh )Tx6,7 | V.28 Receiver 20 ns | (t phl )Rx1 – (tphl )Rx2,7 | 20 ns | (t phl )Rx1 – (tphl )Rx2,7 | V.11 Driver 2 ns | (t phl )Tx1 – (tphl )Tx6,7 | 2n s | ( t plh )Tx1 – (tplh )Tx6,7 | V.11 Receiver 3 ns | (t phl )Rx1 – (tphl )Rx2,7 | 3n s | ( t phl )Rx1 – (tphl )Rx2,7 | V.10 Driver 5 ns | (t phl )Tx2 – (tphl )Tx3,4,5 | 5n s | ( t plh )Tx2 – (tplh )Tx3,4,5 | V.10 Receiver 5 ns | (t phl )Rx2 – (tphl )Rx3,4,5 | 5n s | ( t phl )Rx2 – (tphl )Rx3,4,5 | V.35 Driver 4 ns | (t phl )Tx1 – (tphl )Tx6,7 | 4n s | ( t plh )Tx1 – (tplh )Tx6,7 | V.35 Receiver 6 ns | (t phl )Rx1 – (tphl )Rx2,7 | 6n s | ( t phl )Rx1 – (tphl )Rx2,7 |

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation PINOUT… PIN ASSIGNMENTS… CLOCK AND DATA GROUP Pin 1 — RxD — Receive Data; TTL output, sourced from RD(a) and RD(b) inputs. Pin 14 — TxD — TTL input ; transmit data source for SD(a) and SD(b) outputs. Pin 15 — TxC — Transmit Clock; TTL input for TT driver outputs. Pin 20 — RxC — Receive Clock; TTL output sourced from RT(a) and RT(b) inputs. Pin 22 — ST — Send Timing; TTL input; source for ST(a) and ST(b) outputs. Pin 37 — RT(a) — Receive Timing; analog input, inverted; source for RxC. Pin 38 — RT(b) — Receive Timing; analog input, non-inverted; source for RxC. Pin 42 — ST(a) — Send Timing; analog output, inverted; sourced from ST. Pin 44 — ST(b) — Send Timing; analog output, non-inverted; sourced from ST. Pin 59 — SD(b) — Analog Out — Send data, non-inverted; sourced from TxD. Pin 61 — SD(a) — Analog Out — Send data, inverted; sourced from TxD. Pin 63 — TT(a) — Analog Out — Terminal Timing, inverted; sourced from TxC Pin 65 — TT(b) — Analog Out — Terminal Timing, non–inverted; sourced from TxC. Pin 70 — RD(a) — Receive Data, analog input; inverted; source for RxD. Pin 71 — RD(b) — Receive Data; analog input; non-inverted; source for RxD. Pin 76 — SCT(a) — Serial Clock Transmit; analog input, inverted; source for SCT. Pin 77 — SCT(b) — Serial Clock Transmit: analog input, non–inverted; source for SCT Pin 79 — SCT — Serial Clock Transmit; TTL output; sources from SCT(a) and SCT(b) inputs. CONTROL LINE GROUP Pin 13 — DTR — Data Terminal Ready; TTL input; source for TR(a) and TR(b) outputs. Pin 16 — RTS — Ready To Send; TTL input; source for RS(a) and RS(b) outputs. Pin 17 — RL — Remote Loopback; TTL input; source for RL(a) and RL(b) outputs. Pin 19 — DCD— Data Carrier Detect; TTL output; sourced from RR(a) and RR(b) inputs. Pin 21 — RI — Ring In; TTL output; sourced from IC(a) and IC(b) inputs. Pin 24 — LL — Local Loopback; TTL input; source for LL(a) and LL(b) outputs. Pin 35 — RR(a)— Receiver Ready; analog input, inverted; source for DCD. Pin 36 — RR(b)— Receiver Ready; analog input, non-inverted; source for DCD. Pin 39 — IC(a)— Incoming Call; analog input, inverted; source for RI. Pin 40 — IC(b)— Incoming Call; analog input,non-inverted; source for RI. RxD 1 SDEN 2 TREN 3 RSEN 4 LLEN 5 TTEN 6 SCTEN 7 LATCH 8 DEC 3 9 DEC 2 10 DEC 1 11 DEC 0 12 DTR 13 TxD 14 TxC 15 RTS 16 RL 17 RLEN 18 DCD 19 RxC 20 RI 21 ST 22 STEN 23 LL 24 VCC 25 C 1+ 26 VDD 27 C 2+ 28 GND 29 C 1– 30 C 2– 31 VSS 32 VCC 33 GND 34 RR(a) 35 RR(b) 36 RT(a) 37 RT(b) 38 IC(a) 39 IC(b) 40

60 GND

59 SD(b)

58 TR(a)

57 GND

56 TR(b)

54 RS(a)

53 GND

52 RS(b)

51 LL(a)

50 GND

49 LL(b)

47 RL(a)

46 GND

45 RL(b)

44 ST(b)

43 GND

42 ST(a)

80 CTS

79 SCT

78 DSR

77 SCT(b)

76 SCT(a)

75 GND

73 VCC

72 GND

71 RD(b)

70 RD(a)

69 DM(b)

68 DM(a)

67 CS(b)

66 CS(a)

65 TT(b)

64 GND

63 TT(a)

61 SD(a)

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation Pin 7 — SCTEN — Enables SCT receiver; active high; TTL input. Pin 8 — LATCH — Latch control for decoder bits (pins 9-12), active low. Logic high input will make decoder transparent. Pins 12–9 — DEC 0 – DEC3 — Transmitter and receiver decode register; configures transmitter and receiver modes; TTL inputs. Pin 18 — RLEN — Enables RL driver; active low; TTL input. Pin 23 — STEN — Enables ST driver; active low; TTL input. POWER SUPPLIES Pins 25, 33, 41, 48, 55, 62, 73, 74 — V CC — +5V input. Pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 — GND — Ground. Pin 27 — V DD +10V Charge Pump Capacitor — Connects from VDD to VCC. Suggested capaci- tor size is 22µF, 16V. Pin 32 — V SS –10V Charge Pump Capacitor — Connects from ground to V SS. Suggested ca- pacitor size is 22µF, 16V. Pins 26 and 30 — C 1 + and C1 – — Charge Pump Capacitor — Connects from C 1 + to C1 –. Sug- gested capacitor size is 22 µF, 16V. Pins 28 and 31 — C 2 + and C2 – — Charge Pump Capacitor — Connects from C 2 + to C2 –. Sug- gested capacitor size is 22 µF, 16V. Pin 45 — RL(b) — Remote Loopback; analog output, non-inverted; sourced from RL. Pin 47 — RL(a) — Remote Loopback; analog output inverted; sourced from RL. Pin 49— LL(b) — Local Loopback; analog output, non-inverted; sourced from LL. Pin 51 — LL(a) — Local Loopback; analog output, inverted; sourced from LL. Pin 52 — RS(b) — Ready To Send; analog output, non-inverted; sourced from RTS. Pin 54 — RS(a) — Ready To Send; analog output, inverted; sourced from RTS. Pin 56 — TR(b) — Terminal Ready; analog output, non-inverted; sourced from DTR. Pin 58 — TR(a) — Terminal Ready; analog output, inverted; sourced from DTR. Pin 66 — CS(a)— Clear To Send; analog input, inverted; source for CTS. Pin 67 — CS(b)— Clear To Send; analog input, non-inverted; source for CTS. Pin 68 — DM(a)— Data Mode; analog input, inverted; source for DSR. Pin 69 — DM(b)— Data Mode; analog input, non-inverted; source for DSR Pin 78 — DSR— Data Set Ready; TTL output; sourced from DM(a), DM(b) inputs. Pin 80 — CTS— Clear To Send; TTL output; sourced from CS(a) and CS(b) inputs. CONTROL REGISTERS Pins 2 — SDEN — Enables TxD driver, active low; TTL input. Pins 3 — TREN — Enables DTR driver, active low; TTL input. Pins 4 — RSEN — Enables RTS driver, active low; TTL input. Pins 5 — LLEN — Enables LL driver, active low; TTL input. Pin 6 — TTEN — Enables TT driver, active low; TTL input.

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation requirements of ±1.5V minimum differential output levels with a 54 Ω load. The driver is designed to operate over a common mode range of +12V to -7V, which follows the RS-485 specification. This also covers the +7V to -7V common mode range for V.11 (RS-422) re- quirements. The V.11 drivers are used in RS- 449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data signals. V.35 Drivers The fourth type of driver is the V.35 driver. These drivers were specifically designed to com- ply with the requirements of V.35. Unique to the industry, the Sipex's V.35 driver architec- ture used in the SP505 does not need external termination resistors to operate and comply with V.35. This simplifies existing V.35 implemen- tations that use external termination schemes. The V.35 drivers can produce +0.55V driver output signals with minimum deviation (maxi- mum 20%) given an equivalent load of 100 Ω. With the help of internal resistor networks, the drivers achieve the 50Ω to 150Ω source imped- ance and the 135Ω to 165Ω short-circuit imped- ance for V.35. The V.35 driver is disabled and transparent when the decoder is in all other modes. All of the differential drivers; V.11 (RS- 422) and V.35, can operate over 10Mbps. Driver Enable and Input All the drivers in the SP505 contain individual enable lines which can tri-state the driver out- puts when a logic "1" is applied. This simplifies half-duplex configurations for some applica- tions and also provides simpler DTE/DCE flexibility with one integrated circuit. The driver inputs are both TTL or CMOS compatible. Each driver input should have a pull-down or pull-up resistor so that the output will be at a defined state. Unused driver inputs should not be left floating. Receivers The SP505 has seven (7) independent receivers which can be programmed for the different interface modes. Control for the mode selection is done via a 4–bit control word, which is the same as the driver's 4-bit control word. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous Drivers The SP505 has seven (7) enhanced independent drivers. Control for the mode selection is done via a four–bit control word. The drivers are prearranged such that for each mode of opera- tion, the relative position and functionality of the drivers are set up to accommodate the se- lected interface mode. As the mode of the driv- ers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. Table 1 shows the mode of each driver in the different interface modes that can be selected. There are four basic types of driver circuits — V.28 Drivers The V.28 drivers output single–ended signals with a minimum of +5V (with 3kΩ & 2500pF loading), and can operate to at least 120kbps under full load. Since the SP505 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 drivers are used in RS-232 mode for all signals, and also in V.35 mode where four (4) drivers are used as the control line signals (DTR, RTS, LL, and RL). V.10 Drivers The V.10 (RS-423) drivers are also single– ended signals which produce open circuit V OL and V OH measurements of +4.0V to +6.0V. When terminated with a 450 Ω load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category II signals from each of their corresponding specifications. V.11 Drivers The third type of driver is a V.11 (RS-422) type differential driver. Due to the nature of differ- ential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain typically +2.2V differ- ential output levels with a load of 100 Ω. The signal levels and drive capability of these driv- ers allow the drivers to also support RS-485

interface modes that can be selected. mode for all data, clock and control signals. receivers can operate to at least 120kbps. indicated by their corresponding specifications. which complies with the V.11 specification. signals not covered by Category II V.10 circuits. approximately 10kΩ during tri-state. Figure 51. Simplified RIN Termination Circuit

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation All receivers include a fail-safe feature that outputs a logic "1" when the receiver inputs are open. The differential receivers allocated for data and clock signals (RxD, RxC, and SCT) have advanced fail-safe that outputs a logic "1" when the inputs are either open, shorted, or terminated. Other discrete or integrated imple- mentations require external pull-up and pull- down resistors to define the receiver output state. For single-ended V.28 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. The single-ended V.10 receivers pro- duce a logic LOW ("0") on the output when the inputs are open. This is due to an internal pull- up device connected to the input. The differen- tial receivers have the same internal pull-up device on the non-inverting input which pro- duces a logic HIGH ("1") at the receiver output, representing an "OFF" state to the HDLC con- troller. The three differential receivers when configured in V.35 mode (RxD, RxC & SCT) will also include fail-safe even when the internal termination resistor network is connected and the inputs are either shorted or floating. Decoder The SP505 has the ability to change the inter- face mode of the drivers or receivers via a 4–bit switch. The decoder for the drivers and receiv- ers can be latched through a control pin. The control word can be latched either high or low to write the appropriate code into the SP505 . The codes shown in Tables 1 and 2 are the only specified, valid modes for the SP505 . Unde- fined codes may represent other interface modes not specified (consult the factory for more infor- mation). The drivers and receivers are con- trolled with the data bits labeled DEC 3–DEC0. All of the drivers outputs and receiver outputs can be put into tri-state mode by writing 0000 to the driver decode switch. All internal termina- tion networks are switched off during this mode. Individual tri-state capability is possible for all drivers through each driver's own enable control input. The SCT receiver also contains an indi- vidual enable input. When this control pin is disabled (logic "0"), the V.11 and V.35 input termination is deactivated. The 0000 decoder word will override the enable control line for the one receiver (SCT). The SP505 contains internal loopback capabili- ties for self-diagnostic tests. Loopback is en- abled through the decoder. To initiate single- ended mode loopback, the decoder word is 1010. To initiate differential mode loopback, the de- coder word is 1011. The minimum transmission rates into the SP505 under loopback conditions are 120kbps for single-ended mode and 5Mbps for differential mode. The driver outputs are tri- stated and the receiver inputs are disabled dur- ing loopback. The receiver input impedance during loopback is approximately 10k Ω. The SP505 is equipped with a latch control for the four (4) decoder bits. The latch control pin is pin 8 of the SP505 . The latch control is active low, a logic low on pin 8 will latch the decoder signals. A logic "1" on pin 8 will force the latch to be transparent to the user. A pulse width of at least 30ns is required to latch the decoder for the next mode. The resultant output is typically 600ns after the latch control pin is toggled assuming that the decoder word is set. NET1/2 & TBR2 European Compliancy As with all of Sipex's previous multi-protocol serial transceiver ICs, the drivers and receivers have been designed to meet all the requirements to NET1/2. The SP505 is internally tested to all the NET1/2 physical layer testing parameters and the ITU Series V specifications. With the emergence of ETSI TBR2 (Technical Basis for Regulation) document now in place as an alternative for European compliancy, Sipex has tested the SP505 to TBR2 specifications to ensure "CE" approval for either testing method. The SP505 was externally tested by TUV Telecom Services, Division of TUV Rheinland, and passed both NET1/2 and TBR2 require- ments. Test reports (NET2/052101/98 for NET1/2 and CTR2/ 05101/98 for TBR2) can be furnished upon request. Please note that although the SP505 adheres to NET1/2 testing; any complex or unusual con- figuration should be double-checked to ensure NET compliance. Consult factory for details.

Table 1. SP505 Driver Decoder Table Table 2. SP505 Receiver Decoder Table

Figure 52. SP505 Typical Operating Circuit

14 TxD

2 SDEN

23 STEN

15 TxC

6 TTEN

13 DTR

3 TREN

16 RTS

4 RSEN

18 RLEN

5 LLEN

Figure 53. Mode Diagram — RS-232

Figure 54. Mode Diagram — V.35

Figure 55. Mode Diagram — RS-422

Figure 56. Mode Diagram — RS-449

Figure 57. Mode Diagram — RS-422 w/o termination

Figure 58. Mode Diagram — EIA-530

Figure 59. Mode Diagram — EIA-530A

Figure 60. Mode Diagram — V.36

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation LOOPBACK MODE... The SP505 is equipped with two loopback modes. Single-ended loopback internally connects V.28 driver outputs to V.28 receiver inputs. The signal path is non-inverting and will support data rates up to 120kbps. The propaga- tion delay times are as specified in the electrical specifications. To initiate a single-ended loopback, the code "1010" should be written to the driver decoder. Differential loopback is implemented by applying "1011" to the driver decoder. This internally connects V.11 driver outputs to V.11 receiver inputs. The signal path again is non-inverting; the differential loopback data rate can be at least 5Mbps. Under loopback conditions the receiver decoder is disabled. While the SP505 is in either single- ended or differential loopback mode, the driver outputs are tri-stated and the receiver inputs are disabled. Mode Driver Output Receiver Input Driver Receiver non-inverting inverting non-inverting inverting Input Output Loopback tri-state tri-state >10K to GND >10K to GND active active tri-state tri-state >10K to GND >10K to GND active active Power down clamped tri-state tri-state >10K to GND >10K to GND inactive at ±0.6V Tri-state tri-state tri-state >10K to GND >10K to GND inactive tri-state DEC=1010 DEC=1011 VCC =V DD =VSS =0V DEC=0000 MODE: Differential Loopback DRIVER/RECEIVER DEC 3 DEC2 DEC1 DEC0 RD(a) 70 RxD 1 R T(a) 37 RxC 20 SCT(a) 76 SCT 79 SCTEN 7 SCT(b) 77 CS(a) 66 CTS 80 RR(a) 35 DCD 19 RR(b) 36 CS(b) 67 R T(b) 38 RD(b) 71 1 0 1 1 24 LL IC(a) 39 RI 21 IC(b) 40 DM(a) 68 DSR 78 DM(b) 69 IC(a) 39 RI 21 SCTEN 7 RECEIVERS DRIVERS 1 0 1 0 24 LL DM(a) 68 DSR 78 RR(a) 35 DCD 19 CS(a) 66 CTS 80 RD(a) 70 RxD 1 RT(a) 37 RxC 20 SCT(a) 76 SCT 79 MODE: Single-Ended Loopback DRIVER/RECEIVER DEC 3 DEC2 DEC1 DEC0

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation

80 PIN MQFP (MS-022 BC)

5°-16° 0° MIN. 0°–7° 5°-16° L 0.30" RAD. TYP . 0.20" RAD. TYP . c PIN 1 D CL E CL DIMENSIONS Minimum/Maximum (mm) SYMBOL A b D E e N 80–PIN MQFP JEDEC MS-22 (BEC) Variation MIN NOM MAX 2.45 0.00 0.25 1.80 2.00 2.20 0.22 0.40

17.20 BSC

14.00 BSC

12.35 REF

0.65 BSC

c 0.11 23.00 L 0.73 0.88 1.03 L1 1.60 BASIC PACKAGE: 80 PIN MQFP

Rev: A Date: 1/27/04 SP505 Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation

ORDERING INFORMATION

Model Temperature Range Package Types Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office

233 South Hillview Drive

Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office

22 Linnell Circle

Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Please consult the factory for pricing and availability on a Tape-On-Reel option. DATE REVISION DESCRIPTION 1/27/04 A Implemented tracking revision.

REVISION HISTORY