SP3508EF

SP3508 SIPEX | Alldatasheet

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Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation

FEATURES

■ Fast 20Mbps Differential Transmission Rates ■ Internal Transceiver Termination Resistors for V.11 & V.35 ■ Interface Modes: (V.10 & V.11) ■ Protocols are Software Selectable with 3-Bit Word ■ Eight (8) Drivers and Eight (8) Receivers ■ Termination Network Disable Option ■ Internal Line or Digital Loopback for Diagnostic Testing ■ Adheres to NET1/NET2 and TBR-2 Compliancy Requirements ■ Easy Flow-Through Pinout ■ +3.3V Only Operation ■ Individual Driver and Receiver Enable/Disable Controls ■ Operates in either DTE or DCE Mode SP3508 Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors

DESCRIPTION

The SP3508 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP3508 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex regulated charge pump allowing +3.3V only operation. Sipex's patented charge pump provides a regulated output of +5.5V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. All necessary termination is integrated within the SP3508 and is switchable when V.35 drivers and V.35 receivers, or when V.11 receivers are used. The SP3508 provides the controls and transceiver availability for operating as either a DTE or DCE. Additional features with the SP3508 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP3508 also includes a latch enable pin with the driver and receiver address decoder. The internal V.11 or V.35 termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP3508 include separate enable pins for added convenience. The SP3508 is ideal for WAN serial ports in networking equipment such as routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices. Applicable U.S. Patents-5,306,954; and others patents pending PRELIMINARY

APPLICATIONS

■ Router ■ Frame Relay ■ CSU ■ DSU ■ PBX ■ Secure Communication Terminals Now Available in Lead Free Packaging Refer to page 9 for pinout

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating temperature range (-40°C to +85°C), unless otherwise specified. Input Voltages: Output Voltages: (derate 19.0mW/°C above +70°C) Due to the relatively large package size of the 100-pin quad flat- pack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within Package Derating: These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ABSOLUTE MAXIMUM RATINGS 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order to remove moisture prior to soldering. Sipex ships the 100-pin LQFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH. STORAGE CONSIDERATIONS RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC STUPNICIGOL STUPTUOCIGOL V HO V CC - 6.0 V CC - )stuptuO(sretemaraPCDREVIRD82.V stuptuO egatloVtiucriCnepO5 1± ♦♦♦♦♦ V1 erugiFrep egatloVdedaoL0 .5±5 1± ♦♦♦♦♦ V2 erugiFrep tnerruCtiucriC-trohS0 01± ♦♦♦♦♦ Am4 erugiFrep ecnadepmIffO-rewoP0 03 ♦♦♦♦♦Ω 5erugiFrep )stuptuO(sretemaraPCAREVIRD82.V V CC sretemarapCArofV3.3+= emiTnoitisnarT5 .1 ♦♦♦♦♦ sµV 3-otV3+,6erugiFrep etaRwelSsuoenatnatsnI0 3s µ/V3 erugiFrep t:yaleDnoitagaporP LHP 5.00 .10 .3 ♦♦♦♦♦ sµ t:yaleDnoitagaporP HLP 5.00 .10 .3 ♦♦♦♦♦ sµ etaRnoissimsnarT.xaM0 210 32 ♦♦♦♦♦ spbk

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating temperature range (-40°C to +85°C), unless otherwise specified. RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC )stupnI(sretemaraPCDREVIECER82.V ecnadepmItupnI3 7 ♦♦♦♦♦ kΩ 7erugiFrep saiBtiucriC-nepO0 .2+ ♦♦♦♦♦ V8 erugiFrep dlohserhTHGIH7 .10 .3 ♦♦♦♦♦ V dlohserhTWOL8 .02 .1 ♦♦♦♦♦ V sretemaraPCAREVIECER82.V V CC sretemarapCArofV3.3+= t:yaleDnoitagaporP LHP 0010 05s n t:yaleDnoitagaporP HLP 0010 05s n etaRnoissimsnarTxaM0 215 32s pbk )stuptuO(sretemaraPCDREVIRD01.V egatloVtiucriCnepO0 .4±0 .6± ♦♦♦♦♦ V9 erugiFrep egatloVdetanimreT-tseTV 9.0 CO V0 1erugiFrep tnerruCtiucriC-trohS0 51±A m1 1erugiFrep tnerruCffO-rewoP0 01± ♦♦♦♦♦ Aµ2 1erugiFrep )stuptuO(sretemaraPCAREVIRD01.V V CC sretemarapCArofV3.3+= emiTnoitisnarT0 02 ♦♦♦♦♦ sn% 09ot%01;31erugiFrep t:yaleDnoitagaporP LHP 0010 05 ♦♦♦♦♦ sn t:yaleDnoitagaporP HLP 0010 05 ♦♦♦♦♦ sn etaRnoissimsnarTxaM0 21 ♦♦♦♦♦ spbk )stupnI(sretemaraPCDREVIECER01.V tnerruCtupnI5 2.3-5 2.3+A m5 1dna41serugiFrep sretemaraPCAREVIECER01.V V CC sretemarapCArofV3.3+= t:yaleDnoitagaporP LHP 0210 52 ♦♦♦♦♦ sn t:yaleDnoitagaporP HLP 0210 52 ♦♦♦♦♦ sn etaRnoissimsnarTxaM0 21 ♦♦♦♦♦ spbk

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating temperature range (-40°C to +85°C), unless otherwise specified. RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC )stuptuO(sretemaraPCDREVIRD11.V V(egatloVtiucriCnepO CO )0 .6± ♦♦♦♦♦ V6 1erugiFrep egatloVdetanimreTtseT0 .2± ♦♦♦♦♦ V7 1erugiFrep ecnalaB4 .0±V 7 1erugiFrep tesffO0 .3+ ♦♦♦♦♦ V7 1erugiFrep tnerruCtiucriC-trohS0 51± ♦♦♦♦♦ Am8 1erugiFrep tnerruCffO-rewoP0 01± ♦♦♦♦♦ Aµ9 1erugiFrep )stuptuO(sretemaraPCAREVIRD11.V V CC sretemarapCArofV3.3+= emiTnoitisnarT0 1 ♦♦♦♦♦ sn ot%01;53dna12serugiFrep ;Fp05=LCgnisU%09 t:yaleDnoitagaporP LHP 030 6 ♦♦♦♦♦ sn5 3dna23serugiFrep t:yaleDnoitagaporP HLP 030 6 ♦♦♦♦♦ sn5 3dna23serugiFrep wekSlaitnereffiD5 0 1 ♦♦♦♦♦ sn5 3dna23serugiFrep etaRnoissimsnarT.xaM0 2 ♦♦♦♦♦ spbM )stupnI(sretemaraPCDREVIECER11.V egnaRedoMnommoC7 -7 + ♦♦♦♦♦ V tnerruCtupnI5 2.3-5 2.3± Am ronorewop;22dna02erugiFrep ffo Ω001/wtnerruC noitanimreT -7.06±

5 Am 42dna32erugiFrep

sretemaraPCAREVIECER11.V V CC sretemarapCArofV3.3+= Fp05=LCgnisU t:yaleDnoitagaporP LHP 030 6s n7 3dna23serugiFrep t:yaleDnoitagaporP HLP 030 6s n7 3dna23serugiFrep wekS5 0 1s n2 3erugiFrep etaRnoissimsnarTxaM0 2s pbM

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating temperature range (-40°C to +85°C), unless otherwise specified. RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC )stuptuO(sretemaraPCDREVIRD53.V egatloVtiucriCnepO0 2.1±V 6 1erugiFrep egatloVdetanimreTtseT4 4.0±6 6.0±V 5 2erugiFrep tesffO6 .0± ♦♦♦♦♦ V5 2erugiFrep toohsrevOtuptuO- V2.0- TS -2.0+ V TS ♦♦♦♦♦ V V;52erugiFrep TS etatsydaetS= eulav ecnadepmIecruoS0 50 51 ♦♦♦♦♦Ω Z;62erugiFrep S V= 2 V/ 1 05x ecnadepmItiucriC-trohS5 315 61 Ω 72erugiFrep )stuptuO(sretemaraPCAREVIRD53.V V CC sretemarapCArofV3.3+= emiTnoitisnarT0 2 ♦♦♦♦♦ sn t:yaleDnoitagaporP LHP 030 6 ♦♦♦♦♦ snC ;53dna23serugiFrep L Fp02= t:yaleDnoitagaporP HLP 030 6 ♦♦♦♦♦ snC ;53dna23serugiFrep L Fp02= wekSlaitnereffiD5 ♦♦♦♦♦ snC ;53dna23serugiFrep L Fp02= etaRnoissimsnarT.xaM0 2 ♦♦♦♦♦ spbM )stupnI(sretemaraPCDREVIECER53.V ecnadepmIecruoS0 90 11 Ω Z;92erugiFrep S V= 2 V/ 1 05x Ω ecnadepmItiucriC-trohS5 315 61 Ω 03erugiFrep sretemaraPCAREVIECER53.V V CC sretemarapCArofV5+= t:yaleDnoitagaporP LHP 030 6s nC ;73dna23serugiFrep L Fp02= t:yaleDnoitagaporP HLP 030 6s nC ;73dna23serugiFrep L Fp02= wekS5 0 1s nC ;23serugiFrep L Fp02= etaRnoissimsnarT.xaM0 2s pbM STNERRUCEGAKAELREVIECSNART tnerruCetatS-3tuptuOrevirD0 02A µd elbasidsrevirD;13erugiFrep etatS-3tuptuOrevieceR tnerruC 10 1 Aµ DX 111=

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating temperature range (-40°C to +85°C), unless otherwise specified. RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC STNEMERIUQERREWOP V CC 51.33 .35 4.3V I CC )detceleSedoMoN(1 ♦♦♦♦♦ AµI llA CC Vhtiweraseulav CC V3.3+= )232-SR/82.V5 9 ♦♦♦♦♦ Am f NI &evitcasrevirD;spbk032= dedaol )224-SR/11.V(0 32 ♦♦♦♦♦ Amf NI dedaol&evitcasrevirD;spbM02= )944-SR&035-AIE(0 72 ♦♦♦♦♦ Amf NI dedaol&evitcasrevirD;spbM02= )53.V(0 71 ♦♦♦♦♦ Am If@53.V N @82.V,spbM02= spbk032

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation OTHER AC CHARACTERISTICS TA = 0 to 70°C and VCC = +3.3V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.70 5.0 µsC L = 100pF, Fig. 33 & 39; S1 closed tPZH; Tri-state to Output HIGH 0.40 2.0 µsC L = 100pF, Fig. 33 & 39; S2 closed tPLZ; Output LOW to Tri-state 0.20 2.0 µsC L = 100pF, Fig. 33 & 39; S1 closed tPHZ; Output HIGH to Tri-state 0.40 2.0 µsC L = 100pF, Fig. 33 & 39; S2 closed RS-423/V.10 tPZL; Tri-state to Output LOW 0.15 2.0 µsC L = 100pF, Fig. 33 & 39; S1 closed tPZH; Tri-state to Output HIGH 0.20 2.0 µsC L = 100pF, Fig. 33 & 39; S2 closed tPLZ; Output LOW to Tri-state 0.20 2.0 µsC L = 100pF, Fig. 33 & 39; S1 closed tPHZ; Output HIGH to Tri-state 0.15 2.0 µsC L = 100pF, Fig. 33 & 39; S2 closed RS-422/V.11 tPZL; Tri-state to Output LOW 2.80 10.0 µsC L = 100pF, Fig. 33 & 36; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 33 & 36; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 33 & 36; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 33 & 36; S2 closed V.35 tPZL; Tri-state to Output LOW 2.60 10.0 µsC L = 100pF, Fig. 33 & 36; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 33 & 36; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 33 & 36; S1 closed tPHZ; Output HIGH to Tri-state 0.15 2.0 µsC L = 15pF, Fig. 33 & 36; S2 closed RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.12 2.0 µsC L = 100pF, Fig. 34 & 37; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S2 closed RS-423/V.10 tPZL; Tri-state to Output LOW 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC L = 100pF, Fig. 34 & 37; S2 closed

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation OTHER AC CHARACTERISTICS: Continued TA = 0 to 70°C and VCC = +3.3V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS RS-422/V.11 tPZL; Tri-state to Output LOW 0.10 2.0 µsC L = 100pF, Fig. 34 & 38; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 34 & 38; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 34 & 38; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 34 & 38; S2 closed V.35 tPZL; Tri-state to Output LOW 0.10 2.0 µsC L = 100pF, Fig. 34 & 38; S1 closed tPZH; Tri-state to Output HIGH 0.10 2.0 µsC L = 100pF, Fig. 34 & 38; S2 closed tPLZ; Output LOW to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 34 & 38; S1 closed tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC L = 15pF, Fig. 34 & 38; S2 closed TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 32, 35, 37) RS-232 Driver 100 ns [ (t phl )Tx1 – (tphl )Txn ] 100 ns [ (t plh )Tx1 – (tplh )Txn] RS-232 Receiver 20 ns [ (t phl )Rx1 – (tphl )Rxn ] 20 ns [ (t phl )Rx1 – (tphl )Rxn ] RS-422 Driver 2 ns [ (t phl )Tx1 – (tphl )Txn ] 2n s [ ( t plh )Tx1 – (tplh )Txn ] RS-422 Receiver 3 ns [ (t phl )Rx1 – (tphl )Rxn ] 3n s [ ( t phl )Rx1 – (tphl )Rxn ] RS-423 Driver 5 ns [ (t phl )Tx2 – (tphl )Txn ] 5n s [ ( t plh )Tx2 – (tplh )Txn ] RS-423 Receiver 5 ns [ (t phl )Rx2 – (tphl )Rxn ] 5n s [ ( t phl )Rx2 – (tphl )Rxn ] V.35 Driver 4 ns [ (t phl )Tx1 – (tphl )Txn ] 4n s [ ( t plh )Tx1 – (tplh )Txn ] V.35 Receiver 6 ns [ (t phl )Rx1 – (tphl )Rxn ] 6n s [ ( t phl )Rx1 – (tphl )Rxn]

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation PINOUT GND 1 SDEN 2 TTEN 3 STEN 4 RSEN 5 TREN 6 RRCEN 7 RLEN 8 LLEN 9 RDEN 10 RTEN 11 TXCEN 12 CSEN13 DMEN 14 RRTEN 15 ICEN 16 TMEN 17 D0 18 D1 19 D2 20 D_LATCH 21 TERM_OFF 22 VCC 23 C3P 24 GND 25 C3N 26 VSS2 27 AGND 28 AVCC 29 LOOPBACK 30 TXD 31 TXCE 32 ST 33 RTS 34 DTR 35 DCD_DCE 36 RL 37 LL 38 RXD 39 RXC 40 TXC 41 CTS 42 DSR 43 DCD_DTE 44 RI 45 TM 46 GND 47 VCC 48 RD(b) 49 RD(a) 50

75 GND

74 C1P

73 VCC

72 C2P

71 GND

70 C1N

69 C2N

68 VSS1

67 RL(a)

66 VCC

65 LL(a)

64 TM(a)

62 RRT(a)

61 RRT(b)

60 GNDV10

59 DM(a)

58 DM(b)

57 CS(a)

56 CS(b)

55 TXC(a)

54 GND

53 TXC(b)

52 RT(a)

51 RT(b)

100 VCC

99 SD(b)

98 VCC

97 SD(a)

96 GND

95 TT(b)

94 VCC

93 TT(a)

92 GND

91 ST(b)

90 VCC

89 ST(a)

88 GND

87 TR(b)

86 VCC

85 TR(a)

84 GND

83 RS(b)

82 VCC

81 RS(a)

80 GND

79 RRC(a)

78 VCC

77 RCC(b)

76 VDD

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation SP3508 Pin Designation Pin Number Pin Name Description Pin Number Pin Name Description

1 GND Signal Ground 51 RT(B) RxC Non-Inverting Input

2 SDEN TxD Driver Enable Input 52 RT(A) RxC Inverting Input

3 TTEN TxCE Driver Enable Input 53 TxC(B) TxC Non-Inverting Input

4 STEN ST Driver Enable Input 54 GND Signal Ground

5 RSEN RTS Driver Enable Input 55 TxC(A) TxC Inverting Input

6 TREN DTR Driver Enable Input 56 CS(B) CTS Non-Inverting Input

7 RRCEN DCD Driver Enable Input 57 CS(A) CTS Inverting Input

8 RLEN RL Driver Enable Input 58 DM(B) DSR Non-Inverting Input

9 LLEN LL Driver Enable Input 59 DM(A) DSR Inverting Input

10 RDEN RxD Receiver Enable Input 60 GNDV10 V.10 Rx Reference Node

11 RTEN RxC Receiver Enable Input 61 RRT(B) DCD DTE Non-Inverting Input

12 TxCEN TxC Receiver Enable Input 62 RRT(A) DCD DTE Inverting Input

13 CSEN CTS Receiver Enable Input 63 IC RI Receiver Input

14 DMEN DSR Receiver Enable Input 64 TM(A) TM Receiver Input

15 RRTEN DCD DTE Receiver Enable Input 65 LL(A) LL Driver Output

16 ICEN RI Receiver Enable Input 66 VCC Power Supply Input

17 TMEN TM Receiver Enable Input 67 RL(A) RL Driver Output

18 D0 Mode Select Input 68 VSS1 -2xVCC Charge Pump Output

19 D1 Mode Select Input 69 C2N Charge Pump Capacitor

20 D2 Mode Select Input 70 C1N Charge Pump Capacitor

21 D_LATCH Decoder Latch Input 71 GND Signal Ground

22 TERM_OFF Termination Disable Input 72 C2P Charge Pump Capacitor

23 VCC Power Supply Input 73 VCC Power Supply Input

24 C3P Charge Pump Capacitor 74 C1P Charge Pump Capacitor

25 GND Signal Ground 75 GND Signal Ground

26 C3N Charge Pump Capacitor 76 VDD 2xVCC Charge Pump Output

27 VSS2 Minus VCC 77 RRC(B) DCD DCE Non-Inverting Output

28 AGND Signal Ground 78 VCC Power Supply Input

29 AVCC Power Supply Input 79 RRC(A) DCD DCE Inverting Output

30 LOOPBACK Loopback Mode Enable Input 80 GND Signal Ground

31 TxD TxD Driver TTL Input 81 RS(A) RTS Inverting Output

32 TxCE TxCE Driver TTL Input 82 VCC Power Supply Input

33 ST ST Driver TTL Input 83 RS(B) RTS Non-Inverting Output

34 RTS RTS Driver TTL Input 84 GND Signal Ground

35 DTR DTR Driver TTL Input 85 TR(A) DTR Inverting Output

36 DCD_DCE DCD DCE Driver TTL Input 86 VCC Power Supply Input

37 RL RL Driver TTL Input 87 TR(B) DTR Non-Inverting Output

38 LL LL Driver TTL Input 88 GND Signal Ground

39 RxD RxD Receiver TTL Output 89 ST(A) ST Inverting Output

40 RxC RxC Receiver TTLOutput 90 VCC Power Supply Input

41 TxC TxC Receiver TTL Output 91 ST(B) ST Non-Inverting Output

42 CTS CTS Receiver TTL Output 92 GND Signal Ground

43 DSR DSR Receiver TTL Output 93 TT(A) TxCE Inverting Output

44 DCD_DTE DCD DTE Receiver TTL Output 94 VCC Power Supply Input

45 RI RI Receiver TTL Output 95 TT(B) TxCE Non-Inverting Output

46 TM TM Receiver TTL Output 96 GND Signal Ground

47 GND Signal Ground 97 SD(A) TxD Inverting Output

48 VCC Power Supply Input 98 VCC Power Supply Input

49 RD(B) RXD Non-Inverting Input 99 SD(B) TxD Non-Inverting Output

50 RD(A) RXD Inverting Input 100 VCC Power Supply Input

Table 1. Driver Mode Selection Table 2. Receiver Mode Selection

Figure 44. Functional Diagram

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation The SP3508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP3508 offers the hardware interface modes for RS-232 (V.28), RS-449/V.36 (V.11 and V.10), EIA-530 (V.11 and V.10), EIA-530A (V.11 and The interface mode selection is done via three control pins, which can be latched via micropro- cessor control. The SP3508 has eight drivers, eight receivers, and Sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. Other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail- safe when inputs are either open or shorted. THEORY OF OPERATION The SP3508 device is made up of 1) the drivers 2) the receivers 3) charge pumps 4) DTE/DCE switching algorithm 5) control logic. Drivers The SP3508 has eight enhanced independent drivers. Control for the mode selection is done via a three-bit control word into D0, D1, and D2. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accom- modate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the re- quired signal levels. The mode of each driver in the different interface modes that can be se- lected is shown in Table 1. There are four basic types of driver circuits – ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423), ITU-T-V.11 (RS-422), and CCITT-V.35. The V.28 (RS-232) drivers output single-ended signals with a minimum of +5V (with 3k Ω & 2500pF loading), and can operate over 120kbps. Since the SP3508 uses a charge pump to gener- ate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 driver archi- tecture is similar to Sipex's standard line of RS- 232 transceivers. The RS-423 (V.10) drivers are also single-ended signals which produce open circuit V OL and VOH measurements of +4.0V to +6.0V. When terminated with a 450 Ω load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 (RS-423) drivers are used in RS-449/V.36, EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. The V.10 driver can transmit over 120Kbps if neces- sary. The third type of drivers are V.11 (RS-422) differential drivers. Due to the nature of differ- ential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential out- put levels with a load of 100 Ω. The strength allows the SP3508 differential driver to drive over long cable lengths with minimal signal degradation. The V.11 drivers are used in RS- 449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. Sipex's new driver design over its prede- cessors allow the SP3508 to operate over 20Mbps for differential transmission.

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation The fourth type of drivers are V.35 differential drivers. There are only three available on the SP3508 for data and clock (TxD, TxCE, and TxC in DCE mode). These drivers are current sources that drive loop current through a differential pair resulting in a 550mV differential voltage at the receiver. These drivers also incorporate fixed termination networks for each driver in order to set the V OH and VOL depending on load conditions. This termination network is basically a “Y” configuration consisting of two 51 Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors to GND. Filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. The drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable DTE/DCE. The enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on Figure 44. The enable pins have internal pull-up and pull- down devices, depending on the active polarity of the receiver, that enable the driver upon power- on if the enable lines are left floating. During disabled conditions, the driver outputs will be at a high impedance 3-state. The driver inputs are both TTL or CMOS compatible. All driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic LOW (“0”). Unused driver inputs can be left floating. The internal pull-up resistor value is approximately 500kΩ. Receivers The SP3508 has eight enhanced independent receivers. Control for the mode selection is done via a three-bit control word that is the same as the driver control word. Therefore, the modes for the drivers and receivers are identical in the application. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. Table 1 shows the mode of each receiver in the different interface modes that can be selected. There are two basic types of receiver circuits—ITU-T-V .28 (RS-232) and ITU-T-V.11, (RS-422). The RS-232 (V.28) receiver is single-ended and accepts RS-232 signals from the RS-232 driver. The RS-232 receiver has an operating input voltage range of +15V and can receive signals downs to +3V. The input sensitivity complies with RS-232 and V.28 at +3V. The input impedance is 3kΩ to 7kΩ in accordance to RS- 232 and V.28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic “1” and a +0.4V maximum for a logic “0”. The RS-232 (V.28) protocol uses these receivers for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate over 120kbps. The second type of receiver is a differential type that can be configured internally to support ITU-T-V.10 and CCITT-V.35 depending on its input conditions. This receiver has a typical input impedance of 10k Ω and a differential threshold of less than +200mV, which complies with the ITU-T-V.11 (RS-422) specifications. V.11 receivers are used in RS-449/V.36, EIA-530, EIA-530A and X.21 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential V.11 transceiver has improved architecture that allows over 20Mbps transmission rates. Receivers dedicated for data and clock (RxD, RxC, TxC) incorporate internal termination for V.11. The termination resistor is typically 120Ω connected between the A and B inputs. The termination is essential for minimizing crosstalk and signal reflection over the transmission line . The minimum value is guaranteed to exceed 100Ω, thus complying with the V.11 and RS-422 specifications. This resistor is invoked when the receiver is operating as a V.11 receiver, in modes EIA-530, EIA-530A, RS-449/V.36, and X.21.

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation The same receivers also incorporate a termination network internally for V.35 applications. For V.35, the receiver input termination is a “Y” termination consisting of two 51 Ω resistors connected in series and a 124Ω resistor connected between the two 50 Ω resistors and GND. The receiver itself is identical to the V.11 receiver. The differential receivers can be configured to be ITU-T-V.10 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V10GND and can be grounded separately. The ITU-T-V.10 receivers can operate over 120Kbps and are used in RS-449/V.36, E1A- 530, E1A-530A and X.21 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/ disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on Figure 44. The receiver’s enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs. All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. For single-ended V.28 and V.10 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high (“1”) at the receiver outputs. The differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic HIGH (“1”) at the receiver output. CHARGE PUMP SP3508 uses an internal capacitive charge pump to generate Vdd and Vss. The design is Sipex patented (5,306,954) four-phased voltage shift- ing charge pump converters that converts the input voltage of 3.3V to nominal output volt- ages of +/-6V (Vdd & Vss1). SP3508 also in- cludes an inverter block that inverts Vcc to -Vcc (Vss2). There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. 4-phased doubler pump Phase 1 SS1 charge storage -During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C1+ is then switched to ground and the charge in C1- is transferred to C2-. Since C2+ is connected to V CC, the voltage potential across capacitor C2 is now 2xVCC. VCC = +3V –3V –3V +3V VSS1 Storage Capacitor VDD Storage Capacitor C1 C2 ––– CVDD CVSS1 Figure 45. Charge Pump - Phase 1.

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation Recommended Signals and Port Pin Assignments Pin Number Pin Mnemonic Circuit Pin Mnemonic Pin Number Signal Type Mnemo nic DB-25 Pin(F) Signal Type Mnemo nic DB-25 Pin(F) Signal Type Mnemo nic DB-37 Pin(F) Signal Type Mnemo nic M34 Pin(F) Signal Type Mnemo nic DB-15 Pin(F) SDEN SD(B) 99 V.11 BB(B) 16 V.11 RD(B) 24 V.35 104 T V.11 R(B) 11 TTEN TT(B) 95 V.11 DD(B) 9 V.11 RT(B) 26 V.35 115 X V.11 B(B) 14** STEN ST(B) 91 V.11 DB(B) 12 V.11 ST(B) 23 V.35 114 AA V.11 S(B) 13 RSEN RS(B) 83 V.11 CB(B) 13 V.11 CS(B) 27 V.11 I(B) 12 35 DTR TR(A) 85 V.28 CC 6 V.11 CC(A) 6 V.11 DM(A) 11 V.28 107 E6 TREN TR(B) 87 V.11 CC(B) 22 V.11 DM(B) 29

36 DCD_DCE

RRC(A) 79 V.28 CF 8 V.11 CF(A) 8 V.11 RR(A) 13 V.28 109 F RRCEN RRC(B) 77 V.11 CF(B) 10 V.11 RR(B) 31 37 RL RL(A) 67 V.28 CE 22 V.28 125 J8R L E N 38 LL LL(A) 65 V.28 TM 25 V.10 TM 25 V.10 TM 18 V.28 142 NN9 LLEN# RRT(A) 62

15 RRTEN#

RRT(B) 61 SP3508 Multiprotocol Configured as DCE Interface to System Logic Interface to Port- Connector Receiver_4Receiver_5Receiver_6 Driver_7Driver_8 RS-449 V.35 X.21 Driver_1 RS-232 or V.24 EIA-530 Receiver_2Receiver_3 Driver_2Driver_3Driver_4Driver_5Receiver_1 Driver_6 Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver ** X.21 use either B() or X(), not both Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations Receiver_7Receiver_8 DCE CONFIGURATION Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiv er © Copyright 2004 Sipex Corporation

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation Recommended Signals and Port Pin Assignments Pin Number Pin Mnemonic Circuit Pin Mnemonic Pin Number Signal Type Mnemo nic DB-25 Pin(M) Signal Type Mnemo nic DB-25 Pin(M) Signal Type Mnemo nic DB-37 Pin(M) Signal Type Mnemo nic M34 Pin(M) Signal Type Mnemo nic DB-15 Pin(M) SDEN SD(B) 99 V.11 BA(B) 12 V.11 SD(B) 22 V.35 103 S V.11 T(B) 9 TTEN TT(B) 95 V.11 DA(B) 11 V.11 TT(B) 35 V.35 113 W V.11 X(B) 14**

33 ST ST(A) 894

STEN ST(B) 91 RSEN RS(B) 83 V.11 CA(B) 19 V.11 RS(B) 25 V.11 C(B) 10 35 DTR TR(A) 85 V.28 CD 20 V.11 CD(A) 20 V.11 TR(A) 12 V.28 108 H6 TREN TR(B) 87 V.11 CD(B) 23 V.11 TR(B) 30

36 DCD_DCE RRC(A) 797

RRCEN RRC(B) 77 37 RL RL(A) 67 V.28 RL 21 V.10 RL 21 V.10 RL 14 V.28 140 N8R L E N 38 LL LL(A) 65 V.28 LL 18 V.10 LL 18 V.10 LL 10 V.28 141 L9L L EN# RS-449 V.35 X.21 Receiver_7Receiver_8 RS-232 or V.24 EIA-530 Receiver_4Receiver_5Receiver_6 Driver_7Driver_8 Driver_6 Driver_2Driver_3Driver_4Driver_5 Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver ** X.21 use either B() or X(), not both Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations SP3508 Multiprotocol Configured as DTE Interface to System Logic Interface to Port- Connector Driver_1Receiver_1Receiver_2Receiver_3 DTE CONFIGURATION Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiv er © Copyright 2004 Sipex Corporation

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation TERM_OFF FUNCTION The SP3508 contains a TERM_OFF pin that dis- ables all three receiver input termination networks regardless of mode. This allows the device to be used in monitor mode applications typically found in networking test equipment. The TERM_OFF pin internally contains a pull- down device with an impedance of over 500kΩ, which will default in a "ON" condition during power-up if V.35 receivers enable line and the SHUTDOWN mode from the decoder will disable the termination regardless of TERM_OFF. LOOPBACK FUNCTION The SP3508 contains a LOOPBACK pin that invokes a loopback path. This loopback path is illustrated in Figure 50. LOOPBACK has an inter- nal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. During loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. DECODER AND D_LATCH FUNCTION The SP3508 contains a D_LATCH pin that latches the data into the D0, D1 and D2 decoder inputs. If tied to a logic LOW ("0"), the latch is transparent, allowing the data at the decoder inputs to propa- gate through and program the SP3508 accord- ingly. If tied to a logic HIGH ("1"), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic LOW. There are internal pull-up devices on D0, D1 and D2, which allow the device to be in SHUTDOWN mode ("111") upon power up. However, if the device is powered-up with the D_LATCH at a logic HIGH, the decoder state of the SP3508 will be undefined. CTR1/CTR2 EUROPEAN COMPLIANCY As with all of Sipex's previous multi-protocol serial transceiver IC's the drivers and receivers have been designed to meet all the requirements to NET1/NET2 and TBR2 in order to meet CTR1/ CTR2 compliancy. The SP3508 is also tested in- house at Sipex and adheres to all the NET1/2 physical layer testing and the ITU Series V speci- fications before shipment. Please note that al- though the SP3508, as with its predecessors, ad- here to CRT1/CTR2 compliancy testing, any com- plex or usual configuration should be double- checked to ensure CTR1/CTR2 compliance. Con- sult the factory for details.

Figure 50. Loopback Path

Figure 51. SP3508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability

• - Driver applies for DCE only on pins 15 and 12.

Receiver applies for DTE only on pins 15 and 12. I/O Lines represented by double arrowhead signifies a bi-directional bus. Driver applies for DCE only on pins 8 and 10. Receiver applies for DTE only on pins 8 and 10.

31 SD(a)

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation PACKAGE: 100 PIN LQFP

100 PIN LQFP

D CL b e Seating PlaneA1 CL E A L 11°-13° 0°MIN 0°–7° 0.2 RAD MAX. 0.08 RAD MIN. DIMENSIONS Minimum/Maximum (mm) SYMBOL A b D e E N 100–PIN LQFP JEDEC MS-026 (BED) Variation MIN NOM MAX 1.60 0.05 0.15 1.35 1.40 1.45 0.17 0.22 0.27

16.00 BSC

14.00 BSC

0.50 BSC

A c 11°-13° COMMON DIMENSIONS SYMBL MIN NOM MAX c 0.09 0.20 L 0.45 0.60 0.75 L1 1.00 REF

Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation

ORDERING INFORMATION

Part Number Temperature Range Package Types Corporation ANALOG EXCELLENCE Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. Sipex Corporation Headquarters and Sales Office

233 South Hillview Drive

Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600

REVISION HISTORY

Available in lead free packaging. To order add “-L” suffix to part number. Example: SP3508EF = standard; SP3508EF-L = lead free DATE REVISION DESCRIPTION 1/12/04 A Implemented tracking revision. 2/27/04 B Included Diamond column in spec table indicating which specs apply over full operating temp. range. In figure 51, fixed typo on pin 61 and 62 from an input line to a bidirectional bus. 3/31/04 C Corrected max dimension for symbol c on LQFP package. 6/3/04 D Added tables to page 27 and 28.