SP3203 SIPEX | Alldatasheet
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Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation 3V RS-232 Serial Transceiver with Logic Selector The SP3203 provides a RS-232 transceiver solution for portable and hand-held applications such as palmtops, PDA's and cell phones. The SP3203 uses an internal high-efficiency, charge-pump that requires only 0.1µF capacitors during 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3203 to deliver compliant RS-232 performance from a single power supply ranging from +3.0V to +5.5V. The SP3203 is a 3-driver/2-receiver device, with a unique V L pin to program the TTL input and output logic levels to allow interoperation in mixed-logic voltage systems such as PDA's and cell phones. Receiver outputs will not exceed V L for VOH and transmitter input logic levels are scaled by the magnitude of the VL input. ■ 3 Driver/ 2 Receiver Architecture ■ Logic selector function (VL) sets TTL input/output levels for mixed logic systems ■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply ■ Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source ■ Minimum 250Kbps data rate under load ■ Regulated Charge Pump Yields Stable RS-232 Outputs Regardless of VCC Variations ■ ESD Specifications: +2kV Human Body Model
DESCRIPTION
■ Applications ■ Palmtops ■ Cell phone Data Cables ■ PDA's SP3203
Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. V Input Voltages +25V otherwise noted. Typical values are at VCC = VL +3.3V, TA = +25°C.) SPECIFICATIONS Output Voltages Short-Circuit Duration Power Dissipation per Packages 20-Pin TSSOP RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC SCITSIRETCARAHCCD V( CC T,V5+roV3.3+= A 52+= o )C tnerruCylppuS3 .01A mV =nwodtuhS CC daolon, tnerruCylppuSnwodtuhS1 0 1 µA DNG=nwodtuhS STUPNICIGOL woLdlohserhTcigoLtupnI 8.0 Vn wodtuhS,NIxT VL V0.5roV3.3= 6.0V L V5.2= hgiHdlohserhTcigoLtupnI 4.2 Vn wodtuhS,NIxT VL V0.5= 0.2V L V3.3= 4.1V L V5.2= 9.0V L V8.1= sisretsyHtupnIrettimsnarT5 .0V tnerruCegakaeLtupnI1 0.0±1 ± µA nwodtuhS,NIxT STUPTUOREVIECER stnerruCegakaeLtuptuO5 0.0±0 1± µA delbasidsreviecer,TUOxR woLegatloVtuptuO4 .0V I TUO Am6.1= hgiHegatloVtuptuO VL - 6.0 VL - 1.0 VI TUO Am1-=
Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation SPECIFICATIONS (continued) otherwise noted. Typical values are at VCC = VL +3.3V, TA = +25°C.) RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC STUPNIREVIECER egnaRegatloVtupnI5 2-5 2+V woLdlohserhTtupnI 8.05 .1 VT A 52+= O C VL V0.5= 6.02 .1V L V3.3roV5.2= hgiHdlohserhTtupnI 8.14 .2 VT A 52+= O C VL V0.5= 5.14 .2V L V3.3roV5.2= siseretsyHtupnI5 .0V ecnatsiseRtupnI3 5 7 k Ω TA 52+= O C STUPTUORETTIMSNART gniwSegatloVtuptuO5 ±4 .5±V k 3htiwdedaolstuptuorettimsnartllA Ω Tot A 52= O C ecnatsiseRtuptuO0 03M 01 Ω V CC V2±=tuptuorettimsnart,0=-V=+V= tnerruCtiucriC-trohStuptuO0 6±A mV TUOxT 0= tnerruCegakaeLtuptuO5 2± µA V TUOxT ;delbasidrettimsnart,21±= V CC V5.5otV0.3ro0= Note 2. Transmitter skew is measured at the transmitter zero crosspoint. RETEMARAP. NIM. PYT. XAMS TINUS NOITIDNOC etaRataDmumixaM0 52s pbkR L k3= ,Ω C L ,Fp0001= gnihctiwsrettimsnarteno yaleDnoitagaporPrevieceR t LHP 51.0 µs tuptuoreviecerottupnirevieceR C L Fp051=t HLP 51.0 emiTelbanEtuptuOrevieceR0 02s nn oitarepolamron emiTelbasiDtuptuOrevieceR0 02s nn oitarepolamron nwodtuhStixEotemiT0 01 µs VI TUOxT V7.3>I wekSrettimsnarT It LHP t- HLP I 001s n) 2etoN( wekSrevieceR It LHP t- HLP I 05s n etaRwelSnoigeR-noitisnarT 60 3 /V µs C L Fp0001otFp051= V CC V3.3= TA 52+= oC R L k3= Ω k7ot ,Ω V3+morfderusaem V3+otV3-roV3-ot 40 3C L Fp0052otFp051=
Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation EMANN OITCNUF NIP REBMUN 3023PS +1C .1C,roticapacpmup-egrahclacirtemmysehtfolanimretevitisoP 1 +V. pmupegrahcehtybdetarenegtuptuoV5.5+detalugeR 2 -1C .1C,roticapacpmup-egrahclacirtemmysehtfolanimretevitageN 3 +2C .2C,roticapacpmup-egrahclacirtemmysehtfolanimretevitisoP 4 -2C .2C,roticapacpmup-egrahclacirtemmysehtfolanimretevitageN 5 -V. pmupegrahcehtybdetarenegtuptuoV5.5-detalugeR 6 R 1 NI. tupnireviecer232-SR 41 R 2 NI. tupnireviecer232-SR 31 R 1 TUO. tuptuoreviecerSOMC/LTT 11 R 2 TUO. tuptuoreviecerSOMC/LTT 01 T1 NI. tupnirevirdSOMC/LTT 7 T2 NI. tupnirevirdSOMC/LTT 8 T3 NI. tupnirevirdSOMC/LTT 9 T1 TUO. tuptuorevird232-SR 71 T2 TUO. tuptuorevird232-SR 61 T3 TUO. tuptuorevird232-SR 51 DNG. dnuorG 81 V CC .egatlovylppusV5.5+otV0.3+ 91 NWODTUHS. pmupegrahcdnasrevirdnwodtuhsotWOLcigolylppA 02 VL noitceleSegatloVylppuSleveL-cigoL 21
Figure 7. SP3203 Pinout Configuration
Figure 8. SP3203 Typical Operating Circuit
Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation The SP3203 is a 3-driver/2-receiver device that can be operated as a full duplex, RS-232 serial transceiver with the 3rd driver acting as a control line allowing a Ring Indicator (RI) signal to alert the UART on the PC. This transceiver meet the EIA/TIA-232 and ITU- T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers, PDA's and cell phones. The SP3203 devices feature Sipex's proprietary and patented (U.S.#5,306,954) on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3203 devices can operate at a minimum data range of 250kbps, driving a single driver. The SP3203 is a 3-driver/2-receiver device. THEORY OF OPERATION The SP3203 contains four basic circuit blocks: 1. drivers, 2. receivers, 3. a Sipex proprietary charge pump and 4. V L circuitry. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/ TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. The driver output stages are turned off (High Impedance) when the device is in shutdown mode. The drivers typically can operate at a data rate of 250Kbps. The drivers can guarantee a data rate of 120Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. The SP3203 driver can maintain high data rates up to 250Kbps with a single driver loaded. Fig- ure 9 shows a loopback test circuit used to test the RS-232 Drivers. Figure 10 shows the test results of the loopback circuit with all three drivers active at 120Kbps with typical RS-232 loads in parallel with 1000pF capacitors. Figure 11 shows the test results where one driver was active at 250Kbps and all three drivers loaded with an RS-232 receiver in parallel with a 1000pF capacitor. The transmitter inputs do not have pull-up resistors. Connect unused inputs to ground or V L Receivers The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. Receivers are disabled when in shutdown. The truth table logic of the SP3203 driver and re- ceiver outputs can be found in Table 1. Since receiver input is usually from a transmis- sion line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is immune to noisy transmission lines. Should an input be left un- connected, an internal 5KΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state. Charge Pump The charge pump is a Sipex–patented design (U.S. #5,306,954) and uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply
Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation duces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC , the voltage potential across C 2 is 2 times VCC . VDD Transfer-Phase 4 (Figure 16) The fourth phase of the clock connects the nega- tive terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the V DD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C 4, positive side of capacitor C1 is switched to VCC and the negative side is con- nected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V + and V– are separately generated from VCC , in a no–load condition, V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent ineffiencies in the design. The clock rate for the charge pump is typically operates at 250kHz. The external capacitors are usually 0.1µF with a 16V breakdown voltage rating. VL Supply Level Current RS-232 serial tranceivers are designed with fixed 5V or 3.3V TTL input/output voltages levels. The V L function in the SP3203 allows the end user to set the TTL input/output voltage levels independent of V CC . By connecting VL to the main logic bus of system, the TTL input/ output limits and threshold are reset to interface with the on board low voltage logic circuity. :elbaTnoitceleSroticapaC V CC )V(( 1C µ )F( 4C-2C µ )F 6.3ot0.31 .01 .0 5.5ot5.47 40.03 3.0 5.5ot0.32 2.01
Figure 17. Circuit for the connectivity of the SP3203 with a DB-9 connector
- Received Line Signal Detector
on all driver output and receiver input pins. accepted ESD testing method for semiconductors. Figure 18. ESD Test Circuit for Human Body Model areas where the ICs tend to be handled frequently. 15kΩ and 100pF, respectively.
Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation Gage Plane
1.0 OIA
e 0.169 (4.30) 0.177 (4.50) 0.252 BSC (6.4 BSC) 0’-8’ 12’REF 0.039 (1.0) e/2 0.039 (1.0) 0.126 BSC (3.2 BSC) 0.007 (0.19) 0.012 (0.30) 0.033 (0.85) 0.037 (0.95) 0.002 (0.05) 0.006 (0.15) 0.043 (1.10) Max (θ3)
1.0 REF
0.020 (0.50) 0.026 (0.75) (θ1) 0.004 (0.09) Min 0.004 (0.09) Min 0.010 (0.25) (θ2) 0.008 (0.20) DIMENSIONS in inches (mm) Minimum/Maximum Symbol 20 Lead D 0.252/0.260 (6.40/6.60) e 0.026 BSC (0.65 BSC) D PACKAGE: PLASTIC THIN SMALL OUTLINE (TSSOP)
Rev. 6/25/03 SP3203 © Copyright 2003 Sipex Corporation Model Temperature Range Package Types SP3203CY 0 °C to +70°C 20-pin TSSOP SP3203EY -40 °C to +85°C 20-pin TSSOP
ORDERING INFORMATION
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office
233 South Hillview Drive
Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sales Office
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Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com