SP1204 SIPEX | Alldatasheet
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SP1204 COMPONENT COUNT SUMMARY ARCHITECTURE & ORGANIZATION The organization and complexity of the SP1204 COUNT array makes it ideally suited for integrating Tiles: complete analog system functions on a single : AType 8 silicon chip. The SP1204 employs a tile based B Noe 8 architecture where each tile has been configured yp (sized) so that it can contain a complete analog Transistors: function. Pre-defined macro functions which fit SNPN 192 these tiles are available and can be used to SPNP 192 implement analog systems thus eliminating the tedious task of transistor level design. Using this DBNPN 16 approach also reduces both the manpower and DBPNP 16 elapsed time required to complete a design, while increasing the probability of first time MNPN 8 success. MPNP 8 Each tile on the SP1204 consists of 12 SNPN & 12 SPNP transistors arranged in a 3 x 8 matrix. There HNPN 9 are both A type & B type tiles. The only difference HPNP. i) between the two tile types is that the locations of P-JFET 16 the SNPN & SPNP transistors in the middle row of i is . the tile are reversed. As a result, A type tiles have Thin nonin 5700 i two NPN Quads & one PNP Quad while the B type ear reid Area Sq. rn tiles have two PNP Quads and one NPN Quad. otal 800 K2 Possible) This feature simplifies many types of layouts. The top and bottom rows have A type tiles while Capacitors: the two middle rows contain the B type tiles. 4.5 pF (max) 10 Sixteen P-JFETs, arranged in quads, lie across the 6 pF (max) 12 center of the die. The P-JFETs are only available 7 pF (max) 4 with the 35 Volt process. (These areas are inactive when using the 20 Voit process). Diodes: led Zener 2 Above and below each tile is a clear field area N+/P+ Diodes 40 which is reserved for user defined thin film resistors. Interspersed between the tiles and around the |BondPads | periphery of the array are the various Bond Pads | wo components available on the array. To accommodate rapid layout, all S$P1204 components are positioned on a 15 grid. Within the clear field area there is a 5y sub grid for thin- film resistor layout. The SP1204 is symmetric about the two perpendicular center lines of the array. There are additional symmetries within the tiles themselves as well as between adjacent tiles. The dimensions of the SP1204 are 140 mils x 146 mils. PROCESS OPTIONS Maximum operating voltage is usually a key requirement in most applications. For an analog ASIC application the maximum possible voltage is ultimately limited by the breakdown voltage of the transistors. The lowest breakdown voltage is usually VeEQ and process application capability is specified by this parameter. The VcEo is determined by a combination of starting Gigon resistivity and transistor geometries (i.e. spacings). Higher starting silicon resistivity gives higher VcEQ: but at the expense of slightly higher 7 transistor parasitics (mainly Rc) which will ultimately limit circuit performance.
The SP1204 array is available in two process SUPPORT PRODUCTS & SERVICES options: 20 Volt and 35 Volt processes. By = Commercially Available P-SPICE or Equivalent controlling substrate resistivity, NoEes of 35 Volts Simulators (Purchased Directly From the & 20 Volts are achieved. The 20 Volt VcE9 Vendor) process offers somewhat lower parasitics, and therefore, higher speed. This is the preferred m= Design Manual (DESMAN 1100) process for high speed applications, if maximum = Mylar Layout Worksheets voltages can be held below 20 Volts. = GDS II Database Tape for Workstations Based Layouts MACRO CELLS ; a A Family of Proven Macro Cells (Circuit Design time, cost and risk can be reduced Schematics and Net Lists are Available in the significantly by designing with proven macro cells Design Manual) rather than at the transistor device level. A library m Transistor Level and Macro Cell Kit Parts to of macro cells has been developed to support Support Evaluation and Breadboarding (If SP1204 user designs. Additional macros will be Required) added to the library as they become available. Aoplicati . Traini - Before starting your design, consult your local . pee ication Assistance and Training by Sipex SIPEX sales office or the factory to obtain the ersonnel latest update on available macro cells. SP1204 MACRO CELL LIBRARY a Bel NAME DESCRIPTION MXRBO1 1.5V Voltage Reference | 2.5V Voltage Reference |. | | MXRBO3_ =—-|2.5V Voltage Reference 1 | a +0.5 mA Current Reference MXRBOS 5.0V Voltage Reference La | MXRB10 10,0V Voltage Reference | a | MXOPO1_ =| General Purpose Wideband Op Amp MXOP02_ _|Wideband, Medium Drive 2 Op Amp MXOPO3 ‘| Precision High Bandwidth 2 Op Amp | MXCMO1_ |General Purpose Comparator 1 | | Ciney vitef, SIGNAL PROCESSING EXCELLENCE Sipex Corporation US Regional Sales Offices: European Sales Offices: UK. Six Fortune Drive 333 London Rood Billerica, MA 01821 (NORTHEAST: WEST: (GERMANY: Camberley, GUI5 3H TEL: (508) 663-7811 ‘Six Fortune Drive 49) Fairview Way Rheinstrasse 32 TEL: (0276) - 28128 FAX: (508) 667-5935, Billerica, MA 01821 Milpitas, CA 95035 6100 Darmstadt FAX: (0276) - 691131 TEL: (508) 663-7811 TEL: (408) 945-9080 TEL: (496151) - 291595 For Applications Assistance FAX: (608) 667-5935, FAX: (408) 946-6191 FAX: (496151) - 292762 FAR EAST/JAPAN: Please Call Nippon Sipex (408) 473-8800 ‘SOUTHEAST: CENTRAL: FRANCE Tonyama Building
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‘Suite 500 102 South Tejon Street 94663 Rungis Cedex Shinjuku-ku ‘Columbia MD, 21044, Colorado Springs, CO 80903 TEL: (1) 46.87.8336 Tokyo 162 TEL: (301) 740-5676 TEL: (719) 578-3346 FAX: (1) 45.60.07.84 TEL: 03-266-8585 FAX: (301) 740-5603 FAX: (719) 578-8869 FAX: 03-266-8587 Sjpex Corporation reserves the right fo make changes 10 any producls described herein. Sipex does not assume any labilty arising out of the appication or use of ony product oF citcut described herein; neither does it convey any license under its patent rights nor the rights of other: Aint racammended for Use in life support equipment. A ai7isa ~~ SP1208/2/90/2m
PROMs/SPROMs R29000 Series R29000 Series Applications @ Microprogram control store Standard ™ Microprocessor program store @ Programmable logic ! P rf ™@ Custom look-up tables e ormance @ Security encoding/decoding ™@ Code converter P ROMs and ™@ Character generator . @ Use in redundant systems ~ Power-Switched - SPROMs peseriprion | Raytheon’s R29000 Series of Bipolar Field Programmable Real-Only Memories include both standard and power-switched versions. ) Chip select inputs provide logic flexibility and | ease of memory expansion decoding. _ Features/Benefits The power-switched devices (SPROMs) were @ All devices are available in both commercial originated by Raytheon to reduce overall power (0°C to +75°C) and military (-55°C to +125°C) dissipation in PROM arrays. This technique temperature range takes advantage of the non-volatile nature of WAIl standard performance PROMs are offered PROMs by removing power when a particular in power-switched SPROM versions device is not being used in the system. Unlike @ Very high tolerance to total dose radiation previous power-switching schemes, which @ Typically, 75% power savings achieved on employed external transistors and resistors, the deselected SPROMs SPROM includes all power-switching circuitry ™@ Device pinouts conform to JEDEC standards on the same chip as the memory. Moreover, the WAIl devices programmed on standard PROM power switch state is activated by the same programmers Chip Select (Power Select) input scheme that is @ Reliable nichrome fuses used to address a standard performance @ Three-state outputs PROM; thus, in most cases, SPROMs can be @ Available in surface mount and through-hole directly substituted for standard devices without packaging system redesign. @ 4096 x 8 standard performance PROMs and power-switched SPROMs are offered in 24- All Raytheon R29000 Series PROMs and pin, 0.3" wide DIPs SPROMs are manufactured with nichrome | Raytheon Company Mountal ew CA 94039-7016 Semiconductor Division {t2'68 9011 TWX 910 379 6484 |