SMT4214

SMT4214 SUMMIT | Alldatasheet

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Preliminary Information1 (See Last Page) © SUMMIT Microelectronics, Inc. 2004 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897 The Summit Web Site can be accessed by “right” or “left” mouse clicking on the link: http://www.summitmicro.com/ 2061 2.2 09/15/05 1 FEATURES & APPLICATIONS

• Programmable Tracking Function
• Programmable Voltage Monitoring of 4 or more Independent Supplies
• Programmable Under-Voltage Thresholds
• Provides Soft Start, Reset, IRQ and Force Shutdown functions
• Minimizes Supply Differential During Power-on and Power-off
• Operates From Any One of Four Supply Voltages
• Easily Expandable to Control up to 32 Supplies
• Packaged in a 28 Lead SSOP

Applications

• Multi-voltage supply rail manager for
• Telecom Infrastructure
• Compact PCI
• Servers
• Multi-voltage Network Processors, DSPs, ASICs INTRODUCTION The SMT4214 is a fully integrated programmable voltage manager IC, providing supervisory functions and tracking control for up to four independent power supplies. The four internal managers perform the following functions: Monitor source (bus-side) voltages for under-voltage conditions, monitor back end (card- side) voltages for under-voltage conditions, insure voltage of the card-side tracks within the specified parametric limits, and provides supply status information to a host processor. The SMT4214 incorporates nonvolatile programmable circuits for setting all of the monitored thresholds for each manager. Individual functions are also programmable allowing interrupts or reset conditions to be generated by user-defined combinations of events. Programming of configuration and control values by the user can be simplified with the interface adapter (SMX3200) and Windows GUI software obtainable from Summit Microelectronics. SIMPLIFIED APPLICATIONS DRAWING MR# SCL SDA VIA VO A MR# SCL SDA VGATE A VID VO D VGATE D VIB VO B VGATE B VIC VO C VGATE C VRLINK LINK# FS# VRLINK LINK# FS# SEATED# PWR_ON# IRQ_CLR# IRQ# RST#VDD _CAP VGG_CAP +1.8V +5.0V Short Pin GND Early GND IRQ# RST# Master IRQ_CLR# +1.8V +2.5V +3.3V SMT4214 - Master SMT4214 Slaves Note 1 +3.3V +2.5V +5.0V PWR_ON# +2.7V +2.7V RST# Slave VGATE A RST# VIA VO A 3.3V 2.5V 2.7V RST# Master 1.8V RST# Slave --- t1 --- --- t2 --- 5.0V Power supply and system start-up initialization using multiple SMT4214s. Two power supply channels are set to ‘softstart’ and three are set to track. The above drawing illustrates the use of the SMT4214 in a multi-de vice application. It should be noted this is just an example and the specific component values are purposely not shown. Note 1 - Several pins have in ternal resistors so external re sistors are optional (see the Inte rnal Functional Bloc k Diagram). If external resistors are used they should be tied to VDD_CAP on the Master. Expandable Four-Rail Tracking Manager

after the under-voltage condition has cleared. affect on any other outputs or device operations. immediately be clamped to ground. basic relation between VI, VO, FS# and VGATE. PWR_ON#, FS#, VRLINK and LINK#. coordinate the power-on and power-off operation. devices will use this input as their own ramp reference.

1. If Channel A of device 3 falls behind the ramp

1, 2 and 3 until channel A of device 3 can catch-up. of their four channels configured to track. Figure 4. Timing relation between VI/VO, FS# out and VGATE and the relation between FS# in and VGATE

The SMT4214 has one volatile fault status register. be controlled with two signals; SDA and SCL. Figure 5. Fault Status register bit allocation

Summit Microelectronics, Inc 2061 2.2 09/15/05 6 INTERNAL FUNCTIONAL BLOCK DIAGRAM Supply Manager A Supply Manager B Supply Manager C Supply Manager D IRQ & RST Logic Charge Pump & VGATE Control Bus Interface Configuration Registers and Status Register IRQ# RST# VGATE A VRLINK LINK# VGATE B VGATE C VGATE D SDA SCL VDD Control Sequence Enable Logic VIA VO A VIB VO B VIC VO C VID VO D SEATED# FS# PWR_ON#

3 IRQ_CLR#

GND VDD_CAP VGG_CAP Force Shutdown Arbitration 2MR# 100K Ω nom. 100K Ω nom. 100K Ω nom. 3 plcs. 100K Ω nom. 5 plcs.

Summit Microelectronics, Inc 2061 2.2 09/15/05 7 Pin Number Pin Type Pin Name Pin Description

1 I/O SDA

SDA is the bi-directional serial data pin. It is configured as an open drain output. SDA is internally connected to VDD_CAP through a 100kΩ pull-up resistor. In multiple device systems, an external pull-up should be connected to the highest supply

2 I MR#

The Manual Reset input is an active low input, internally connected to VDD_CAP through a 100kΩ pull-up resistor. Taking MR# low will force the RST# output low. MR# must be forced low when writing to the configuration registers.

3 I IRQ_CLR#

Interrupt Clear is an active low input. Forcing IRQ_CLR# low will clear the IRQ# output provided that it is not being driven by an under-voltage condition. IRQ_CLR# is internally connected to VDD_CAP through a 100kΩ pull-up resistor.

4 I/O FS#

Force Shutdown is an active low open-drain I/O internally connected to VDD_CAP through a 100kΩ pull-up resistor. FS# can be asserted either by an outside signal or by a programmable under-voltage condition. If FS# is brought low, the SMT4214 will immediately take the VGATE outputs to 0V. If multiple SMT4214’s are used on a single board, the FS# outputs can be tied together. In this configuration it is possible for a fault condition on one SMT4214 to shutdown all of the SMT4214’s on a system.

5 I/O PWR_ON#

The Power-On input must be low for the SMT4214 to begin turning on the VGATE outputs. PWR_ON# is internally connected to VDD_CAP through a 100kΩ pull-up resistor, therefore its normal state is not active. PWR_ON# must be held in its inactive state while writing to the configuration registers. Once the power-on operation has completed, de-asserting the PWR_ON# input will force the ‘tracked’ channels to power down and then clamp all VGATE outputs to ground.

6 PWR VGG_CAP

VGG_CAP is a charge storage connection for the charge pump. This capacitor provides current to the VGATE outputs under varying load conditions. VGG_CAP should nominally be 1µF.

7 I SEATED#

The SEATED# is an active low input, internally connected to VDD_CAP through a 100kΩ pull-up resistor. The SEATED# input is effectively an enable input that must be low for tSEATED before the power-on operation can proceed. It is generally tied to the ‘short pin’ in a staggered pin connector. When the card is removed, SEATED# will go high and will initiate a power-off operation.

8 I A0

9 I A1

The address pins are biased either to VDD_CAP or GND and provide a mechanism for assigning a unique bus address to the SMT4214. AO and A1 are internally connected to VDD_CAP through a 100kΩ pull-up resistor

10 I VOD

11 I VOC

12 I VOB

13 I VOA

The Voltage Output monitor inputs are used to monitor the ‘card-side’ voltages for the individual managers. See Figure 8 for additional external component recommendations.

14 O RST#

Reset is an active low open-drain output. It will be driven low whenever the MR# input is low. RST# can be programmed so that it is asserted on an under-voltage condition. PIN DESCRIPTIONS

Summit Microelectronics, Inc 2061 2.2 09/15/05 8 PIN DESCRIPTIONS CONT’D Pin Number Pin Type Pin Name Pin Description

15 O IRQ#

Interrupt is an active low open-drain output. It can be programmed so that it is driven low on an under-voltage condition. It is cleared by removing any under- voltage conditions and asserting IRQ_CLR#.

16 PWR VDD_CAP

VDD_CAP is a charge storage connection to the SMT4214’s internal power supply. For most applications this is tied to a 10µF capacitor. A smaller 0.1µF can be added in parallel for additional noise decoupling

17 O VGATED

18 O VGATEC

19 O VGATEB

20 O VGATEA

The VGATE outputs are used to control the “turn-on” of the card-side voltages by providing a high side voltage to a power MOSFET. The VGATE output voltages are programmable as either 10.5V or 14.5V depending on the type of MOSFET gate drive needed to fully enhance the device. See Figure 8 for additional external component recommendations.

21 I/O VRLINK

Voltage Ramp Link is an I/O and is used in a multi-SMT4214 application. If the SMT4214 is designated as the master its VRLINK will become an output providing the ramp reference of the card-side voltages for the slave SMT4214’s. If the SMT4214 is designated as a slave its VRLINK will become the input for the VRLINK of the master.

22 I/O LINK#

Link is an active low open-drain I/O internally connected to VDD_CAP through a 100kΩ pull-up resistor. In a multi-SMT4214 application the LINK# pin of all the devices can be tied together to synchronize tracking. The LINK# I/O is active only during a power-on or power-off operation. If one of the devices is falling behind in tracking of the card-side voltages, it will assert its LINK# output and temporarily halt the ramping of the VGATE voltages of the other devices.

23 I VI A

24 I VI B

25 I VI C

26 I VI D

The Voltage Inputs provide two functions. Internally they are diode-OR’ed; therefore, the input with the highest voltage will act as the device’s VDD supply. They are also the bus-side (unswitched) voltage monitoring inputs to the individual supply managers. See Figure 8 for additional external component recommendations. 27 PWR GND GND is the ground for both the analog and digital portions of the internal circuitry.

28 I SCL

SCL is the serial clock input, used for clocking data into or out of the SMT4214. SCL is internally connected to VDD through a 100kΩ pull-up resistor. In multiple device systems, an external pull-up should be connected to the highest supply. PACKAGE PIN CONFIGURATION VIA VIB VIC VID VGATE A VO A PWR_ON# GND VO C VO B VO D VGATE B VGATE C VGATE D SDA SCL VGG_CAP VDD_CAP VRLINK LINK# FS# IRQ_CLR# IRQ#RST# MR# SEATED# SMT4214 PIN 1

28 Lead SSOP

Summit Microelectronics, Inc 2061 2.2 09/15/05 9 ABSOLUTE MAXIMUM RATINGS Terminal Voltage with Respect to GND: Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. RECOMMENDED OPERATING CONDITIONS Package Thermal Resistance (θ JA) Moisture Classification Level 1 (MSL 1) per J-STD- 020 Notes: 1/ For reliable operation the VDD_CAP node voltage must be equal to or greater than 2.7V (voltage level measured on pin 16). RELIABILITY CHARACTERISTICS DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit VI Supply Voltage VIA, VIB, VIC or VID Device supply voltage defined by the highest of the four VI inputs. Note 1/ 2.7 6.0 V IDD (ON) Power Supply Current Active Current VGATE Outputs enabled 2 mA PVIT Programmable VI Threshold 8-bit resolution 20mV/bit 0.9 6.0 V PVOT VO Threshold VI X-VOX 180 200 220 mV Option 1 (MOSFETs on) 13 14 V PVVG Programmable VGATE Output Option 2 (MOSFETs on) 10 10.5 V VVG OFF VGATE Output VGATE sinking 2mA 0 0.4 V IVG VGATE Drive Current MOSF ET switches enabled 20 80 µA SRVG VGATE Slew Rate 500 V/s VTRKR Tracking Differential Voltage Allowable differential between VO pins programmed for tracking 100 250 mV VI = 2.7V 0.9xVI VI V VIH Input High Voltage VI = 5.0V 0.7xVI VI V VOL Output Low Voltage Open Drain Outputs, I SINK = 2mA 0 0.4 V RPull-Up Input Pullup Resistors S ee Pin Descriptions 50 100 165 kΩ Notes: 1/ - At least one of the VI inputs needs to be at or above 2.7V for proper device operation.

provided by the device receiving data. high transition of SDA during tHIGH is a stop condition. match the state of these pins. last written (or read) address incremented by 1. 8 for an illustration of the read sequence. Figure 7. Write configuration register sequence.

0 W 10 01 A

XFigure 8. Read Configuration register or status register sequence.

Summit Microelectronics, Inc 2061 2.2 09/15/05 13 DEVELOPMENT HARDWARE & SOFTWARE The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and Windows GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (see below). The SMX3200 programming Dongle/cable interfaces directly between a PC’s parallel port and the target application. The device is then configured on- screen via an intuitive graphical user interface employing drop-down menus. The Windows GUI softwar e will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMT4214 via the programming Dongle and cable. An example of the connection interface is shown in Figure 9A and 9B. When design prototyping is complete, the software can generate a HEX data file that should then be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector SMT4214 SDA SCL VDD_CAP GND 0.1 µF Common Ground MR# PWR_ON# 4.7k Ω Pin 5, Reserved Pin 9, 5V Pin 7, 10V Pin 3, GND Pin 1, GND Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 8, Reserved Pin 10, Reserved C1 C2 4.7k Ω 0.1 µF Figure 9A – SMX3200 Programmer and I 2C serial bus connections to program the SMT4214. For the SMT4214, the PWR_ON# pin must be high in order to program the device. It can be done optionally through the SMX3200 programmer and R1/R2 or through an external control signal or switch. The SMX3200 should be disconnected after programming th e part. If the PWR_ON# is hardwi red to ground, this method will not work. Normally SDA and SCL signals require on board pull-up resistors, however, both the SMT4214 and the SMX3200 have internal pull-up resistors. D1 and D2 (1N4148) are needed between the Dongle Supplies and the VDD_CAP and PWR_ON# pins so that there will be no contention between the two supplies. C1 and C2 are for noise bypassing. The latest revisions of all software and an application brief describing the SMX3200 is available from the website at: http://www.summitmicro.com/tech_support/program_kit/SMX3200.htm

Summit Microelectronics, Inc 2061 2.2 09/15/05 14 DEVELOPMENT HARDWARE & SOFTWARE (Cont.) APPLICATIONS INFORMATION An example master/slave application circuit is shown in Figure 10A and 10B. Additional optional noise bypassing components are shown for the VIX and VOX pins. These components consist of ferrite bead inductors and capacitors. They may be necessary in very noisy systems where tight undervoltage tolerances are needed. All unused channels must be programmed to soft- start mode. The thresholds for unused channels should be set to minimum, and the VO and VI inputs should be tied to the highest voltage VI input. The VGATE output pins require series resistors to drive the gates of the power MOSFETs. Gate capacitors (C23 thru C30) are also recommended to prevent initial MOSFET turn-on during the SMT4214 power on sequence. To minimize transient power surges in hot-swappable line card designs, place a 0.01µF (10nF), 25V, ceramic capacitor on each VGATE output pin to ground. The VGATE output level is programmable to either 10.5V or 14V depending on the type of MOSFET. To minimize the voltage drop across the MOSFET, it needs to be fully enhanced to minimize RDS (ON). However, some MOSFETs have maximum VGS specifications of 15V wh ile others are 20V. For improved tracking performance with the SMT4214, it is recommended to use the lower rated VGS devices with the VGATE output levels set to 10.5V instead of 14V. The industry trend for power MOSFETs is toward lower VGS specs wh ile also maintaining low RDS (ON) specifications. SMT4214 SDA SCL VDD_CAP GND 0.1 µF Common Ground MR# PWR_ON# 4.7k Ω C1 C2 R2 4.7k Ω 0.1 µF 5.6V Zener Figure 9B – An alternative connection between the SMX3200 Programmer and SMT4214 I 2C serial bus connections. Although this alternat ive requires additional components, it will work regardless of the position of the external PWR_ON# control signal or sw itch (S1). The zener diode (D3) provides furthe r protection by clamping the output voltage at 5.6V.

Summit Microelectronics, Inc 2061 2.2 09/15/05 15 APPLICATIONS INFORMATION (Cont.) LAYOUT CONSIDERATIONS When a power MOSFET is off, the trace from the supply to the VIX input of the SMT4214 carries very little current. As that MOSFET turns on the trace will carry more current possibly causing a voltage drop across the trace. If this voltage drop is severe, the VIX input will droop below the UV trip point and the supply will stay below the trip point even when the MOSFET is fully enhanced. Therefore, the internal ramp model of the SMT4214 will halt indefinitely. Subsequent higher voltage channels will also halt with the internal ramp model causing their corresponding VGATE outputs to halt. This leaves the MOSFETs on but not fully enhanced and therefore with higher rDS(ON) and more power dissipation. In order to prevent this situation it is recommended t hat the sense lines of the power supply be connected close to the power MOSFET as the power supply will then compensate for any voltage drop along the trace. The trace should also be designed to adequately handle the required current with minimal voltage drop. The Tracking Time Limit feature in the Windows GUI should be enabled to prevent tracking from hanging-up and allowing the MOSFETs to get hot. Lowering the UV trip points will also solve the problem, but could leave the output voltages lower than expected.

Summit Microelectronics, Inc 2061 2.2 09/15/05 16 APPLICATIONS INFORMATION (Cont.) Figure 10A – Example application using two SMT4214s connected in a Master/Slave configuration. The Master is shown above, the Slave is shown in Figure 10B.

Summit Microelectronics, Inc 2061 2.2 09/15/05 17 APPLICATIONS INFORMATION (cont.) Figure 10B – Example application using two SMT4214s connected in a Master/Slave configuration. The Slave is shown above, the Master is shown in Figure 10A

Summit Microelectronics, Inc 2061 2.2 09/15/05 18 DEFAULT CONFIGURATION REGISTER SETTINGS – SMT4214G-115 Register Hex Contents Configured as: R00 B4 Channel A UV Trip Point = 4.5V R01 69 Channel B UV Trip Point = 3.0V R02 41 Channel C UV Trip Point = 2.2V R03 28 Channel D UV Trip Point = 1.7V R04 F1 Channel A,B,C, and D set to track Tracking time limit enabled RST# timeout interval set to 25ms Device set as Master R05 21 VGATE output level = 10.5V UV cause RST# after tracking enabled UV cause IRQ# after tracking disabled Filter time = 0ms Virtual address A2 set to high UV does not cause a FS# after tracking is complete (steady state) UV does not cause a FS# at the end of tracking filter time interval R06 00 Volatile register, all status bits are low The default device ordering number is SMT4214G-115. It is programmed with the register contents as shown above and tested over the commercial temperature range. Application Note 28 contains a complete description of the Windows GUI and the default settings of each of the 6 individual Configuration Registers.

Summit Microelectronics, Inc 2061 2.2 09/15/05 19 PACKAGE

28 Lead SSOP Package

Summit Microelectronics, Inc 2061 2.2 09/15/05 20 PART MARKING SMT4214G L AYYWW Pin 1 Annn Summit Part Number Date Code (YYWW) Part Number suffix (Contains Customer specific programming and ordering requirements. The default device ordering number is not marked on the device) Product Tracking Code (Summit use) Lot tracking code (Summit use) Drawing not to scale xx Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) SUMMIT 100% Sn, RoHS compliant

ORDERING INFORMATION

G=28 Lead SSOP Summit Part Number Specific requirements are contained in the suffix nnn Part Number Suffix (see page 18) C Temp Range C=Commercial Blank=Industrial L Environmental Attribute L = 100% Sn, RoHS compliant NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. Revision 2.2 - This document supersedes all previous versions. . Data Sheet updates can be accessed by “right” or “left” mouse clicking on the link: http://www.summitmicro.com/prod_select/summary/smt4214.htm Device Errata sheets can be accessed by “right” or “left” mouse clicking on the link: http://www.summitmicro.com/errata/SMT4214 SUMMIT Microelectronics, Inc. reserves the ri ght to make changes to the products cont ained in this publication in order to impr ove design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and sche dules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the inform ation in this publication has been carefully checked, SUMMI T Microelectronics, Inc. shall not be liabl e for any damages arising as a result o f any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expe cted to cause any failure of either syst em or to significantly affect their sa fety or effectiveness. Products are not authorized for use in such applications unless SU MMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2004 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER FOR A DIGITAL WORLD™ I2C is a trademark of Philips Corporation.