SMS2902 SUMMIT | Alldatasheet

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SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131  Campbell, CA 95008  Telephone 408-378-6461  Fax 408-378-6586  www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 2000 2028 5.1 8/2/00 Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc.

FEATURES

  • Precision Voltage Monitor –V CC Supply Monitor - Complementary reset outputs for complex microcontroller systems - Integrated memory write lockout function - No external components required Watchdog Timer – 1600 ms, internal  Two Wire Serial Interface (I2C™)  Extended Programmable Functions available on SMS24  High Reliability – Endurance: 100,000 erase/write cycles – Data retention: 100 years  8-Pin SOIC Packages Voltage Supervisory Circuit With Watchdog Timer SMS2902/SMS2904/SMS2916 OVERVIEW The SMS29xx is a power supervisory circuit that monitors VCC and will generate complementary reset outputs. The reset pins also act as I/Os and may be used for signal conditioning. The SMS29xx also has an on-board watch- dog timer. The SMS29xx integrates a nonvolatile serial memory. It features the industry standard I 2C serial interface allowing quick implementation in an end-users’ system. BLOCK DIAGRAM GND VCC RESET#2 VTRIP RESET CONTROL RESET7 1.26V SCL 6 SDA 5 WATCHDOG TIMERWDI# 1 2028 T BD 2.0 WRITE CONTROL NONVOLATILE MEMORY ARRAY PROGRAMMABLE RESET PULSE GENERATOR

FIGURE 1. SERIAL BUS TIMING DIAGRAM

2028 5.1 8/2/00 ABSOLUTE MAXIMUM RATINGS NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. 2.7V to 4.5V 4.5V to 5.5V Symbol Parameter Conditions Min Max Min Max Units fSCL SCL Clock Frequency 0 100 400 KHz tLOW Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4.0 0.6 µs tBUF Bus Free Time Before New Transmission 4.7 1.3 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tSU:STO Stop Condition Setup Time 4.7 0.6 µs tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 3.5 0.2 0.9 µs tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 0.2 µs tR SCL and SDA Rise Time 1000 300 ns tF SCL and SDA Fall Time 300 300 ns tSU:DAT Data In Setup Time 250 100 ns tHD:DAT Data In Hold Time 0 0 ns TI Noise Spike Width Noise Suppression Time Constant 100 100 ns @ SCL, SDA Inputs tWR Write Cycle Time 10 10 ms AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) 2028 PGM T5.0 2028 PGM T4.0 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter Conditions Min Max Units SCL = CMOS Levels @ 100KHz V CC =5.5V 3 mA ICC Supply Current (CMOS) SDA = Open All other inputs = GND or VCC VCC =3.3V 2 mA ISB Standby Current (CMOS) SCL = SDA = V CC VCC =5.5V 50 µA All other inputs = GND ILI Input Leakage V IN = 0 To VCC 10 µA ILO Output Leakage V OUT = 0 To VCC 10 µA VIL Input Low Voltage S0, S1, S2, SCL, SDA, RESET# 0.3xV CC V VIH Input High Voltage S0, S1, S2, SCL, SDA, RESET 0.7xV CC V VOL Output Low Voltage I OL = 3mA SDA 0.4 V VCC =3.3V 25 µA Temperature Min Max Commercial 0 °C +70 °C Industrial -40 °C +85 °C RECOMMENDED OPERATING CONDITIONS 2028 PGM T3.0

FIGURE 2. RESET OUTPUT TIMING

2028 5.1 8/2/00 ENDURANCE AND DATA RETENTION The SMS29xx is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. Reset Controller Description The SMS29xx provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. During power-up, the RESET outputs remain active until V CC reaches the VTRIP threshold and will continue driving the outputs for tPURST (200 msec) after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driv- ing active when V CC falls below VTRIP. The RESET pins are I/Os; therefore, the SMS29xx can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET# input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a reset conditioning circuit. WATCHDOG TIMER OPERATION The SMS29xx has a watchdog timer with a program- mable timeout period. Whenever the watchdog times out it will generate a reset output on both RESET# and RESET. Any transition on WDI will clear the watchdog timer. If a transition is not detected within t WDTO seconds the watch- dog will time out and force the reset outputs active. PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wire- ORed with any number of open-drain or open-collector outputs. RESET# - RESET# is an active low output. Whenever V CC is below VTRIP the SMS29xx will drive the RESET# pin to ground. The RESET# pin is an I/O and can be used as a reset input. Refer to Figure 1 as an example use of this pin as a push button switch debounce circuit. It should be noted this is an open drain output and an external pull-up resistor tied to V CC is needed for proper operation. RESET — RESET is an active high output. Whenever VCC is below VTRIP the SMS29xx will drive the RESET pin to the VCC rail. The RESET pin is an I/O and can be used as a reset input. It should be noted this is an open drain output and an external pull-down resistor tied to ground is needed for proper operation. WDI# - The WDI# input is used as a hardware method of clearing the watchdog timer. A high to low transition on this pin will clear the watchdog timer. If a transition is not detected within 1.6 seconds the watchdog will time out and force the reset outputs active.

FIGURE 10. RANDOM ADDRESS BYTE READ MODE WRITE) followed by the address of the word it is to read. SMS29xx to the desired address. the address, acknowledge and data transfer sequence.

ACKnowledge, and issues a STOP conditions. address, acknowledge and data transfer sequence. FIGURE 11. SEQUENTIAL READ OPERATION (starting with a Random Address READ)

2028 5.1 8/2/00 TYPICAL APPLICATION CONFIGURATION USING SYSTEM DECODE LOGIC TO RESET WDI TYPICAL APPLICATION USING DUAL RESET FUNCTION AND WATCHDOG TIMER 5.0VDC WDI# RESET# NC GND VCC RESET SCL SDA SMS29xx I/O I/O Z80 PB_RST# 2028 T fig13 2.0 RST# DECODER 2028 T fig14 2.0 VCC WDI# RESET# NC GND VCC RESET SCL SDA SMS29xx 5.0VDC PBRST# TOL GND VCC ST# RST# RST SCL SDA 24C16 I/O I/O ALE 8051 Family Part ALE 8051 Family PartRST I/O I/O 1232 GND RST VCC = 3.0V or 5.0V WDI# RESET# NC GND VCC RESET SCL SDA SMS29xx RESET# SCL SDA I2C Peripheral RST SCL (P0.0) SDA (P0.1) ALE

8051 Type

PB_RST# 2028 T fig12 2.0 From This To This

2028 5.1 8/2/00 .228 (5.80) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.

8 Places

.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00)1 .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

2028 5.1 8/2/00 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation.

ORDERING INFORMATION

S = SOIC A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V 2028-02 Tree 2.0 SMS2904 S A Base Part Number VTRIP Package S = SOIC A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V 2028-04 Tree 2.0 SMS2916 S A Base Part Number VTRIP Package S = SOIC A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V 2028-16 Tree 2.0