SMS24

SMS24 SUMMIT | Alldatasheet

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1Characteristics subject to change without notice 2048 2.4. 3/1/01 SMS24SUMMIT MICROELECTRONICS, Inc. ©SUMMIT MICROELECTRONICS, Inc., 2001 • 300 Orchard City Dr., Suite 131  Campbell, CA 95008  Phone 408-378-6461  FAX 408-378-6586  www.summitmicro.com /G6CUser Programmable Device Configuration /G6CGuaranteed Reset Valid to VCC = 1V /G6CImmune to Short Negative VCC Transients /G6CSix Unique Pin Configurations /G6CUser Programmable Feature Options: /G77Reset Threshold Voltages /G77Reset Pulse Widths /G77Programmable Watchdog Timeouts /G77Programmable Over- or Under-Voltage Sens- ing /G6CHigh Reliability /G77Endurance: 100,000 erase/write cycles /G77Data retention: 100 years Highly Programmble Voltage Supervisory Circuit

FEATURES

The SMS24 is a configurable and in-system program- mable second generation 8 pin supervisory circuit. This single device is adaptable to provide the optimum func- tionality for a given system or sub-system. User program- mable functions available — reset pulse width, watchdog delays, and voltage monitor thresholds — eliminate exter- nal components and allow standardization to enhance system reliability. Additionally, 4K bits of general purpose EEPROM is available on all configurations. The SMS24 is available in six pin configurations, and is compatible with all Summit programmable devices and other I2C compo- nents. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Sum- mit Microelectronics. 2048 DTTable 2.1 NC RESET# NC GND VCC RESET SCL SDA Device Code 001 NC RESET# NC GND VCC WP SCL SDA Device Code 010 WDI RESET# NC GND VCC RESET SCL SDA Device Code 011 RESET#2 RESET#1 VSENSE GND VCC MR# SCL SDA Device Code 100 VLOW # RESET# VSENSE GND VCC RESET SCL SDA Device Code 101 VLOW # RESET# VSENSE GND VCC WDI SCL SDA Device Code 110 2046 DT 1.0 eciveD edoC noitcnuF #teseRt eseRg odhctaW erawtfoS IDW niPIDW etirW tcetorP niP dn2 egatloV rotinoM launaM teseR tupnI VN yromeM

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. FUNCTIONAL BLOCK DIAGRAMS Block Diagram Device Code 010 Block Diagram Device Code 001 GND VCC VTRIP RESET CONTROL 1.25V SCL 6 SDA 5 2046 BD001 2.1 WRITE CONTROL NONVOLATILE MEMORY ARRAY RESET#2 RESET7 PROGRAMMABLE RESET PULSE GENERATOR PROGRAMMABLE WATCHDOG TIMER GND VCC RESET#2 VTRIP RESET CONTROL WP7 1.25V SCL 6 SDA 5 2046 BD010 2.1 WRITE CONTROL NONVOLATILE MEMORY ARRAY PROGRAMMABLE RESET PULSE GENERATOR PROGRAMMABLE WATCHDOG TIMER

2048 2.4. 3/1/01 SMS24 SUMMIT MICROELECTRONICS, Inc. Block Diagram Device Code 100 Block Diagram Device Code 011 GND VCC RESET#2 VTRIP RESET CONTROL RESET7 1.25V SCL 6 SDA 5 2046 BD011 1.0 WRITE CONTROL NONVOLATILE MEMORY ARRAY PROGRAMMABLE RESET PULSE GENERATOR WDI 1 PROGRAMMABLE WATCHDOG TIMER GND VCC RESET#12 VTRIP RESET CONTROL MR# 1.25V SCL 6 SDA 5 2046 BD100 1.1 WRITE CONTROL NONVOLATILE MEMORY ARRAY PROGRAMMABLE RESET PULSE GENERATOR VSENSE 3 RESET#2 PROGRAMMABLE WATCHDOG TIMER

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. Block Diagram Device Code 110 Block Diagram Device Code 101 GND VCC RESET#2 VTRIP RESET CONTROL RESET7 1.25V SCL 6 SDA 5 2046 BD101 1.0 WRITE CONTROL NONVOLATILE MEMORY ARRAY PROGRAMMABLE RESET PULSE GENERATOR VSENSE 3 VLOW #1 PROGRAMMABLE WATCHDOG TIMER OV UV GND VCC RESET#2 VTRIP RESET CONTROL WDI71.25V SCL 6 SDA 5 2046 BD110 1.0 WRITE CONTROL NONVOLATILE MEMORY ARRAY PROGRAMMABLE RESET PULSE GENERATOR VSENSE 3 VLOW #1 PROGRAMMABLE WATCHDOG TIMER OV UV

2048 2.4. 3/1/01 SMS24 SUMMIT MICROELECTRONICS, Inc. *COMMENT Stresses listed under Absolute Maximum Ratings may cause perma- nent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Terminal Voltage with Respect to GND: DC OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* (Over Recommended Operating Conditions; Voltages are relative to GND) lobmySr etemaraPs noitidnoC. niM. pyT. xaMs tinU V CC ylppusgnitarepO egatlov tuptuo#TESERdilaV1 5 .5V notarepoyromeM7 .25 .5V ICC tnerrucylppuS <V6.3V CC V5.5<0 5A µ <V7.2V CC V6.3<0 2A µ sseccayromeM3 A µ V TSRP dlohserhtteserelbammargorP 4RR3 RR2 RR1 RR0 RR 00001 5 70.25 1.25 2.2V 00010 5 5.25 6.27 .2V 00100 8 .29 .20 .3V 01000 5 2.45 73.45 .4V 10000 5 .45 26.45 7.4V VT V ESNES dlohserhttupni3 2.15 2.17 2.1V V LO V,2#TESER,1#TESER WOL :# egatlovtuptuo I KNIS V,Am2.1= CC V= TSRP .nim 3.0V I KNIS V,Am002= CC V2.1=3 .0V I RM tnerrucpullup#RM 001A µ V Ll VnonoitcejeresioN CC 3.0 × V CC V V HI otgnissorcdlohserhtyaleD tuoTESER 7.0 × V CC V 2046 DCElect Table 2.0 RECOMMENDED OPERATING CONDITIONS Temperature –40ºC to 85ºC. Voltage 2.7V to 5.5V ENDURANCE AND DATA RETENTION The SMS24 is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles.

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. PIN DESCRIPTIONS RESET# This signal is an active-low open drain I/O. Whenever the voltage on VCC is below the programmed threshold volt- age the RESET# pin will be driven low. After VCC passes through the threshold (in a positive direction) the RESET# output will continue to be driven for the programmed time- out period (t PTO ). In most configurations RESET# is also an input. Whenever it is driven low it will activate the reset timer. The RESET# output will then be driven low by the device for the programmed period. If the input pulse is of shorter duration than t PTO , RESET# will continue to be driven. If it is longer than tPTO , RESET# will be released and follow the input back high. RESET This signal is an active-high open drain I/O. Whenever the voltage on V CC is below the programmed threshold volt- age the RESET pin will be driven high. After VCC passes through the threshold (in a positive direction) the RESET output will continue to be driven for the programmed time- out period. In all configurations using RESET it is also an input. Whenever it is driven high it will activate the reset timer. The RESET output will then be driven high by the device for the programmed period. If the input pulse is of shorter duration than t PTO , RESET will continue to be driven. If it is longer than tPTO , RESET will be released and follow the input back low. RESET#1 & RESET#2 These signals are active-low open drain outputs (not I/Os). These outputs are only available to Device Code 100, and are both set to a low state by any one of three events: V CC below trip level, VSENSE < 1.25V, or MR# strobed low. MR# Manual Reset input is an active low input. Whenever it is taken low it will generate a reset time-out. VSENSE This is a second voltage sense input connected to its own comparator that has reference of 1.25V. The comparator can be programmed to activate the V LOW # output either for an over-voltage or under-voltage condition. VLOW # This is an active-low open-drain output that can be wire- ORed with the RESET# output or tied directly to an interrupt input. WDI This is the Watchdog Interrupt input. Whenever a transi- tion occurs on WDI the watchdog timer will be cleared. If the device does not receive an interrupt before t WDTO the device will drive the reset output(s). The period tWDTO is programmable for four basic values. It can also be placed into an idle mode, facilitating system debug, and allowing a system time to configure itself after a power-on. WP This is an auxilliary Write lockout input pin. When held high no writes will occur. SCL The serial interface clock input. SDA The serial interface data I/O.

SUMMIT MICROELECTRONICS, Inc. locks the contents of the register. Table 1. Configuration Register Table 2. Programming Register 0

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. since it never initiates any data transfers. will be interpreted as a start or a stop condition. Table 3. Programming Register 1

1 D ecive T 1101sserddAepy

while the clock is high is defined as the “START ” condition. high is defined as the “STOP ” condition. Figure 1. START and STOP Conditions

SUMMIT MICROELECTRONICS, Inc. Figure 2. Programming the SMS24 four bits of the slave address are the device type identifier. Registers have a device type address of 1001. The next three bits are the high order address bits. performed. When set to “1” a read operation is selected. When set to “0” a write operation is selected.

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. Table 4. Device Addressing ated and then the balance of the address is transmitted. to any requests from the master. The SMS24 is capable of a 16-byte page write operation.

2048 2.4. 3/1/01 SMS24 SUMMIT MICROELECTRONICS, Inc. ment the current address pointer. When the SMS24 receives the slave address field with the R/W bit set to “1” it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point the SMS24 discontinues data transmission. Random Address Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMS24 to the desired address. After the word address acknowlthe R/W bit set to READ. The SMS24 will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point the master does not acknowledge the transmission but does gener- ate the stop condition. The SMS24 discontinues data transmission and reverts to its standby power mode. Sequential READ Sequential reads can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowl- edge, indicating that it requires additional data from the SMS24. The SMS24 continues to output data for each ACKnowledge received. The master terminates the se- quential READ operation by not responding with an AC- Knowledge, and issues a STOP condition. During a sequential read operation the internal address counter is automatically incremented with each ACKnowledge sig- nal. For read operations all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address the address counter will rollover and the memory will continue to output data.

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. Table 5. Memory AC Operating Characteristics Figure 7. Memory Operating Characteristics

SUMMIT MICROELECTRONICS, Inc. Figure 8. System Timing Patterns

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. AC OPERATING CHARACTERISTICS Under recommended Operating Conditions lobmySr etemaraPn oitidnoC. niM. pyT. xaMs tinU t OTP tuoemitteserelbammargorP )1etoN(doirep 1TR0 TR 00 0 25 20 3s m 01 5 30 55 6s m 10 5 60 015 31s m 11 0 310 020 72s m t OTWP godhctawelbammargorP doireptuoemitremit 2DW1 DW0 DW 00x f fO 01 1 4 .0s 100 8 .0s 10 1 6 .1s 11 0 2 .3s 111 4 .6s t RM eslupteserlaunammuminiM htdiw 05s n t HCTILG VnonotcejeresioN CC 03s n t DPR otgnissorcdlohserhtyaleD tuoTESER 5s µ Note 1: Minimum and maximum values for these parameters may change without notice. 2046 ACElect Table 2.0

2048 2.4. 3/1/01 SMS24 SUMMIT MICROELECTRONICS, Inc.

ORDERING INFORMATION

8 PIN SOIC PACKAGE

1 – 6 (HEX Format) (HEX Format) 2046 Tree 1.0 .05 (1.27) TYP.

8 Pin SOIC

0.150 - 0.157 (3.80 - 4.00) 0.189 - 0.196 (4.80 - 5.00) 0.053 - 0.069 (1.35 - 1.75) 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.010 (0.10 - 0.25) 0.016 - 0.050 (0.40 - 1.27) ×45º 0.010 - 0.020 (0.25 - 0.50) 0.228 - 0.244 (5.80 - 6.20) Ref. JEDEC MS-012 Inches (Millimeters)

2048 2.4. 3/1/01 SUMMIT MICROELECTRONICS, Inc. NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2001 SUMMIT Microelectronics, Inc. Supersedes all previous versions. I2C is a trademark of Philips Corporation.