SMR101 SUMMIT | Alldatasheet
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Preliminary Information 1 (See Last Page) © SUMMIT Microelectronics, Inc. 2004 • 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897 http://www.summitmicro.com 2091 2.1 4/21/2005 1
- Two Programmable Reset Outputs, SOFT_RST# And HARD_RST#
- De-Bounced Push-Button Reset Input With a Programmable Delay Up To 40 Seconds Prior To Reset Assertion
- 8 Programmable Settings For Both SOFT_RST# And HARD_RST# Delay
- Programmable Voltage Monitor With 8 Voltage Settings To Trigger SOFT_RST# Output
- Programmable Reset Output Duration From 1- 200ms
- Built-In 15us Voltage Glitch Filtering And Input “De-Bouncing”
- 6 Ball Ultra CSP TM (Chip-Scale) Package
- 8 Lead SOIC Package
Applications
- PDAs, Handheld PCs, Cameras, Camcorders
- Handheld GPS Equipment
- Satellite And Cable-TV Set-Top Box The SMR101 is a programmable reset controller especially designed for embedded consumer electronics. The device provi des dual outputs that can be used to implement “soft” and “hard” system resets. Both resets can be triggered by an external reset input, and an internal voltage monitor can trigger the soft reset. Typically a “soft” reset applies to volatile registers in an embedded controller while a hard reset is equivalent to a full power cycle without the associated power-up delays. The SMR101 receives an external push-button input using an internal programmable de- bounced timer. The push button input hold down time is programmable up to 40 seconds with an internal on-chip timer. A “short” hold down time (0.125-10 sec) asserts the SOFT_RST# pin while a long hold down time (0.5- 40 sec) asserts the HARD_RST# pin. Both reset outputs have programmable output durations from 1- 200ms. Additionally, voltage monitoring is provided via a programmable threshold detector (2.30V – 4.50V) on the VDD pin. This vo ltage detector asserts the SOFT_RST# pin for the same 1-200ms output duration as above. A 15us glitch filter avoids nuisance tripping that can result in unnecessary system resets. The SMR101 is factory programmed, to default values; however, multiplexed programming pins are also provided for in-system programming for prototype purposes. FILT_CAP TRIM_C AP SMR101 3.3V 2.7V _ 5.5V GND VDD PROG RESET_IN# HARD_RST# SOFT_RST# 0.1µf µP Manual Reset Switch Figure 1 – Applications schematic using the SMR101 to supervise an embedded controller. As shown, the SMR101 implements a two-level RESET function including external manual input. SIMPLIFIED APPLICATIONS DRAWING FEATURES & APPLICATIONS INTRODUCTION
Summit Microelectronics, Inc 2091 2.1 4/21/2005 2 Figure 2 – SMR101 Operation and timing diagram. The SMR101 is a programmable reset controller that monitors the power supply in µP and digital systems for under voltage conditions The integrated feature set provides excellent circuit reliability and low cost by eliminating external components while the programmable settings allow “on the fly” adjustments necessary for modern control techniques. The device performs several functions: it first asserts a “soft” reset signal whenever the VDD supply voltage declines below a preset threshold, keeping it asserted for a programmable time period after VDD has risen above the reset threshold. The part also provides a push button input with two programmable delays for hierarchical manual system reset. The open-drain SOFT_RST# and HARD_RST# outputs have on-chip 100K pull-up resistors and do not require external pull-up resistors unless more drive current is needed (see figure 3). The SOFT_RST# comparator is designed to ignore fast transients on VDD, and the output is guaranteed to be in the correct logic state for VDD down to 1V. Low supply current makes the SMR101 ideal for use in portable equipment. The RESET_IN# input includes a programmable hold-down delay timer for use with a push button switch for consumer equipment such as set-top boxes and PCs. A microprocessor’s (µP’s) reset input starts the µP in a known state. The SMR101 asserts a SOFT_RST# to prevent code execution errors during power-up, power-down, or UnderVoltage (UV) conditions whenever the VDD supply voltage declines below a programmed limit (V MON). There are 8 programmable voltage settings to trigger the SOFT_RST# output. SOFT_RST# stays asserted for a programmable period after VDD has risen above the reset threshold. The SOFT_RST# signal is also asserted whenever the RESET_IN# input is asserted for a programmed delay. There are 8 programmable timing settings (T RESET_SR) to trigger SOFT_RST# output. The HARD_RST# signal is also asserted whenever the RESET_IN# input is asserted for a separate programmed delay. There are 8 programmable timing settings (T RESET_HR) to trigger the HARD_RST# output. It is recommended that the soft reset time be of a shorter duration than that of the HARD_RST#. In addition to issuing a reset to the µP during power- up, power-down, and brow nout conditions, the SMR101 is immune to short-duration VDD transients (glitches) due to an internal glitch filter. A external 0.1µF bypass capacitor mounted as close as possible to the VDD pin provides additional transient immunity. Since the SOFT_RST# and HARD_RST# outputs are open drain, the device interfac es easily with µPs that have bidirectional-reset pins. Connecting the SOFT_RST# output directly to the µP’s RESET pin allows either the µP or the SMR101 to assert a reset. GENERAL DESCRIPTION VDD HARD_RST# SOFT_RST# RESET_IN# Push-Button Input TRESET TRESET_HR TRESET VMON TGLITCH Push-Button Released TRESET Push-Button Engaged Push-Button Engaged Push-Button Released TRESET TRESET_SR TRESET_SR
Summit Microelectronics, Inc 2091 2.1 4/21/2005 3
8 KHz
Oscillator, +/-10% accurate Programmable Delay Generator/ Logic z zz Up Count MSB z Programmable Hold-Down Time, 0.125 to 40 Sec VDD GND User Reset Pushbutton z Vref Glitch Filter z Reset Input zzzz zzzz RESET _IN# HARD_RST# SOFT_RST# 2.7V_5.5V SOFT_RST at 2.30V-4.5V 100k z 100k z 100k z zPROG z z Programmable Duration Reset Output z z Figure 3 – SMR101 Internal Block Diagram. Pushbutton Input delay (seconds) Voltage Monitor Threshold (V ) RESET Timeout Period (ms) Register Value HARD_RST# Register Value SOFT_RST# Register Value Voltage Register Value Time 000 0.5 000 0.125 000 4.50 00 1 001 1 001 0.25 001 4.25 01 25 010 2 010 0.5 010 2.97 10 100 011 4 011 1 011 2.81 11 200 100 8 100 2 100 2.70 101 16 101 4 101 2.55 110 32 110 8 110 2.43 111 40 111 10 111 2.30 Figure 4 – SMR101 Register Maps. The SMR101 is user programmable using the SMX3199 Programmer and the SMR101 Windows GUI. INTERNAL BLOCK DIAGRAM
Summit Microelectronics, Inc 2091 2.1 4/21/2005 4 PIN DESCRIPTIONS PACKAGE AND PIN CONFIGURATION RESET_IN# VDD HARD_RST#GND PROG A1 A2 B1 B2 C1 C2 SOFT_RST# PROG NC RESET_IN# GND VDD NC SOFT_RST# HARD_RST# CSP Ball Number SOIC Lead Number Pin Type Pin Name Pin Description A1 1 I PROG High voltage programming pin. Connected to ground during normal operation. A2 8 PWR VDD Positive supply voltage. B1 4 PWR GND Ground pin. B2 5 O HARD_RST# Open Drain active low Hard Reset Out indicator. Internally connected to VDD through a 100KΩ resistor. C1 3 I RESET_IN# De-bounced push button switch input. Internally connected to VDD through a 100KΩ resistor. Also used as the Data input programming pin. C2 6 O SOFT_RST# Open Drain active low Soft Reset Out indicator. Internally connected to VDD through a 100KΩ resistor. NA 2,7 NC NC No Connect
6 Ball Ultra CSPTM
8 Lead SOIC
PACKAGE AND PIN CONFIGURATION
Summit Microelectronics, Inc 2091 2.1 4/21/2005 5 Terminal Voltage with Respect to GND: Note - The device is not guarant eed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. Temperature Range (Commercial). ……….0 °C to +70°C Note 1 – The device can operate over a supply range of 2.7V to 5.5V. Package Thermal Resistance (Θ JA) Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit VDD Supply Voltage Range 2.7 3.3 5.5 V VDD = 3.3V, no RESET in progress. 40 50 IDD Power Supply Current VDD = 5.5V, no RESET in progress. 55 65 µA tGLITCH Glitch filter time 15 18 µs VIH Input High Voltage VDD = 3.3V 0.9xVDD VDD V VIL Input Low Voltage VDD = 3.3V 0.1xVDD V VOL Open Drain Outputs (HARD_RST#, SOFT_RST#) ISINK = 1mA 0 0.4 V IOL Output Low Current 0 1.0 mA DC OPERATING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATION CONDITIONS
Summit Microelectronics, Inc 2091 2.1 4/21/2005 6 (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min. Typ. Max Unit 0.80 1 1.20 ms 20 25 30 ms 80 100 120 ms TRESET Reset Output Timeout period Programmed Default = 100ms 160 200 240 ms 4.41 4.5 4.59 V 4.16 4.25 4.34 V 2.91 2.97 3.03 V 2.75 2.81 2.87 V 2.64 2.7 2.76 V 2.5 2.55 2.6 V 2.38 2.43 2.48 V VMON Voltage Monitor Threshold1 Programmed Default = 2.97V 2.25 2.3 2.35 V 0.10 0.125 0.15 s 0.20 0.25 0.30 s 0.40 0.5 0.60 s 0.80 1 1.20 s 1.60 2 2.40 s 3.20 4 4.80 s 6.40 8 9.60 s TRESET_SR Programmable Reset Hold- Down Delay times (soft reset) Programmed Default = 0.25s 8 10 12 s 0.40 0.5 0.60 s 0.80 1 1.20 s 1.60 2 2.40 s 3.20 4 4.80 s 6.40 8 9.60 s 12.80 16 19.20 s 25.60 32 38.40 s TRESET_HR Programmable Reset Hold- Down Delay times (hard reset) Programmed Default = 4s 32 40 48 s Note 1 - Voltage monitor threshold accuracies are relative to factory programmed setting, deviation from this setting can result in errors exceeding those stated above. AC OPERATING CHARACTERISTICS
Summit Microelectronics, Inc 2091 2.1 4/21/2005 7
8 Lead SOIC Package
.05 (1.27) TYP.
8 Pin SOIC
0.150 - 0.157 (3.80 - 4.00) 0.189 - 0.196 (4.80 - 5.00) 0.053 - 0.069 (1.35 - 1.75) 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.010 (0.10 - 0.25) 0.016 - 0.050 (0.40 - 1.27) ×45º 0.010 - 0.020 (0.25 - 0.50) 0.228 - 0.244 (5.80 - 6.20) Ref. JEDEC MS-012 Inches (Millimeters) PACKAGE OUTLINE
Summit Microelectronics, Inc 2091 2.1 4/21/2005 8
6 Ball Ultra CSPTM – Chip Scale Package
PACKAGE OUTLINE (CONTINUED)
Summit Microelectronics, Inc 2091 2.1 4/21/2005 9 SUMMIT SMR101S AYYWW Pin 1 Annn Summit Part Number Date Code (YYWW) Part Number suffix (Contains Customer specific ordering requirements) Lot tracking code (Summit use) Drawing not to scale SS Status Tracking Code (01, 02,...) (Summit Use) Product Tracking Code (Summit use) SMR101 E Package E = 6 Ball Ultra CSPTM Summit Part Number nnn Part Number Suffix Customer specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. S = 8 Lead SOIC The default device ordering number is SMR101E-316 and is programmed as described in the AC Operating Characteristics table on page 6 and tested over the commercial temperature range. NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. SUMMIT Mi croelectronics, Inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and ma kes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc . shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affe ct their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receive s written assurances, to its satisfaction, that: (a) the risk of in jury or damage has been minimized; (b) the user assumes all su ch risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Device Errata sheets can be accessed at: http://www.summitmicro.com/errata/ Revision 2.1 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at http://www.summitmicro.com for data sheet updates. © Copyright 2005 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE ANALOG FOR A DIGITAL WORLD™ Ultra CSP TM is a registered name of FlipChip International, LLC.
6 Ball Ultra CSPTM 8 Lead SOIC
(Customer specific ordering requirements) Date Code Y = Single digit year Drawing not to scale Product Tracking Code (Summit use)