SMP9517 SUMMIT | Alldatasheet

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© SUMMIT MICROELECTRONICS, Inc. 2000 • 300 Orchard City Drive, Suite 131  Campbell, CA 95008  Phone 408-378-6461  Fax 408-378-6586  www.summitmicro.com Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc. 2035 3.0 5/10/00 SMP9517

FEATURES

Digitally Controlled Electronic Potentiometer

  • 7-Bit Digital-to-Analog Converter (DAC) – Independent Reference Inputs – Differential Non-Linearity of ±0.5LSB max – Integral Non-Linearity of ±1LSB max V OUT Value in EEPROM for Power-On Recall – Equivalent to 128-Step Potentiometer  Unity Gain Op Amp Drives up to 1mA  Simple Trimming Adjustment – Debounced Pushbutton Interface  Low Noise Operation  “Clickless” Transitions between DAC Steps  No Mechanical Wear-out Problem – 1,000,000 Stores (typical) – 100 Year Data Retention  Operation from 2.7V to 5.5V Supply  Low Power: 1mW max at 5V Nonvolatile DACPOT™ Electronic Potentiometer With Debounced Push Button Interface OVERVIEW The SMP9517 DACPOT trimmer is an 7-bit nonvolatile DAC designed to replace mechanical potentiometers. The SMP9517 includes a unity-gain amplifier to buffer the DAC output and enables V OUT to swing from rail to rail. The DACPOT trimmer operates over a supply voltage range of 2.7V to 5.5V. The SMP9517’s simple pushbutton input provides an ideal interface for operator adjusted equipment. This interface allows for quick and easy adjustment of even the most sophisticated systems. The SMP9517 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. For higher resolution applications the pin-compatible S9518 pro- vides 256 steps with the same pushbutton interface. Both the SMP9517 and the S9518 provide ‘clickless’ transitions of V OUT . FUNCTIONAL BLOCK DIAGRAM DWN# VDD VOUT57-Bit E2PROM VL6 VH3 7-Bit Data Register Debounce Circuit & Write Control Logic 7-Bit DAC UP# STR# GND 2035 T BD 3.0

SUMMIT MICROELECTRONICS, Inc.2035 3.0 5/10/00 Analog Section The SMP9517 is an 7-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts 7-bit digital values into equivalent analog output voltages in proportion to the applied reference voltage. Reference Inputs The voltage differential between the V L and VH inputs sets the full-scale output voltage range. VL must be equal to or greater than ground (a positive voltage). VH must be greater than VL and less than or equal to VDD . See specifications for guaranteed operating limits. Output Buffer Amplifier The voltage output is from a precision unity-gain follower that provides a rail-to-rail output swing. Digital Interface The interface provides simple pushbutton control of an up/down counter that drives the DAC. The DAC output is a ratiometric voltage output. UP# is an active low pushbutton input. An internal pull-up resistor, with nominal value of 50kΩ , eliminates an exter- nal resistor. A 30ms debounce period is included in the input timing to prevent multiple pulsing of the counter. Either a switch closure to ground or a low logic level will, after the debounce time, change the potentiometer tap position. UP# moves the output voltage towards the V H reference input. If the UP# pushbutton is kept depressed the counter will continue to increment at the rate of one count every 250ms for one second. After one second the counter increments faster, one count every 50ms, until the pushbutton is released. Changes to the DAC output using the UP# input do not alter the data stored in EEPROM. PINOUT DWN# is an active low pushbutton input that decrements the counter and moves the potentiometer output voltage towards the V L reference input. The DWN# control input also includes an internal 50kΩ pull-up resistor and a 30ms debounce period to prevent multiple pulsing. A low logic level will also change the potentiometer tap position after the debounce period. If the DWN# pushbutton is kept depressed the counter continues to decrement at the rate of one count every 250ms for one second. After one second the counter decrements at one count every 50ms until the pushbutton is released. Changes to the DAC output using the DWN# input do not alter the data stored in EEPROM. STR# This input can be used in two ways: 1) If the input is tied low, then AUTOSTORE is enabled. When V DD powers down, an automatic store cycle takes place that updates the nonvolatile EEPROM memory. 2) STR# is an active low pushbutton input that also updates the nonvolatile memory. The input is debounced but does not have an internal pull-up resistor. For every valid push the SMP9517 will store the current potentiometer position to EEPROM. PIN NAMES 2035 Table01 3.0 lobmySn oitpircseD #PUV sevom,tupniBP TUO Vdrawot H tupni #NWDV sevom,tupniBP TUO Vdrawot L tupni VH V FER hgih DNGd nuorG V TUO tuptuoegatlovdemmirT VL V FER wol #RTS tupnilortnocagnidivorp,tupnierotS noitarepoerotsaetaitiniot V DD )V5.5otV7.2(egatlovylppuS UP# DWN# VH GND VDD STR# VL VOUT 8-Pin SOIC 2035 T PCon 3.0

SUMMIT MICROELECTRONICS, Inc.2035 3.0 5/10/00 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias –55°C to 125°C Storage Temperature –65°C to 150°C Voltage on pins with reference to GND: Analog Inputs –0.5V to VDD +0.5V Digital Inputs –0.5V to VDD +0.5V Analog Outputs –0.5V to VDD +0.5V Digital Outputs –0.5V to VDD +0.5V Lead Solder Temperature (10s) 300 °C COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operation sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RECOMMENDED OPERATING CONDITIONS noitidnoC. niM. xaM erutarepmeTC º04– Cº58 V DD V7.2V 5.5 2035 Table02 3.0

5SUMMIT MICROELECTRONICS, Inc. 2035 3.0 5/10/00 RELIABILITY CHARACTERISTICS 2035 Table03 3.0 Symbol Parameter Conditions Min. Typ. Max. Units Accuracy INL Integral Non-Linearity I LOAD = 100µA, 0.5 ±1 LSB DNL Differential Non-Linearity ILOAD = 100µA, 0.1 ±0.5 LSB Guaranteed but not tested References VH VREFH Input Voltage V REFL VDD V VL VREFL Input Voltage Gnd V REFH V R IN VREFH to VREFL Resistance 38k Ω TCR IN Temperature Coefficient VREFH to VREFL 600 ppm/ °C of RIN Analog G EFS Full-Scale Gain Error DATA = FF HEX ±1 LSB Output VOUT ZS Zero-Scale Output Voltage DATA = 00HEX 02 0 m V TCV OUT VOUT Temperature V DD = 5, ILOAD = 50µA, Coefficient V REFH = 5V, VREFL = 0V 50 µV/ °C Guaranteed but not tested IL Amplifier Output Load Current -200 1000 µA R OUT Amplifier Output ResistanceILOAD = 100µA VDD = 5V 10 Ω VDD = 3V 20 Ω PSRR Power Supply Rejection I LOAD = 10µA 1 LSB/V eN Amplifier Output Noise f = 1kHz, VDD = 5V 90 nV/ √H Z THD Total Harmonic Distortion V IN = 1VRMS , f = 1kHz 0.08 % BW Bandwidth –3dB V IN = 100mVRMS 300 kHz DAC DC ELECTRICAL CHARACTERISTICS VDD = 2.7V to 5.5V, VREFH = VDD , VREFL = 0V, TA = –40°C to 85°C, unless specified otherwise 2017 PGM T3.4 lobmySr etemaraP. niM. xaMt inU V PAZ ytilibitpecsusDSE0 002V I HTL puhctaL0 01A m T RD noaitneterataD0 01s raeY N DNE ecnarudnE0 00,000,1s erotS

SUMMIT MICROELECTRONICS, Inc.2035 3.0 5/10/00 2017 PGM T5.1 DC ELECTRICAL CHARACTERISTICS VDD = 2.7V to 5.5V, VH = VDD , VL = 0V, Unless otherwise specified Notes: 1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference resistor chain. 2. UP# and DWN# have internal pull-up resistors of approximately 50kΩ . When the input is pulled to ground the resulting output current will be VDD /50ký. Limits Symbol Parameter Min. Typ. Max. Units fGAP Time Between Two Separate Push Button Events 0 µs tDB Debounce Time 30 60 ms tS SLOW After Debounce to Wiper Change on a Slow Mode 100 250 375 ms tS FAST Wiper Change on a Fast Mode 25 50 75 ms tPU Power-Up to Wiper Stable 500 µs tR VDD VDD Power-Up Rate 0.2 50 mV/µs tASTO AUTOSTORE Cycle Time (Note 3) 4 2 ms VASTH AUTOSTORE Threshold Voltage (Note 3) 4.6 5.5 V tASEND AUTOSTORE Cycle End Voltage 3.5 V AC OPERATING CHARACTERISTICS VDD = 4.5V to 5.5V 2017 PGM T6.0 Symbol Parameter Conditions Min Max Units IDD Supply Current STR# = 1.2 mA during store (Note 1) ISB Supply Standby Current 200 µA IIH Input Leakage Current V IN = VDD 10 µA IIL Input Leakage Current (Note 2) V IN = 0V -100 µA VIH High Level Input Voltage 2 V DD V VIL Low Level Input Voltage 0 0.8 V Notes: 3. tASTO and VASTH are characterized and periodically sampled, but not 100% tested.

FIGURE 3. AUTOSTORE CYCLE TIMING DIAGRAM FIGURE 4. SLOW MODE TIMING FIGURE 5. FAST MODE TIMING

1 Second

SUMMIT MICROELECTRONICS, Inc.2035 3.0 5/10/00 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc.

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

ORDERING INFORMATION

.228 (5.80) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.

8 Places

.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00)1 .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2 SMP9517 S Base Part Number Package S=8-Pin SOIC 2035 Tree 3.0