SMM766B

SMM766B SUMMIT | Alldatasheet

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© SUMMIT Microelectronics, Inc. 2006 • 757 N. Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266 The Summit Web Site can be accessed by “right” or “left” mouse clicking on the link: http://www.summitmicro.com/ 2122 3.0 5/5/2008 1 Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link

Extremely accurate (±0.2%) Active DC Output Control (ADOC™)
Sequence-Link™ provides sequencing of up to 48 channels
ADOC automatically adjusts supply output voltage level under all DC load conditions
Monitors, controls, and margins up to 6 supplies from 0.3V to 5.5V with 1.25V Vref
Programmable power-on/-off sequencing
Operates from any intermediate bus supply from 6V to 14V and from 2.7V to 5.5V
Monitors 12V input VDD and temperature sensor
Wide margin/ADOC range from 0.3V to VDD
Monitors two general-purpose 10-bit ADC inputs
I2C 2-wire serial bus for programming configuration and monitoring status, including 10-bit ADC conversion results
2 programmable Under Voltage (UV) and Over Voltage (OV) threshold limits for each of 11 monitored inputs
2k-bit general purpose nonvolatile memory

Applications

Monitor/control distributed and POL supplies
Multi-voltage processors, DSPs, ASICSs used in telecom, CompactPCI or server systems The SMM766B is an Active DC Output power supply Controller (ADOC TM) that monitors, margins, and cascade sequences. The ADOC feature is unique and maintains extremely accurate settings of system supply voltages to within ±0.2% under full load. The SMM766B actively controls up to 6 DC/DC converters and can be linked with up to 7 other Sequence-Link™ devices to accommodate sequencing of up to 48 channels. Control of t he DC-DC converters is accomplished through the use of a Trim or Regulator VADJ/FB pin to adjust the out put voltage. For system test, the part also controls margining of the supplies using I 2C commands. It can margin supplies with either positive or negative control within a range of 0.3V to VDD, depending on the specified range of the converter. The SMM766B also intelligently sequences or cascades the power supplies on and off in any order using enable outputs with programmable polarity. It can operate off any intermediate bus supply ranging from 6V to 14V or from 5.5V to as low as 2.7V. The part monitors 6 power supply channels as well as VDD, 12V input, two general-purpose analog inputs and an internal temperature sensor using a 10-bit ADC. The 10-bit ADC can measure the value on any one of the monitor channels and output the data via the I 2C bus. A host system can communicate with the SMM766B status register, margining and utilize 2K- bits of nonvolatile memory. SIMPLIFIED APPLICATIONS DRAWING TRIMB PUPB VMB TRIM_CAPB CAPB TRIMA PUPA VMA TRIM_CAPA CAPA SMM766B µP/ ASIC VDD RST# HEALTHY MR# 3.3VIN (+2.7V to +5.5V Range) RESET# READY HEALTHY 12VIN 12VIN (+6V to +14V Range) External or Internal TEMP SENSOR AIN1 2.5VIN 1.2VIN 12V SDA SCLI2C BUS 3.3V VREF VIN TRIM Vout DC/DC Converter A ON/OFF VIN TRIM Vout DC/DC Converter B ON/OFF External or Internal REFERENCE Environmental SENSOR AIN2 DC/DC Converter C, E DC/DC Converter D, F 2 of 6 DC-DC Converters shown SEQ_LINK To additional Sequence- Link devices Figure 1 – Applications schematic using the SMM766B controller to actively control the output levels of up to 6 DC/DC converters while also providing power-on/off, cascade sequencing and output margining. Note: This is an applications example only. Some pins, components and values are not shown. INTRODUCTION FEATURES & APPLICATIONS

Summit Microelectronics, Inc 2122 3.0 5/5/2008 2 TABLE OF CONTENTS Internal Functional Block Diagram……..… ……………4 Recommended Operating Conditions……… …..……..8 DC Operating Characteristics………………….. …..8-11 I2C 2-Wire Serial Interface AC Operating DEVICE OPERATION Power-On Cascade Sequencing….………… …….….16 Power-Off Cascade Sequencing…………… …….…..18 Recommended Use Of The Power On Pin……… ….20 I2C Programming Information Command And Status Registers……………… ……...30 General-Purpose Memory Read/Write……..…… …..33 Command And Status Register Read/Write…… …...34 Default Configuration Register Settings………. ……..35

Summit Microelectronics, Inc 2122 3.0 5/5/2008 3 GENERAL DESCRIPTION The SMM766B is a highly integrated and accurate power supply controller, monitor, and sequencer. Each device has the ability to autom atically control, monitor and cascade sequence up to 6 power supplies. In addition, the SMM766B includes Sequence-Link  a feature that allows for the seamless integration of other Sequence-Link devices to accommodate sequencing of up to 48 channels. The SMM766B can monitor the VDD input, the 12V input, two general- purpose analog inputs, and the internal temperature sensor. The SMM766B has four operating modes: power-on sequencing mode, monitor mode, supply margining mode using Active DC Output Control (ADOC TM), and power-off sequencing mode. Power-on sequencing is initiated by the rising edge of the PWR_ON pin. During power-on sequencing the SMM766B will sequence the power supply channels on, in any order, by activating the PUP outputs and monitoring the respective converter voltages to ensure cascading of the supplies. Cascade sequencing is the ability to hold off the next sequenced supply until the first supply reaches a programmed threshold. A programmable sequence termination timer can be set to disable all channels if the power-on sequence stalls. Once all supplies have sequenced on and the voltages are above the UV settings, the ADOC, if enabled, will bring the supply voltages to their nominal settings. During this mode, the HEALTHY output will remain inactive and the RST# output will remain active. Once the power-on sequencing mode is complete, the SMM766B enters monitor mode. In the monitor mode, the SMM766B starts the ADOC control of the supplies and adjusts the output voltage to the programmed setting under all load conditions, especially useful for supplies without sense lines. Typical converters have ±2% accuracy ratings for their output voltage; the ADOC feature of the SMM766B increases the accuracy to ±0.2% (using a ±0.1% external voltage reference). The part also enables the triggering of outputs by monitored fault conditions. The 10-bit ADC cycles through all 11 channels every 2ms and checks the conversions against the programmed threshold limits. The results can be used to trigger RST#, HEALTHY and FAULT# outputs as well as to initiate a Fault-Triggered power-off or force-shutdown operation. While the SMM766B is in its monitoring mode, an I command to margin the supply voltages can bring the part into margining mode. In margining mode the SMM766B can margin 6 supply voltages in any combination of nominal, high and low voltage settings using the ADOC feature, all to within ±0.2% using a ±0.1% external reference. The margin high and low voltage settings can range from 0.3V to VDD around the converters’ nominal output voltage setting depending on the specified margin range of the DC- DC converter. During this mode the HEALTHY output is always active and the RST# output is always inactive regardless of the voltage threshold limit settings and triggers. Furthermore, the triggers for power-off and force-shutdown are temporarily disabled. The power-off sequencing mode can only be entered while the SMM766B is in the monitoring mode. It can be initiated by either bringing the PWR_ON pin low, through I 2C control, or triggered by a channel exceeding its programmed thresholds. Once power- off is initiated, it will di sable the ADOC function and sequence the PUP outputs off in the reverse order as power-on sequencing. To ensure cascading of the supplies during power-off sequencing all supplies will be monitored as they tu rn off. The sequence termination timer performs a forced-shutdown operation if power-off sequencing stalls. 2.5V 2.7V 1.8V 2.0V 1.5V VDD (+2.7V to +5.5V) or 12VIN ( +8V to +15V) 2 3 45SEQUENCE POSITION 1.2V Figure 2 – Example power supply sequencing and system start-up initialization using the SMM766B. Cascade sequencing ensures that all supplies in the previous sequence position are valid before the next channel is released. Using the SMM766B any order of supply sequencing can be applied.

Summit Microelectronics, Inc 2122 3.0 5/5/2008 4 AIN2 10-Bit ADC AIN1 VMA Active DC Output Control (ADOCTM) CAPA VMF CAPF TRIMA TRIM_CAPA TRIMF TRIM_CAPF VREF FILT_CAP 12VIN VDD PUPA Cascade Sequence Control PUPB PUPC PUPD PUPE PUPF FS#PWR_ON 3.6V or 5.5V Regulator Power Supply Arbitrator Temperature Sensor VDD_CAP Output Control MR# RST# HEALTHY FAULT# Memory, Limit and Status Registers I2C Interface SDA SCL GND UVLO Control SEQ_LINK Figure 3 – SMM766B Internal Functional Block Diagram. INTERNAL FUNCTIONAL BLOCK DIAGRAM

Summit Microelectronics, Inc 2122 3.0 5/5/2008 5 PIN DESCRIPTIONS Pin Number Pin Type Pin Name Pin Description

1 DATA SDA SDA (Serial Data) is an open drain bi-directional pin used as the I 2C data

line. 2 CLK SCL SCL (Serial Clock) is an open drain input pin used as the I2C Clock line.

3 IN A2

The A2 (Address bit 2) pin is biased either to VDD_CAP or GND. When communicating with the SMM766B over the 2-wire I 2C bus, A2 provides a mechanism for assigning a unique bus address.

4 IN MR#

MR# (Manual Reset) is an active low input. When asserted the RST# output will become active. When de-asserted the RST# output will go inactive immediately after a reset timeout period (t RTO) if there are no RST# trigger sources active. This timeout period makes it suitable to use as a pushbutton for manual reset purposes.

5 I/O PWR_ON

PWR_ON (Power On) is an open drain bi-directional pin. On the rising edge of PWR_ON the part will sequence the supplies on, during the falling edge the part will sequence the supplies off. This pin must be tied high through an external pull-up resistor. Note: The SMM766B does not monitor for faults during power-on/off sequencing.

6 I/O FS#

FS# (Force Shutdown) is an open drain ac tive low bi-directional pin. FS# is used to immediately turn off all converter enable signals (PUP outputs) when a fault is detected. Whenever FS# is asserted PWR_ON will automatically be pulled low as well. This pin must be tied high through an external pull-up resistor.

7 OUT FAULT#

The FAULT# pin is an active low open drain output. Active when a programmed fault condition exists on AIN1, AIN2, or the internal temperature sensor. When used, FAULT# should be pulled high through an external pull- up resister.

8 OUT HEALTHY

HEALTHY is an active high open drain output. Active when all programmed power supply inputs and monitored input s are within OV and UV limits and ADOC has begun. When used, HEALTHY should be pulled high through an external pull-up resistor.

9 OUT RST#

RST# (Reset) is an active low open drain output pin. Active when a programmed fault condition exists on an y power supply inputs or monitored inputs, when MR# is active, or when ADOC is not ready. RST# has a programmable timeout period with options for 0.64ms, 25ms, 100ms and 200ms. When used, RST# should be pulled high through an external pull-up resistor. 10 IN AIN1 AIN1 (Analog Input 1) is a general-purpose monitored analog input. 11 IN AIN2 AIN2 (Analog Input 2) is a general-purpose monitored analog input. 12 GND GND Ground.

Summit Microelectronics, Inc 2122 3.0 5/5/2008 6 Pin Number Pin Type Pin Name Pin Description

13 I/O SEQ_LINK

SEQ_LINK (Sequence-Link™) is an open drain bi-directional pin. This pin should be attached to other Sequence-Link devices, during linked operation. SEQ_LINK must be pulled high through an external pull-up resistor when multiple Sequence-Link devices are used. When the SMM766B is not used with another Sequence-Link device, SEQ _LINK should be tied directly to ground.

14 I/O VREF

VREF (Voltage Reference) is a bi-directional analog pin. VREF is used for Active DC Output Control and margining. VREF can be programmed to output the internal 1.25V reference.

15 CAP FILT_CAP FILT_CAP (Filter Capacitor) is an external capacitor input used to filter VMX

inputs. 41,36, 31,26, 21,16 IN VM X VMX (Voltage Monitor) pins are analog inputs. These pins are normally attached to the positive converter sense line, VMA through VMF. 42,37, 32,27, 22,17 CAP CAP X External capacitor input used to filter the VMX inputs to the 10-bit ADC, CAPA through CAPF. This provides an RC filter where R = 25kΩ.. 43,38, 33,28, 23,18 OUT PUP X PUPX (Power Up Permitted) pins are programmable active high/low open drain converter enable output, PUPA through PUPF. 44,39, 34,29, 24,19 OUT TRIM X Output voltage used to control the output of DC/DC converters, TRIMA through TRIMF. 45,40, 35,30, 25,20 CAP TRIM_CAP X TRIM_CAPX is an analog output pin used to control the output of DC/DC converters. If the ADOC/margining functionality is not used on a channel the associated TRIM_CAPX pin should be left floating. There are 6 TRIM_CAPX pins, TRIM_CAPA through TRIM_CAPF.

46 PWR VDD Power supply of the part

47 PWR 12VIN 12VIN (12 Volt Input) is a power supply input internally regulated to either

3.6V or 5.5V.

48 CAP VDD_CAP VDD_CAP (VDD Capacitor) is an external capacitor input used to filter the

internal supply. PIN DESCRIPTIONS (Cont.)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 7 PACKAGE AND PIN CONFIGURATION

48 LEAD TQFP

MR# PWR_ON FS# FAULT# HEALTHY RST# AIN1 AIN2 GND SEQ_LINK VREF FILT_CAP VMF CAPF PUPF TRIMF TRIM_CAPF VME CAPE PUPE TRIME VMB TRIM_CAPC TRIMC PUPC CAPC VMC TRIM_CAPD TRIMD PUPD CAPD VMD TRIM_CAPE VDD_CAP 12VIN VDD TRIM_CAPA TRIMA PUPA CAPA VMA TRIM_CAPB TRIMB PUPB CAPB

Summit Microelectronics, Inc 2122 3.0 5/5/2008 8 Terminal Voltage with Respect to GND: PUP Note A - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stre ss ratings only and functional operation of the device at these or any other conditions outs ide those listed in the operational sections of the specificat ion is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. Package Thermal Resistance (θJA) Moisture Classification Level 1 (MSL 1) per J-STD- 020. MSL 3 for 100% Sn, RoHS compliant, see

ordering information

Note B – Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification below. RELIABILITY CHARACTERISTICS DC OPERATING CHARACTERISTIC (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max Unit VDD Supply voltage 2.7 5.5 V Internally regulated to 5.5V 10 14 V 12VIN Supply voltage Internally regulated to 3.6V 6 14 V IDD Power supply current from VDD All TRIM pins floating, 12VIN floating 1.4 5 mA I12VIN Power supply current from 12VIN All TRIM pins floating, VDD floating 3 5 mA TRIM characteristics TRIM sourcing maximum current 1.5 mA ITRIM TRIM output current through 100Ω to 1.0V, Note 10 TRIM sinking maximum current 1.5 mA VTRIM Margin and ADOC range Depends on TRIM range of DC-DC converter VREF/4 VDD V TRIM_CAP characteristics ITRIM_CAP TRIM output current through 1uF capacitor to ground, Note 2 Max acceptable board and cap leakage is 50nA 100 nA All other input and output characteristics Internally regulated to 3.6V 3.4 3.6 3.8 V VVDD_CAP VDD_CAP voltage Internally regulated to 5.5V 5.3 5.5 5.7 V VSENSE Positive sense voltage VM pin +0.3 VDD_CAP V VMONITOR Monitor threshold step size VM, AIN1/AIN2 pins 5 mV OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS

Summit Microelectronics, Inc 2122 3.0 5/5/2008 9 DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max Unit VDD = 2.7V 0.7 x VDD_CAP V VIH Input high voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#),Note 3 VDD = 5.0V 0.7 x VDD_CAP V VDD = 2.7V 0.3 x VDD_CAP V VIL Input low voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#), Note 3 VDD = 5.0V 0.3 x VDD_CAP V VDD_CAP = 3.6V 0.7 x VDD_CAP V VIH Input high voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#), Notes 3, 10 VDD_CAP = 5.5V 0.7 x VDD_CAP V VDD_CAP = 3.6V 0.3 x VDD_CAP V VIL Input low voltage (MR#, SDA, SCL, PWR_ON, SEQ_LINK, FS#), Notes 3, 10 VDD_CAP = 5.5V 0.3 x VDD_CAP V VOL Open drain outputs (RST#, FS#, PWR_ON, HEALTHY, FAULT#, PUPx, SEQ_LINK) I SINK = 1mA 0 0.4 V IOL Output low current, Note 6 0 1.0 mA IIN Leakage current on SDA, SCL SDA or SCL are at 3.6V 1.0 µA VOLSDA Output low voltage for SDA I OLSDA = 3mA 0 0.4 V Commercial temp range -4 ±4 +4 oC TSA Internal temperature sensor accuracy, Note 5, 8 Industrial temp range -6 ±6 +6 oC TMONITOR Temperature threshold step size Internal temp sensor 0.25 oC T = +25°C -0.4 +0.4 % VREF Internal 1.25VREF Output Voltage Accuracy T = -40°C to +85°C -0.8 +0.8 % Ext VREF External V REF voltage range 0.5 VDD_CAP V External VREF=1.25V, ±0.1%, Total PUPx ISINK = 6ma, VSENSE ≤ 3.5V, T = 0°C to +50°C -0.20 ±0.1 +0.20 % External VREF=1.25V, ±0.1%, Total PUPx ISINK = 6ma, VSENSE ≤ 3.5V, T = 0°C to +70°C -0.35 ±0.1 +0.35 % External VREF=1.25V, ±0.1%, Total PUPx ISINK = 6ma, VSENSE ≥ 3.5V, T = 0°C to +50°C -0.50 ±0.3 +0.50 % ADOCACC ADOC (Active DC Output Control)/Margin accuracy Internal VREF=1.25V, Total PUPx ISINK = 6ma, T = 0°C to +50°C -0.50 ±0.3 +0.50 %

Summit Microelectronics, Inc 2122 3.0 5/5/2008 10 DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max Unit VOUT VALID Minimum output valid voltage VDD_CAP voltage at which the PUP, RST#, HEALTHY and FAULT#, FS#, PWR_ON SEQ_LINK, outputs valid 1 V VDD_CAP rising 2.6 V UVLO UVLO (Under Voltage Lockout) threshold, Note 4 VDD_CAP falling 2.5 V IVDD_CAP Maximum load on VDD_CAP Note 10 10 mA AIN1/AIN2 ADC characteristics N Resolution 10 Bits MC Missing codes Minimum resolution for which no missing codes are guaranteed 10 Bits S/N Signal-to-noise Ratio Conversion rate = 500Hz 72 dB DNL Differential non-linearity -1/2 +1/2 LSB INL Integral non-linearity Note 7 -1 +1 LSB GAIN Positive full scale gain error Note 7 -0.5 ±0.16 +0.5 % OFFSET Offset error Note 7 -1 +1 LSB ADC_TC Full scale temperature coefficient ±15 PPM/ oC IMADC Analog ADC Input Impedance 10 MΩ IIVREF V REF input current 250 nA ICVREF V REF input capacitance 200 pF IRVREF V REF input impedance 1 kΩ VMA-VMF, VDD ADC characteristics Symbol Parameter Notes Min Typ Max Unit N Resolution 10 Bits MC Missing codes Minimum resolution for which no missing codes are guaranteed 10 Bits S/N Signal-to-noise Ratio Conversion rate = 500Hz 72 dB ERR_ADC Total ADC Error Total ADC Read Error (Note 11) -4 +4 LSB IMADC Analog ADC Input Impedance VMA-VMF 100 KΩ 12VIN ADC characteristics Symbol Parameter Notes Min Typ Max Unit N Resolution 10 Bits MC Missing codes Minimum resolution for which no missing codes are guaranteed 10 Bits S/N Signal-to-noise Ratio Conversion rate = 500Hz 72 dB ERR_ADC Total ADC Error Total ADC Read Error (Note 12) -4 +4 LSB

Summit Microelectronics, Inc 2122 3.0 5/5/2008 11 Note 1 – Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification. Note 2 – See Application Note 37, which describes the type of capacitors to use to obtain minimum leakage. Note 3 – All logic levels are with respect to the voltage on VDD_CAP, when supplied from VDD; VDD_CAP is equal to VDD, under no load. Note 4 – (100mV typical Hysteresis) Note 5 – Under certain operating conditions, self-heating could result in additional temperature sensor error. Note 6 – SDA not included (separate electrical specification). The device can sink more than 20mA, however total ISINK from all PUPx pins should not exceed 6mA or ADOCACC specification will be affected Note 7 – The formula for the total ADC inaccuracy is: [((ADC read voltage) +/- INL)*(range of gain error)]+range of offset erro r Note 8 – When temperature sensor is not used, as determined by the hex file configuration setting, sensor accuracy is tested for typical values only. Note 9 – The term “FAULT#” throughout this document describes a pin and output signal, whereas the term “fault” describes an operating condition that may or may not activate the FAULT# pin. The FAULT# pin can only be activated by Ain1, Ain2 and Temperature fault conditions. Note 10 – Guaranteed by Design and/or Characterization. Note 11 – ADC accuracy can be improved using the following formula: 1024 * Limit(V)_NEW/(4 * VREF_ADC) Note 12 – ADC accuracy can be improved using the following formula: 1024 * Limit(V)_NEW/(4 * VREF_ADC)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 12 Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 5 and 6 Timing diagrams. Symbol Description Conditions Min Typ Max Unit TDPON = 0.64ms TDPON = 12.5ms TDPOFF = 25ms tDPON Programmable power-on delay from restart timer expiration to PUPY active TDPOFF = 50ms -25 t DPON +25 % TDPOFF = 0.64ms tDPOFF Programmable power-off delay from VMX off to PUPY inactive TDPOFF = 12.5ms -25 t DPOFF +25 % TPRTO = 0.64ms TPRTO = 25ms TPRTO = 100ms tPRTO Programmable reset time- out delay TPRTO = 200ms -25 t PRTO +25 % TSTT = OFF TSTT = 100ms TSTT = 200ms tSTT Programmable sequence termination timer TSTT = 400ms -25 t STT +25 % tFTRD Fault-triggered restart delay Time from restart timer expiration to PUPY active after a fault-triggered power-off or force-shutdown. 2.4 s tFTRDACC Fault-triggered restart delay accuracy -25 t FTRD +25 % tCTRD Command-triggered restart delay Time from restart timer expiration to PUPY active after command- triggered power-off or force- shutdown. 12.5 ms tCTRDACC Command-triggered restart delay accuracy -25 t CTRD +25 % TADC 10-bit ADC sampling period Time for ADC conversion of all 11 channels 2 ms tADC 10-bit ADC sampling time per channel Time for one ADC conversion 182 µs TDC_CONTROL ADOC sampling period Update period for ADOC of channels A – F 1.7 ms tDC_CONTROL ADOC sampling time per channel Update time for ADOC per channel 283 µs Slow Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1µF 850 ms tMARGIN Margin Time from Nominal Fast Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1µF 85 ms tA-M_SUSPEND Auto-Monitor Suspend Period Auto-Monitor suspended indefinitely by a faulty I2C transaction 200 300 400 ms AC OPERATING CHARICTERISTICS

Summit Microelectronics, Inc 2122 3.0 5/5/2008 13 I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS –100/400 kHz T =-40C to +85C, VDD = +2.8V to +5.5V, unless otherwise noted. All voltages are relative to GND. See Figure 4 Timing Diagram. 100kHz 400kHz Symbol Description Conditions Min Typ Max Min Typ Max Units fSCL SCL clock frequency 0 100 0 400 KHz TLOW Clock low period 4.7 1.3 µs THIGH Clock high period 4.0 0.6 µs tBUF Bus free time Before new transmission – Note 13 4.7 1.3 µs tSU:STA Start condition setup time 4.7 0.6 µs tHD:STA Start condition hold time 4.0 0.6 µs tSU:STO Stop condition setup time 4.7 0.6 µs tAA Clock edge to data valid SCL low to valid SDA (cycle n) 0.2 3.5 0.2 0.9 µs tDH Data output hold time SCL low (cycle n+1) to SDA change 0.2 0.2 µs tR SCL and SDA rise time Note 13 1000 1000 ns tF SCL and SDA fall time Note 13 300 300 ns tSU:DAT Data in setup time 250 150 ns tHD:DAT Data in hold time 0 0 ns TI Noise filter SCL and SDA Noise suppression 100 100 ns tWR_CONFIG Write cycle time config Configuration registers 10 10 ms tWR_EE Write cycle time EE Memory array 5 5 ms Note 13 - Guaranteed by Design. tR tF tHIGH tLOW tSU:STA tHD:STA tSU:DATtHD:DAT tSU:STO tBUF tDHtAA SCL SDA (IN) SDA (OUT) tWR (For Write Operation Only) Figure 4 - Basic I2C Serial Interface Timing TIMING DIAGRAMS

Summit Microelectronics, Inc 2122 3.0 5/5/2008 16 A pulse of current either sourced or sunk for 5µs every 1.7ms, to the capacitors connected to the TRIM_CAP X pins adjusts the voltage output on the TRIM X pins. The voltages on the TRIM_CAP X pins are buffered and applied to the TRIM X pins. The voltage adjustments on the TRIMX pins cause a slight ripple of less than 1mV on the power supply voltages. The amplitude of this ripple is a function of the TRIM_CAP capacitor and the trim gain of the converter. Application Note 37 details the calculation of the TRIM_CAP capacitor to achieve a desired minimum ripple. Each channel can be programmed to either enable or disable the ADOC function. When disabled or not active, the TRIM X pins on the SMM766B are high impedance inputs. If disabled and not used, they can be connected to ground. The voltages on the TRIM X pins are buffered and applied to the TRIM_CAP X pins charging the capacitors. This allows a smooth transition from the converter powering up to its nominal voltage, to the SMM766B controlling that voltage, and to the ADOC nominal setting. The pulse of current can be increased to a 10X pulse of current until the power supply voltages are at their nominal settings by selecting the programmable Fast Margin option. As the name implies, this option decreases the time required to bring a supply voltage from the converter’s nominal output voltage to the ADOC nominal, high, or low voltage setting. Note: The ADC and ADOC functions are not related except that they share VR EF. ADC errors will not necessarily show up as ADOC errors and vice versa. ADOC accuracy specs do not imply the same accuracy for the ADC. See individual specs for details. POWER-ON CASCADE SEQUENCING The SMM766B can be programmed to sequence on 48 supplies occupying up to 29 sequence positions. This is accomplished using the SEQ_LINK pin. Each of the 6 channels (A-F) on a SMM766B has an associated open drain PUP output that, when connected to a converter’s enable pin, controls the turn-on of the converter. The channels are assigned sequence positions to determine the order of the sequence. The polarity of each of the PUP X outputs is programmable for use with various types of converters. Power-on sequencing is initiated on the rising edge of the PWR_ON pin. Once the PWR_ON pin is asserted high, it must remain high until the sequence-on event has completed. Should the PWR_ON pin be low after the last sequence position has exceeded its programmed UV1 limit, and for a period of 25ms afterwards, the SMM766B will perform a sequence-off event. A forced shutdown will also be issued by the SMM766B when the next PWR_ON assertion occurs if the sequence termination timer is enabled. Following the forced shutdown, the SMM766B will latch off if it is programmed for zero retries. If not programmed for zero retries, a power-on sequence will be initiated after 2.4 seconds. The SMM766B can be programmed to wait until any or all VDD, 12VIN, and Internal Temp (Internal Temperature) ADC readings are within their respective voltage threshold or temperature limits before power- on sequencing is allowed to begin. This ensures that the converters have reached their full supply voltage before they are enabled. On the rising edge of the PWR_ON pin the SMM766B will wait a power-on delay time (t DPON) for any channels in the first sequence position (position 1) and then activate the PUP X outputs for those channels. The power-on delay times are individually programmable for each channel. The SMM766B will then wait until all VM X inputs of the channels assigned to the first sequence position are above their user programmable UV1 thresholds, which is called cascade sequencing. At this point, the SMM7 66B will enter the second sequence position (position 2) and begin to timeout the power-on delay times for the associated channels. This process continues unt il all of the channels assigned to participate in the sequence have turned on and are above their UV1 threshold. Once the sequence has completed the status register indicates that all sequenced power supply channels have turned on. After the sequence has completed the SMM766B will begin the ADOC of the enabled channels. The power-on sequencing mode ends when the ADOC channels are at their nominal voltage setting. The “Ready” bit in the status r egister signifies that the voltages are at their set points. The programmable sequence termination timer can be used to protect against a stalled power-on sequence. This timer resets itself at the beginning of each sequence position. All channels in the sequence position must go above their UV1 threshold before the sequence termination timer times out (t STT) or the sequence will terminate by pulling the FS# pin low, APPLICATIONS INFORMATION (CONTINUED)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 17 initiating a Force Shutdown. The status register contains bits indicating in which sequence position the timer timed out. This sequence termination timer has four settings of OFF, 100ms, 200ms and 400ms. While the SMM766B is in the power-on sequencing mode the RST# output is held active and the HEALTHY output is held inactive regardless of trigger sources (Figure 8). The power-off and force-shutdown trigger options are also disabled while in this mode. Furthermore, the SMM766B will not respond to activity on the PWR_ON pin or to a power-off I 2C command during power-on sequencing mode. The SMM766B permits multiple supplies to occupy the same sequence position. When a sequence position is shared, each channel will be enabled after its respective power-on delay. When the last channel occupying a shared sequence position exceeds its UV1 setting the SMM766B w ill increment to the next sequence position. Any unused channel should be assigned to the null sequence position. Note: During the sequence-on event, the SMM766B ignores all limit triggers. Limit trigger monitoring begins after the last sequence position exceeds its UV1 setting when “Limit Triggers Enabled After Sequencing Ready” is selected and after ADOC is complete when “Limit Triggers Enabled After Active Control Ready”. ONGOING OPERATIONS-MONITORING MODE During ongoing operations mode, the part can monitor, and actively control via ADOC, and use the force- shutdown operation if necessary. Once the power-on sequence is complete, depending on the user programmed settings; the SMM766B will either enter the ongoing oper ations mode directly or wait for ADOC to successfully bring all channels within their nominal values. The ongoing operations mode will end when a power-off sequence, or force- shutdown has been initiated. Once the ongoing operations mode has begun, the SMM766B continues to monitor all VM X inputs, the VDD and 12VIN inputs, and two temperature sensor inputs with a 10-bit ADC. Each of these inputs is sampled and converted by the ADC every 2ms. The ADC input has a range of 0V to four times the voltage on VREF for inputs VM A-F and the VDD input. The range is extended to 12 times VREF for the 12VIN input and is reduced to two times VREF for the AIN1, AIN2 inputs. The SMM766B monitors internal temperature using the 10-bit ADC and the automonitor function. Two under-temperature and two over-temperature thresholds can be set, each with its own programmable threshold options and consecutive conversion, before trigger counter. Resolution is

0.25 C per bit scaled over the range of -128 C to

127.75 C. The temperature value can be acquired over the I 2C bus as a 10-bit signed two's complement value. The SMM766B compares each resulting ADC conversion with two programmable 10-bit under- voltage limits (UV1, UV2) and two programmable 10- bit over-voltage limits (OV1, OV2) for the corresponding input. A consecutive conversion counter is used to provide filtering of the ADC inputs. Each limit can be programmed to require 1, 2, 4 or 6 consecutive out-of-limit conversions before it is said to be in fault. One in-limit conversion will remove the fault from the threshold limit. This provides digital filtering of the monitored inputs. The ADC inputs VM A-F can use additional filtering by connecting a capacitor from the corresponding CAPX pin to ground to form an analog RC filter (R=25k Ω). The input is considered to be in a fault condition if any of its limit thresholds are in fault. Setting an OV threshold limit to full-scale (3FFHEX), or setting a UV threshold limit to 000 HEX, ensures that the limit can never be in fault. The status registers provide real-time status of all monitored inputs. The voltage threshold limits for inputs VM A-F, VDD and 12VIN can be programmed to trigger the RST# and HEALTHY outputs as well as a Fault-Triggered force- shutdown and power-off operation when exceeded. The threshold limits for the internal temperature sensor and the AIN1/AIN2 inputs can be programmed to assert RST#, HEALTHY, and FAULT# output pins The HEALTHY and FAULT# outputs of the SMM766B are active as long as the monitored threshold remains in violation. The RST# output also remains active as long as the monitored threshold remains in violation. However, once the threshold violation goes away, the RST# will remain active for a programmable reset timeout period (t PRTO). The SMM766B treats Command-Triggered force- shutdown and power-off operations, those caused by I2C commands and assertion of the FS# and PWR_ON pin, differently than those caused by a Fault-Triggered forced-shutdown and power-off conditions, those caused by UV/OV violations or a sequence termination timer expiration. The mode in which either a Forced Shutdown or a power-off occurs effects how or whether th e SMM766B will restart, and the number of allowable retries permitted. APPLICATIONS INFORMATION (CONTINUED)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 18 APPLICATIONS INFORMATION (CONTINUED) AUTOMONITOR MODE The automonitor mode, responsible for monitoring all voltage thresholds and triggering the programmable options, is paused during an I 2C transaction. This is done to allow the I 2C interface to access the internal data bus that is used in the automonitor function Specifically, the automonitor is paused approximately 100ns after the falling edge of SCL during transmission of the R/W bit of a valid slave address. For normal I 2C transactions, the automonitor function is resumed following an I2C STOP issued at the end of the transaction or upon the NACK of an invalid slave address. For I2C ADC conversion transactions, which employ acknowledge polling, the automonitor function is resumed after the conversion has completed (appr. 300us after the second ACK of the transaction) and following an I 2C STOP issued at the end of the transaction or upon the NACK of an invalid slave address. During every suspension of the automonitor, a 200msec timer is activated. This timer is reset on every falling edge of SCL. The clock stage will determine the exact timeout period, typically between 200msec and 400msec. Should the I 2C transaction fail, this timer will expire and restart the automonitor. Please note that if the timer expires during an I2C transaction, the current I2C transaction is cancelled. See “Auto-Monitor Function” section for timing details and conditions under which the Automonitor timer will be asserted. TEMPERATURE SENSOR ACCURACY The internal temperature sensor accuracy is ±6 oC from -40 to +85 oC. The sensor measures the temperature of the SMM766B die and the ambient temperature. If VDD is at 5V, the die temperature is +2 oC and at 12V, it is +4 oC. In order to calculate this difference in specific applications, measure the VDD or 12VIN supply current and calculate the power dissipated and multiply by 80 oC/W. For instance, 5V and 5mA is 25mW, which creates a 2oC offset. Note: For hex files (configuration settings) that indicate no use of the temperature sensor, only the typical temperature sensor accuracy is valid. MARGINING The SMM766B has two additional ADOC voltage settings for channels A-F, margin high and margin low. The margin high and margin low voltage settings can range from 0.3V to VDD of the converters’ nominal output voltage, depending on the specified margin range of the DC-DC converter. These settings are stored in the configuration registers and are loaded into the ADOC voltage setting by margin commands issued via the I 2C bus. The channel must be enabled for ADOC in order to enable margining. The margin command registers contain two bits for each channel that decode the commands to margin high, margin low, or control to the nomi nal setting. Therefore, any combination of margin high, margin low, and nominal control is allowed in the margining mode. Once the SMM766B receives the command to margin the supply voltages, it begins adjusting the supply voltages to move toward the desired setting. When all channels are at their voltage setting, a bit is set in the margin status registers. Note: Configuration writes or reads of registers 00 HEX to 0FHEX should not be performed while the SMM766B is margining. POWER-OFF CASCADE SEQUENCING The SMM766B performs power-off sequencing in the reverse order of power-on sequencing. Power-off cascade sequencing can be initiated by the PWR_ON pin, via I 2C control or triggered by a fault condition on any of the monitored inputs. Toggling the PWR_ON pin low will initiate the power-off sequence. To enable software control of the power-off sequencing feature, the SMM766B offers an I command to initiate power-off sequencing while the PWR_ON pin is asserted. Furthermore, power-off sequencing can be initiated by a fault condition on a monitored input. Once power-off sequencing begins, the SMM766B will wait a power-off delay time (t DPOFF) for any channel in the last sequence position and then deactivate the PUP outputs for those channels. The power-off delay times are individually programmable for each channel. The SMM766B will then wait until all VM X inputs of the channels assigned to that sequence position are below the programmed OFF thresholds. At this point, the SMM766B will move to the next sequence position and begin to timeout the power-off delay times for the associated channels. This process continues until all of the channels in the sequence have turned off and are below their OFF thresholds. The status register rev eals that all sequenced channels have turned off. The power-off sequencing mode ends when all sequenced supplies are below their OFF thresholds.

Summit Microelectronics, Inc 2122 3.0 5/5/2008 19 APPLICATIONS INFORMATION (CONTINUED) The sequence termination timer can be used to protect against a stalled power-off sequence. This timer resets itself at the beginning of each sequence position. All channels in the sequence position must go below their OFF threshold before the sequence termination timer times out (t STT) or the sequence will terminate and all PUP outputs will be switched to their inactive state. This timer has four settings of: OFF, 100ms, 200ms and 400ms. The sequence termination timer can be disabled separately for power-off sequencing. While the SMM766B is in the power-off sequencing mode, the RST# output is held active and the HEALTHY output is held inactive, regardless of trigger sources (Figure 8). The force-shutdown trigger option is also disabled while in this mode. Furthermore, the SMM766B will not respond to activity on the PWR_ON pin during power-off sequencing mode. FORCE SHUTDOWN The force-shutdown operation brings all PUP X outputs to their inactive state. This operation is used for an emergency shutdown when there is not enough time to sequence the supplies off. The force-shutdown operation shuts off all sequenced channels pulls the PWR_ON pin low, and waits for the supply voltages to drop below their respective OFF thresholds before beginning a restart sequence. A force-shutdown operation can be initiated by any one of four events. The first two methods for initiating a force-shutdown are always enabled. Simply taking the FS# pin low will initiate a force-shutdown operation and maintain it until the pin is brought high again. An I 2C force-shutdown command allows the force- shutdown operation to be initiated via software control. This bit is cleared after all sequenced channels have dropped below their OFF voltage threshold. For restarting the device, the FS command needs to be cleared by writing that bi t to a zero. This will clear the command and, if the POWER-ON/OFF pin is not being forced low externally the SMM766B will begin a power-on sequence. LINKED OPERATION The SMM766B can be linked to multiple Sequence- Link devices to create a seamless multi-channel power manager. With linked operation 8 SMM766B devices in a system can sequence up to 48 supplies within 29 sequence positions. The sequencing in this mode can be interlaced, sequencing a supply from device A, then from device B, then again from device A, etc. This extended sequencing is made possible by the inclusion of a SEQ_LINK pin. For this mode of operation, the control pins, including SEQ_LINK, PWR_ON, and FS# on each device, must be tied together. In addition, the VDD and 12V supply must also be connected on all linked devices. As a consequence when multiple devices are linked together, they must be powered by the same supply. RESTART There are two possible condi tions in which a restart sequence may be initiated. The first instance occurs when either the FS# pin is asserted or the PWR_ON pin is pulled low thus initiating a command-triggered restart. The second condition occurs when a user programmable fault triggers a force-shutdown operation or a power-off seque nce thus resulting in a fault-triggered restart. In either case, the SMM766B will wait until all voltages have fallen below their user programmable OFF thresholds, after all channels are off, the PWR_ON pin will continue to be held low for a period of time dependent on the nature of the fault. When a power-off or force-shutdown condition results from a command-triggered power-off or force- shutdown, the SMM766B will automatically begin the restart procedure. When restart begins an internal timer will begin to timeout for a command-triggered Restart Delay (t CTRD) of 12.5 ms. After this time has expired the PWR_ON pin is released, allowing the power-on sequence to begin. When a power-off or force-shutdown condition results from a fault-triggered power-off or force-shutdown, the SMM766B may or may not begin the restart procedure (see PROGRAMMABLE RETRI ES), if restart begins the internal timer will begin to timeout a fault-triggered Restart Delay (t FTRD) of 2.4 s before the PWR_ON pin is released allowing the power-on Sequence to begin. If the SMM766B is programmed to wait for VDD, 12VIN, or Internal Temp to be valid (>UV1 and <OV1) before power-on sequencing may commence, then this condition will be checked after the restart timer has expired and the PWR_ON pin has been released. The conditions that may lead to a Fault-Triggered restart include any channel exceeding its user programmable thresholds (OV or UV), set to trigger either a forced-shutdown or a power-off sequence. In addition, in the event that the sequence termination timer times out before a channel reaches its UV1 or OFF threshold, during sequencing, a Fault-Triggered restart occurs.

Summit Microelectronics, Inc 2122 3.0 5/5/2008 20 APPLICATIONS INFORMATION (CONTINUED) I2C POWER OFF CONTROL Power-on sequencing is only permitted while the PWR_ON pin is active. Once the PWR_ON pin is active and the SMM766B has entered monitoring mode, an I 2C command may be issued to commence the power-off sequence. This condition will continue until an I2C “power-off clear” command is issued. PROGRAMABLE RETRIES In the event of a persistent system fault, the SMM766B may be programmed to limit the number of Fault-Triggered restarts it will allow. This programmable setting ensures that the SMM766B will not enter a hiccup-mode of operation, while still reducing susceptibility to transient fault conditions. In the event of a Fault-Tri ggered restart the fault will be registered and internally compared to the maximum number of allowable faults. If this number is exceeded then the fault condition will be latched and the PWR_ON and FS# pins will be pulled low while the RST# output is asserted. This fault condition will remain latched until power is cycled on the SMM766B, at which point the PWR_ON and FS# pins will be released, the number of faul ts will be reset zero, and the restart sequence will begin. The allowable programmable setting include one, three, and unlimited retries.

Summit Microelectronics, Inc 2122 3.0 5/5/2008 23 APPLICATIONS INFORMATION (CONTINUED) SDA Re-Enabling Auto-Monitor: Auto-Monitor Timeout SCL AUTO-MONITOR Figure 9E: Auto-monitor is re-enabled on the falling edge of the internal system clock after the auto- monitor timer has timed out. The auto-monitor timer is enabled when auto-monitor is paused and is restarted on the falling edge of SCL. SYSTEM CLOCK BA0 R/W ACK AUTO-MON TIMER ENABLE AUTO-MON TIMER TIMEOUT >25ms (T=5us)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 25 APPLICATIONS INFORMATION (CONTINUED) SDA Re-Enabling Auto-Monitor: Invalid Slave Address During an I2C A-to-D Conversion SCL AUTO-MONITOR SYSTEM CLOCK (T=5us) Figure 9H: Auto-monitor is re-enabled on the falling edge of the internal system clock after the falling edge of SCL during the NACK following a invalid slave address after the conversion has com pleted. CONVERSION_BUSY SA + R/W NACK Start SA + R/W NACK Start (Invalid SA) (Invalid SA)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 26 APPLICATIONS INFORMATION (CONTINUED) UNDERVOLTAGE LOCKOUT The internally filtered supply voltage as seen across VDD_CAP is edge-triggered to lock out false or nuisance signals during both the power-on and power- off sequences. If the VDD_CAP voltage falls below 2.5V (Figure 10), an internal undervoltage lockout (UVLO) circuit will reset all internal logic. Once power has recovered above 2.6V the SMM766B will restart as if a Command-Triggered power-off had been issued. VDD_CAP 2.5V 3.6V, 5.5V UVLO (Internal) 2.6V Figure 10 - Timing Sequence recovering from a VDD_CAP Power ‘Brown-Out’

Summit Microelectronics, Inc 2122 3.0 5/5/2008 27 Figure 11 – SMM766B Distributed power applications schematic. The accuracy of the external reference (U10) sets the accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2% APPLICATIONS INFORMATION (CONTINUED)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 28 DEVELOPMENT HARDWARE & SOFTWARE The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and Windows TM GUI software. It can be ordered on the website or from a local representative. The SMX3200 programming Dongle/cable interfaces directly between a PC’s parallel port and the target application. The device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. The Windows GUI software will generate the data and send it in I 2C serial bus format so that it can be directly downloaded to the SMM766B via the programming Dongle and cable. An example of the connection interface is shown in Figure 15. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 8, Reserved Pin 10, Reserved Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. SMM766B SDA SCL VDD_CAP GND 0.1µFMR# 1N4148 Figure 12 – SMX3200 Programmer I2C serial bus connections to program the SMM766B. Note that the MR# pin does not need to be connected to pin 6 for programming purposes. The latest revisions of all software and an application brief describing the SMX3200 is available from the website at: http://www.summitmicro.com/tech_support/program_kit/SMX3200.htm

Summit Microelectronics, Inc 2122 3.0 5/5/2008 29 SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standar d 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (t HIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 4-bit device type identifier SA[3:0] (slave address) and a 3-bit bus address BA[2:0]. The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMM766B. The device type identifier for the memory array is generally set to 1010 BIN following the industry standard for a typical nonvolatile memory. There is an option to change the identifier to 1011 BIN allowing it to be used on a bus that may be occupied by other memory devices. The configuration registers are grouped with the memory array and thus use 1010 BIN or 1011 BIN as the device type identifier. The command and status registers as well as the 10-bit ADC are accessible with the separate device type identifier of 1001 BIN. The bus address bits BA[1:0] are programmed into the configuration registers. Bu s address bit BA[2] can be programmed as either 0 or biased by the A2 pin. The bus address accessed in the address byte of the serial data stream must match the setting in the SMM766B and on the A2 pin. Any access to the SMM766B on the I 2C bus will temporarily halt the monitoring function. This does not affect the ADOC function, which will continue functioning and control the DC outputs. This is true not only during the monitor mode, but also during power-on and power-off sequencing when the device is monitoring the channels to determine if they have turned on or turned off. The SMM766B halts the monitor function from when it acknowledges the address byte until a valid stop is received. WRITE Writing to the memory or a configuration register is illustrated in Figures 13, 14, 15, 17 and 19. A Start condition followed by the address byte is provided by the host; the SMM766B responds with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMM766B responds with an acknowledge; the host then clocks in on byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive a ddresses within the same page. After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the configuration registers, memory, command and status registers and ADC registers must be set before data can be read from the SMM766B. This is accomplished by a issuing a dummy write command, which is simply a write command that is not followed by a Stop condition. The dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figures 16, 18 and 21 for an illustration of the read sequence. I2C PROGRAMMING INFORMATION

Summit Microelectronics, Inc 2122 3.0 5/5/2008 30 WRITE PROTECTION The SMM766B powers up into a write protected mode. Writing a code to the volatile write protection register can disable the write protection. The write protection register is located at address 87 HEX of slave address 1001BIN. Writing 0101 BIN to bits [7:4] of the write protection register allow writes to the general-purpose memory while writing 0101 BIN to bits [3:0] allow writes to the configuration registers. The write protection can re- enable by writing other codes (not 0101BIN) to the write protection register. Writing to the write protection register is shown in Figure 13. CONFIGURATION REGISTERS The majority of the configuration registers are grouped with the general-purpose memory located at either slave address 1010 BIN or 1011 BIN. Bus address bits BA[2:1] are programmable. The bus address bit BA[0], however, is used to differ entiate the general-purpose memory from the configuration registers and should be set to 1 BIN when accessing the configuration registers . Bus address bit BA[2] can be programmed as a “virtual 0” or biased by the A2 pin. An additional configuration register is located at address 84HEX of slave address 1001BIN. Writing and reading the configuration registers is shown in Figures 14, 15, 16, 17, and 18 Note: Configuration writes or reads of registers 00 HEX to 0FHEX should not be performed while the SMM766B is margining. GENERAL-PURPOSE MEMORY The 2k-bit general-purpose memory is located at either slave address 1010 BIN or 1011 BIN. Bus address bits BA[2:1] are programmable. The bus address bit BA[0], however, is used to differentiate the general- purpose memory from the configuration registers and should be set to 0 BIN when accessing general purpose memory. Bus address bit BA[2] can be programmed as a “virtual 0” or biased by the A2 pin. The word address must be set each time the memory is accessed. Memory writes and reads are shown in Figures 19, 20 and 21. COMMAND AND STATUS REGISTERS The command and status registers are located at slave address 1001 BIN. Writes and reads of the command and status registers are shown in Figures 22 and 23. ADC CONVERSIONS An ADC conversion on any monitored channel can be performed and read over the I 2C bus using the ADC read command. The ADC read command, shown in Figure 24, starts with a dummy write to the 1001 BIN slave address. Bits [6:3] of the word address byte are used to address the desired monitored input. Once the device acknowledges the channel address, it begins the ADC conversion of the addressed input. This conversion requires 182 µs to complete. During this conversion time, acknowledge polling can be used. The SMM766B will not acknowledge the address bytes until the conversion is complete. When the conversion has completed, the SMM766B will acknowledge the address byte and return the 10-bit conversion along with a 4-bit channel address echo. GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMM766B graphical user interface (GUI) is highly recommended. The software is available from the Summit website at: (http://www.summitmicro.com/tech_support/tech.htm# GUI. Using the GUI in conjunction with this datasheet simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMM766B. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I bus protocol. Slave Address Bus Address Register Type 1001BIN BA2 BA1 BA0 Write Protection Register, Command and Status Registers, One Configuration Register, ADC Conversion Readout BA2 BA1 0 2-k Bits of General-Purpose Memory 1010BIN or 1011BIN BA2 BA1 1 Configuration Registers Table 1 - Address bytes used by the SMM766B. I2C PROGRAMMING INFORMATION (CONTINUED)

Summit Microelectronics, Inc 2122 3.0 5/5/2008 35 DEFAULT CONFIGURATION REGISTER SETTINGS – SMM766BFC-752 Register Contents Register Contents Register Contents Register Contents R0 FD R40 FD R96 11 RBD E0 R1 84 R41 9D R97 EC RBE 03 R2 0E R42 0E R98 49 RBF E0 R3 00 R43 2D R99 85 RC0 03 R4 0E R44 0E R9A 81 RC1 38 R5 62 R45 A2 R9B 71 RC2 03 R6 0E R46 0F R9C 29 RC3 38 R7 C7 R47 20 R9D 9A RC4 01 R8 0F R48 0F R9E 11 RC5 90 R9 55 R49 B4 R9F AE RC6 01 RA 0B R4A 0B RA0 49 RC7 90 RB 20 R4B 69 RA1 0A RC8 00 RC FF R4C 00 RA2 80 RC9 00 RD 00 R4D 12 RA3 F6 RCA 00 RE 04 R4E 50 RA4 29 RCB 00 RF 08 R80 4A RA5 5C RCC 03 R10 7F R81 7B RA6 11 RCD FF R11 7F R82 82 RA7 71 RCE 03 R12 7F R83 66 RA8 48 RCF FF R13 7F R84 2A RA9 CD RD0 00 R14 7F R85 CD RAA 80 RD1 00 R15 7F R86 12 RAB B8 RD2 00 R30 7F R87 E1 RAC 29 RD3 00 R31 6E R88 49 RAD 1F RD4 03 R32 0E R89 D7 RB0 11 RD7 D8 R33 DA R8A 81 RB1 33 RE0 00 R34 0E R8B C3 RB2 02 RE1 3D R35 46 R8C 2A RB3 52 RE2 00 R36 0E R8D 29 RB4 03 RE3 3D R37 80 R8E 12 RB5 FF RE4 00 R38 0F R8F 3D RB6 03 RE5 3D R39 08 R90 49 RB7 FF RE6 00 R3A 0F R91 85 RB8 02 RE7 3D R3B D9 R92 81 RB9 23 RE8 00 R3C 00 R93 71 RBA 02 RE9 3D R3D 12 R94 29 RBB 23 REA 00 R3E 50 R95 D7 RBC 03 REB 3D RC1 The default device ordering number is SMM766BFC-752. It is programmed with the register contents as shown above and tested over the commercial temperature range with a VREF setting of 1.25V. Other standard external VREF The value is derived from the customer supplied hex f ile. New device suffix numbers are assigned to non-default requirements. If other VREF values are required, please contact a Summit Microelectronics Sales Representative.

Summit Microelectronics, Inc 2086 2.2 5/1/06 36 PACKAGE A B Pin 1 Indicator Inches (Millimeters) 0.002 - 0.006 (0.05-0.15) MAX.0.047 (1.2) 0.037 - 0.041 0.95 - 1.05 0.018 - 0.030 (0.45 - 0.75) 0.039 (1.00) 0.02 (0.5) BSC 0.007 - 0.011 (0.17 - 0.27) DETAIL "A" DETAIL "B" (B) (A) (A) 0.354 (9.00) BSC 0.276 (7.00) BSC (B)

48 PIN TQFP PACKAGE

Summit Microelectronics, Inc 2122 3.0 5/5/2008 37 PART MARKING Date Code (YYWW) Part Number suffix (Contains Customer specific ordering requirements) Lot tracking code (Summit use) Drawing not to scale xx Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) Product Tracking Code (Summit use) L 100% Sn, RoHS compliant SMM766B F Package F=48 Lead TQFP Summit Part Number Specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. The calibrated VREF voltage settings are standard values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300 nnn Part Number Suffix (see page 35) C Temp Range C=Commercial Blank=Industrial L L = 100% Sn, RoHS compliant Environmental Attribute

Summit Microelectronics, Inc 2122 3.0 5/5/2008 38 Terms and Definitions Fault-Triggered This term refers to either a power -off or force-shutdown operation. When a UV, OV, or sequence termination condition trigger a power-off or force-shutdown a fault triggered power- off or force-shutdown is said to occur. This sets the restart delay at 2.4s, and can limit the number of allowable retries. This term has no correlation to the FAULT pin. Command-Triggered This term refers to either a power-off or force-shutdown operatio n. When either the FS# or PWR_ON pin is asserted or an I2C command is issued a Command-Triggered power-off or force-shutdown is said to occur. This sets the restart delay at 12.5ms, and will not limit the number of allowable retries. ADOC™ ADOC (Active DC Output Control) is a proprietary secondary closed loop compensation control, used to maintain output voltages to ±0.2%. Power-off Power-off sequencing refers to cascaded power-off sequencing unless explicitly noted. Cascaded power-off sequencing refers to a feedback based supply termination in which each channel in the previous sequence position is monitored, and the monitored voltage must fall below a programmable OFF threshold before the next sequence position is allowed to turn off. Channels in the same sequence positi on are not capable of Cascaded power-off sequencing. Power-on Power-off sequencing refers to cascaded power-off sequencing unless explicitly noted. Cascaded power-off sequencing refers to a feedback based supply termination in which each channel in the previous sequence position is monitored, and the monitored voltage must fall below a programmable OFF threshold before the next sequence position is allowed to turn off. Channels in the same sequence position are not capable of Cascaded power-off sequencing. Force-shutdown When all supplies are immediately disabled without regard to sequence position. Sequence-Link™ When more than one SMM766B or SM M766B derivatives are connected creating a seamless multi-channel network. UV Programmed Under Voltage threshol d for monitored channels and supplies OV Programmed Over Voltage threshol d for monitored channels and supplies UVLO Undervoltage Lockout. Prevents voltage at VDD or 12VIN pin from powering the SMM766B until proper operating voltages have been reached. Margin The ability to change the nominal output voltage by use of trim pin. ADC Analog to Digital Converter. Converts anal og voltage to digital voltage. SMM766B represents all measured voltages by 10-bit digital reading. Retries The number of times the SMM766B will rest art after a Fault-Triggered power-off or force- shutdown. Restart When the SMM766B begins power on s equencing, includes initial power-on sequence. Power-on delay Delay from restart timer expiration to PUP Y pin active Power-off delay Programmable delay from VM X off to PUPY inactive Sequence Termination When a supply fails to reach its programmed UV, or OFF, threshold before expiration of internal timer. Monitoring When any quantity including temperature, and voltage is converted to a digital value by the ADC and compared against a user programmable setting. GUI Graphical user interface. Program that reads from and writes to non-volatile registers on the SMM766B and displays results in accordance to register function.

Summit Microelectronics, Inc 2122 3.0 5/5/2008 39 NOTICE Revision 3.0 - This document supersedes all previous versions. SUMMIT Microelectronics, Inc. reserves the ri ght to make changes to the products cont ained in this publication in order to impr ove design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and sche dules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the inform ation in this publication has been carefully checked, SUMMI T Microelectronics, Inc. shall not be liabl e for any damages arising as a result o f any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expe cted to cause any failure of either syst em or to significantly affect their sa fety or effectiveness. Products are not authorized for use in such applications unless SU MMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2007 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER FOR A GREEN PLANET™ ADOC TM and Sequence-Link TM are registered trademarks of Summit Microelectronics Inc., I2C is a trademark of Philips Corporation.

Summary

Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link

Description